Stars
5
stars
written in SystemVerilog
Clear filter
OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
antmicro / verilator
Forked from verilator/verilatorVerilator open-source SystemVerilog simulator and lint system
pulp-platform / ibex
Forked from lowRISC/ibexIbex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.