Neethu Bal Mallya

Doctoral Student, Chalmers University of Technology

I'm a doctoral student at the Chalmers University of Technology supervised by Prof. Ioannis Sourdis and co-supervised by Dr. Bhavishya Goel. Formerly, I was a Researcher advised by Prof. Onur Mutlu at ETH Zürich, and Research Assistant to Prof. Trevor E. Carlson at the National University of Singapore. I obtained my engineering master's and bachelor's degrees in 2015 and 2013 respectively from BITS Pilani.


My research interests include memory systems, near-memory processing, and heterogeneous computing. My recent work focuses on memory subsystems in chiplet-based architectures. I have also explored near-data computing in the context of GPGPUs and 3D-DRAM architectures. Previously, I have worked on designing and building simulation infrastructures, energy-efficient cache memory architectures, and cache coherence protocols.


Education

Chalmers University of Technology, Sweden


Doctor of Philosophy in Computer Science
Aug 2021 - present
Licentiate of Engineering in Computer Science
Aug 2021 - Mar 2025

Thesis: Performance Analysis and Enhancements of Memory Systems for Multi-Chiplet NUMA Architectures [ thesis] [ info]


Birla Institute of Technology and Science Pilani, India


Master of Engineering in Software Systems
Aug 2013 - May 2015
Bachelor of Engineering (Hons.) in Electronics and Instrumentation Engineering
Aug 2009 - May 2013

Research Experience

ETH Zürich, Switzerland

Research Intern, SAFARI Research Group
  • Supervisor : Prof. Onur Mutlu
  • Research areas : Near Data Processing, Processing In Memory, 3D DRAM Architectures
May 2019 - Apr 2020

National University of Singapore, Singapore

Research Assistant, School of Computing
  • Supervisor : Prof. Trevor E. Carlson
  • Research areas : High-efficiency micro-architectures, Simulation infrastructures
Feb 2018 - Jan 2019

BITS Pilani K.K. Birla Goa Campus, India

Research Assistant, Dept. of Computer Science and Information Systems
Jan 2014 - May 2015

Publications

Conference Publications
  • MEMPLEX: A Multi-Chiplet NUMA Architecture with Data Replication and Migration [ paper]
  • Neethu Bal Mallya, Bhavishya Goel and Ioannis Sourdis
  • ACM International Conference on Supercomputing (ICS), 2025

  • A Performance Analysis of Chiplet-Based Systems [ paper]
  • Neethu Bal Mallya, Panagiotis Strikos, Bhavishya Goel, Ahsen Ejaz and Ioannis Sourdis
  • 2025 Design, Automation and Test in Europe Conference and Exhibition (DATE), 2025

  • Simulation based Performance Study of Cache Coherence Protocols [ paper]
  • Neethu Bal Mallya, Geeta Patil and Biju K. Raveendran
  • IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2015

  • Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors Nominated Best Paper [ paper]
  • Neethu Bal Mallya, Geeta Patil and Biju K. Raveendran
  • IEEE International Conference on VLSI Design (VLSID), 2015

Workshop Publications
  • Flexible Timing Simulation of RISC-V Processors with Sniper [ paper] [ slides]
  • Neethu Bal Mallya, Cecilia Gonzalez-Alvarez and Trevor E. Carlson
  • Workshop on Computer Architecture Research with RISC-V (CARRV), 2018

Journal Publications
  • MOESIF: A MC/MP Cache Coherence Protocol with Improved Bandwidth Utilization [ paper]
  • Geeta Patil, Neethu Bal Mallya and Biju K. Raveendran
  • International Journal of Embedded Systems (IJES), 2019


Industry Experience

Morgan Stanley Advantage Services Private Limited, Bangalore, India

Software Engineer (full stack), Enterprise Infrastructure Group
Aug 2015 - Jan 2018

Broadcom Communications Technologies Pvt Ltd, Bangalore, India

Intern
Jan 2013 - Jun 2013

Madras Atomic Power Station, Kalpakkam, India

Intern
May 2011 - Jul 2011

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