After 25+ years of SynthWorks VHDL training funding OSVVM development, I am searching for additional sources of funding for OSVVM. Due to AI, I am not confident that training will continue to be able to fund open source development. On GitHub, I have started a sponsors page. If you would like to sponsor OSVVM, go to https://github.com/OSVVM/OsvvmLibraries and click on the Sponsor’s link in t... »
Problem and Solution In 2026.05, AXI4 Memory is now AXI word width where previously it was byte width. This impacts indirect accesses to the memory using NewID. Use case for older releases (2026.01 and before): vMemID := NewID( Name => MEMORY_NAME, AddrWidth => AXI_ADDR_WIDTH, DataWidth => 8, ParentID => ParentID, Search => NAME ) ; With 2026.05, the call to NewID needs to be updated as follows: v... »
Problem and Solution In 2026.05, if a test case calls SetAxi4Options/GetAxi4Options at time 0 with a parameter other than an AXI4 bus value (such as BRESP) the test case will crash. Problematic use case: ManagerProc : process variable IntOption : integer ; begin -- this process starts at time 0, delta cycle 0 (aka Initialization phase) -- SetAxi4Options or GetAxi4Options access a parameter that is... »
OSVVM release 2026.05 adds the following Script Exit on build done Script Bug Fix: two RunTest when running interactively Script bug: VhdlLsToml Script bug: Simulate and generics Testbench updates to remove Assert WARNING/ERROR from Numeric_Std CoveragePkg Refactor MemoryGenericPkg Support for 64 bit integers AlertLogPkg Use Parent ID DynamicVectorGenericPkg VHDL-2019 Interface Support Ethernet Bu... »
Introduction With the 2026.01 release of OSVVM a new verification component (or VC) was added to support the PCI Express (PCIe) bus protocol. OSVVM already has a comprehensive suite of VCs for both memory mapped address bus protocols, such as AXI, and streaming protocols, such as Ethernet. The PCIe VC extends OSVVM’s supported protocols as part of its ongoing development. However, there is somethi... »
The OSVVM 2026.01 release adds one big feature, PCIe CoSim Verification Component, and numerous smaller updates. PCIe CoSim Verification Component OSVVM now has a co-simulation based PCIe Verification Component thanks to Simon Southwell’s hard work. This reverses the typical co-simulation relationship where software communicates through the MIT interface to an OSVVM VHDL VC. Instead, ... »
Introduction The OSVVM Co-simulation features allow user supplied C or C++ code to drive model independent transaction (MIT) signals in a VHDL logic simulation via a supplied API, as I’ve discussed in a previous blog. When combined with one of the supplied Verification Components (VCs) or with a custom VC, the user software can generate protocol specific signalling to drive a design under te... »
Accelerate your path to adopting OSVVM. OSVVM training is available on-line and on-site. Class details are here On-line classes are live sessions with OSVVM author, Jim Lewis. Through SynthWorks, Mr Lewis has been offering VHDL training for 25+ years and on-line training for 10+ years. So don’t worry, we got this. Your on-line class session will be great. On-line class sessions are of... »
The 2025.06 release adds: Build Directories Tcl procedure CreateTestCaseCommonPkg Tcl procedure RunAllTests Questa – new vs. old script flows Clock edge specification for WaitForClock, WaitForTransaction, … Most VC Test Cases updated Build Directories All build output is now collected into a build directory. The default name for is DirName_ScriptName. Set the name with BuildName... »
The 2024 Wilson Verification survey shows that OSVVM is being used by 35% of all FPGA designers world-wide, which makes OSVVM VHDL’s #1 Verification Methodology. Year after year we have made steady gains on UVM (SystemVerilog) in FPGA Verification. In Europe for FPGA, the 2022 survey showed that OSVVM is used more than UVM (38% to 20%). Here are a few reasons why you should be using O... »