[PDF][PDF] Field-programmable logic and applications

PHW Leong, A Koch, E Boemo - IET Computers & Digital …, 2007 - researchgate.net
… systems, taken from the 16th International Conference on Field Programmable Logic and
Applications (FPL) which was held 28–30 August, 2006 in Madrid, Spain. The papers cover …

Automated hardware-in-the-loop modeling and simulation in active sensor imaging using t16713 dsp units

AB Ramirez, D Rodriguez - 2006 49th IEEE International …, 2006 - ieeexplore.ieee.org
This paper presents a new methodology for the modeling and simulation of active sensor
imaging systems using a hardware-in-the-loop technique based on TI6713 digital signal …

Super fast hardware string matching

CTD Lo, YG Tai, K Psarris… - 2006 IEEE International …, 2006 - ieeexplore.ieee.org
With the appearance of multi-gigabit network infrastructure, a typical network intrusion detection
system (NIDS) has to cope with the network speed. By examining each packet flowing …

[HTML][HTML] FPGA organisation of a block-2 fast path-based predictor

O Cadenas, GM Megson - FPL06: 16th …, 2006 - westminsterresearch.westminster.ac …
… and Megson, GM 2006. Parallel linear hashtable motion estimation algorithm for parallel
video processing. in: International Symposium on Parallel Computing in Electrical Engineering: …

[PDF][PDF] Field Programmable Port Extender (FPX) Reference Testing

JW Lockwood - 2006 - arl.wustl.edu
… [1] PH Jones, JW Lockwood, and YH Cho, “A thermal management and profiling method
for reconfigurable hardware applications,” in 16th Annual Conference on Field Programmable …

Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs

CTD Lo, YG Tai - International Workshop on Applied Reconfigurable …, 2008 - Springer
16th International Conference on Field Programmable Logic and Applications (FPL 2006),
Madrid, SPAIN (August 2006), … In: The 16th International Conference on Field Programmable …

Features, design tools, and application domains of FPGAs

JJ Rodriguez-Andina, MJ Moure… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
2006) illustrates the influence of the number of available MAC units in the bandwidth of a
processing system. Fig. 11(a) depicts the implementation of a 256-coefficient FIR filter when …

Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources

G Caffarena, JA Lopez, C Carreras… - 2006 International …, 2006 - ieeexplore.ieee.org
… using heterogeneous-resource FPGAs," in 16th Int. Conf on Field Programmable Logic
and Applications, FPL '06, 2006. [7] Xilinx Inc., www.xilinx.com. [8] Altera Corp., www.altera.com. …

An FPGA-based accelerator for Fourier Descriptors computing for color object recognition using SVM

F Smach, J Miteran, M Atri, J Dubois, M Abid… - Journal of Real-Time …, 2007 - Springer
Fourier Descriptors (FD) can be used as feature vector components in various applications,
such as real-time color object recognition or image retrieval. The full process is composed of …

[PDF][PDF] Using c-to-hardware acceleration in FPGAs for waveform baseband processing

D Lau, J Blackburn, C Jenkins - 2006 Software …, 2006 - application-notes.digchip.com
Software-defined radio (SDR) architectures typically include general-purpose CPUs (GPPs),
digital signal processing (DSP) ASSPs and FPGAs that process different waveforms, …