A blocker-tolerant, noise-cancelling receiver suitable for wideband wireless applications
A new wideband receiver architecture is proposed that employs two separate passive-mixer-based
downconversion paths, which enables noise cancelling, but avoids voltage gain at …
downconversion paths, which enables noise cancelling, but avoids voltage gain at …
A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure
As narrowband off-chip RF filtering is not compatible with the concept of software-defined
radio (SDR), an SDR receiver must be designed to tolerate large out-of-band blockers with …
radio (SDR), an SDR receiver must be designed to tolerate large out-of-band blockers with …
Relationship between endothelial cell loss and microcoaxial phacoemulsification parameters in noncomplicated cataract surgery
…, MZ Eid, MAB Mohammed, A Hafez… - Clinical …, 2012 - Taylor & Francis
Purpose To assess the relationship between postoperative endothelial cell loss and
microcoaxial phaco parameters using Ozil IP (Alcon Laboratories, Inc, Fort Worth, TX) in …
microcoaxial phaco parameters using Ozil IP (Alcon Laboratories, Inc, Fort Worth, TX) in …
A 32–48 Gb/s serializing transmitter using multiphase serialization in 65 nm CMOS technology
A power-efficient transmitter is proposed using a multiphase serializer, multiphase dividers
using injection-locked oscillators, and a high-speed multiplexing structure to relax the timing …
using injection-locked oscillators, and a high-speed multiplexing structure to relax the timing …
Scalability and design-space analysis of a 1T-1MTJ memory cell for STT-RAMs
We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ)
characteristics and target memory specifications, to explore the design margin of a one-…
characteristics and target memory specifications, to explore the design margin of a one-…
A 0.1–1.5 GHz 8-bit inverter-based digital-to-phase converter using harmonic rejection
This paper presents a digital-to-phase converter (DPC) with 8-bits of resolution and a wide
frequency range for the input/output clocks. A harmonic rejection (HR) filter is introduced to …
frequency range for the input/output clocks. A harmonic rejection (HR) filter is introduced to …
Design and optimization of multipath ring oscillators
Multipath ring oscillators have been used to generate multiple clock phases and higher
oscillation frequencies. This paper presents a modified linear analysis to find an accurate …
oscillation frequencies. This paper presents a modified linear analysis to find an accurate …
[PDF][PDF] Low-Noise Monolithic Frequency Synthesizers for
AN Hafez - uwspace.uwaterloo.ca
The wireless market is currently experiencing a huge growth in terms of both the number of
users and the range of services offered. With this growth, there is an acute demand for …
users and the range of services offered. With this growth, there is an acute demand for …
A 4.6 GHz MDLL with− 46dBc reference spur and aperture position tuning
Multiplying delay-locked loops (MDLLs) have been shown to have improved jitter accumulation
and tracking over VCO-based PLLs. By injecting the reference clock edge into the VCO …
and tracking over VCO-based PLLs. By injecting the reference clock edge into the VCO …
A 3.8 mW/Gbps quad-channel 8.5–13 Gbps serial link with a 5 tap DFE and a 4 tap transmit FFE in 28 nm CMOS
…, U Singh, M Abdul-Latif, Y Liu, AA Hafez… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
This paper presents a quad-lane serial transceiver that supports virtually all data center
communication standards around 8.5-13 Gbps, implemented in 28 nm CMOS technology. The …
communication standards around 8.5-13 Gbps, implemented in 28 nm CMOS technology. The …