An FPGA chip identification generator using configurable ring oscillators

H Yu, PHW Leong, Q Xu - … on very large scale integration (VLSI …, 2011 - ieeexplore.ieee.org
Physically unclonable functions (PUF) are commonly used in applications such as hardware
security and intellectual property protection. Various PUF implementation techniques have …

Towards a unique FPGA-based identification circuit using process variations

H Yu, PHW Leong, H Hinkelmann… - … Conference on Field …, 2009 - ieeexplore.ieee.org
A compact chip identification (ID) circuit with improved reliability is presented. Ring oscillators
are used to measure the spatial process variation and the ID is based on their relative …

Fine-grained characterization of process variation in FPGAs

H Yu, Q Xu, PHW Leong - 2010 International Conference on …, 2010 - ieeexplore.ieee.org
As semiconductor manufacturing continues towards reduced feature sizes, yield loss due to
process variation becomes increasingly important. To address this issue on FPGA platforms, …

A detailed delay path model for FPGAs

E Hung, SJE Wilton, H Yu, TCP Chau… - … Conference on Field …, 2009 - ieeexplore.ieee.org
A complete circuit-level description of a representative FPGA is presented in this paper, from
which a simple RC delay model as a function of architectural and technology parameters is …

HTOutlier: Hardware Trojan detection with side-channel signature outlier identification

J Zhang, H Yu, Q Xu - … on Hardware-Oriented Security and Trust, 2012 - ieeexplore.ieee.org
Hardware Trojan (HT) is a growing concern for the semiconductor industry. As a non-invasive
and inexpensive approach, side-channel analysis methods based on signatures such as …

The Interaction of lncRNA XLOC-2222497, AKR1C1, and Progesterone in Porcine Endometrium and Pregnancy

T Su, H Yu, G Luo, M Wang, C Zhou, L Zhang… - International Journal of …, 2020 - mdpi.com
The endometrium is an important tissue for pregnancy and plays an important role in
reproduction. In this study, high-throughput transcriptome sequencing was performed in …

FPGA interconnect design using logical effort

H Yu, YH Chan, PHW Leong - 2008 International Conference …, 2008 - ieeexplore.ieee.org
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology
independent manner. It offers the potential to simplify delay models for FPGAs and gain more …

On timing yield improvement for fpga designs using architectural symmetry

H Yu, Q Xu, PHW Leong - 2011 21st International Conference …, 2011 - ieeexplore.ieee.org
As semiconductor manufacturing technology continues towards reduced feature sizes,
timing yield will degrade due to increased process variation. This work proposes the use of …

[HTML][HTML] HER2 and Epigenetic Modifications in Tumorigenesis: Mechanisms and Therapeutic Implications

Z Ye, H Yu, L Zhu, X Fan, A Lin, X Wang - 2025 - intechopen.com
Human epidermal growth factor receptor 2 (HER2) is a transmembrane tyrosine kinase
receptor that plays a pivotal role in the development and progression of cancers, particularly in …

Coda: A concurrent online delay measurement architecture for critical paths

Y Zhang, H Yu, Q Xu - 17th Asia and South Pacific Design …, 2012 - ieeexplore.ieee.org
With technology scaling, integrated circuits behave more unpredictably due to process variation,
environmental changes and aging effects. Various variation-aware and adaptive design …