A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS
T Kim, SD Lee, J Park, H Cho, B You… - … Solid-State Circuits …, 2011 - ieeexplore.ieee.org
As the NAND flash memory market grows rapidly due to various applications, such as USB
devices, MP3 players, SSDs, cellular phones, and cameras, there is a requirement for high-…
devices, MP3 players, SSDs, cellular phones, and cameras, there is a requirement for high-…
Antifuse EPROM circuit for field programmable DRAM
JS Choi, JK Wee, HY Cho, PJ Kim… - … Solid-State Circuits …, 2000 - ieeexplore.ieee.org
A 3 V EPROM circuit is implemented in an existing 0.22 /spl mu/m DRAM process with an
antifuse based on destructive breakdown of the highly-reliable 6.5 nm oxide-nitride-oxide (ONO…
antifuse based on destructive breakdown of the highly-reliable 6.5 nm oxide-nitride-oxide (ONO…
Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications
SC Park, YS Kim, HY Cho, SD Choi, MS Yoon… - ETRI …, 2014 - Wiley Online Library
In current NAND flash design, one of the most challenging issues is reducing peak current
consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in …
consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in …
An effective routing methodology in the era of 0.2/spl mu/m and beyond technologies for reducing the DRAM design cost
JK Wee, PJ Kim, HY Cho, JK Oh… - AP-ASIC'99. First …, 1999 - ieeexplore.ieee.org
The optimum routing methodology for high-performance and fast-layout time DRAM design
in the era beyond 0.2 /spl mu/m technology is investigated. The key attributes of the …
in the era beyond 0.2 /spl mu/m technology is investigated. The key attributes of the …
Scaling challenge of self-aligned STI cell (SA-STI cell) for NAND flash memories
S Aritome, T Kikkawa - Solid-state electronics, 2013 - Elsevier
This paper describes scaling limitations and challenges of Self-Aligned STI cell (SA-STI cell)
over 2X–0Xnm generations for NAND flash memories. The scaling challenges are …
over 2X–0Xnm generations for NAND flash memories. The scaling challenges are …
Study of NAND Flash Memory Cells
有留誠一 - 2013 - hiroshima.repo.nii.ac.jp
This paper presents the device technologies of NAND Flash memory to realize low bit cost
and high reliability. First, planar (two-dimensional) NAND Flash memory cells are discussed. …
and high reliability. First, planar (two-dimensional) NAND Flash memory cells are discussed. …