Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory
J Jang, HS Kim, W Cho, H Cho, J Kim… - 2009 symposium on …, 2009 - ieeexplore.ieee.org
Vertical NAND flash memory cell array by TCAT (Terabit Cell Array Transistor) technology is
proposed. Damascened metal gate SONOS type cell in the vertical NAND flash string is …
proposed. Damascened metal gate SONOS type cell in the vertical NAND flash string is …
Three dimensionally stacked NAND flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30nm node
For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by
implementing S3 (Single-crystal Si layer Stacking ) technology, which was used to develop S3 …
implementing S3 (Single-crystal Si layer Stacking ) technology, which was used to develop S3 …
Highly cost effective and high performance 65nm S/sup 3/(stacked single-crystal Si) SRAM technology with 25F/sup 2/, 0.16 um/sup 2/cell and doubly stacked SSTFT …
…, H Park, C Chang, S Lee, J Yun, W Cho… - Digest of Technical …, 2005 - ieeexplore.ieee.org
In order to meet the great demands for higher density SRAM in all area of SRAM
applications, the 25F/sup 2/S/sup 3/ (stacked single-crystal Si ) SRAM cell, which is a truly 3-…
applications, the 25F/sup 2/S/sup 3/ (stacked single-crystal Si ) SRAM cell, which is a truly 3-…
Highly area efficient and cost effective double stacked S/sup 3/(stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density …
SM Jung, H Lim, W Cho, H Cho, C Yeo… - IEDM Technical …, 2004 - ieeexplore.ieee.org
For the first time, the highest density SRAM, such as 512M bit SRAM, is developed by
implementing the smallest 25F/sup 2/S/sup 3/ SRAM cell technology, whose cell size is 0.16/spl mu…
implementing the smallest 25F/sup 2/S/sup 3/ SRAM cell technology, whose cell size is 0.16/spl mu…
A 45nm 4Gb 3-dimensional double-stacked multi-level NAND flash memory with shared bitline structure
…, D Kim, S Hwang, M Kang, H Cho… - … Solid-State Circuits …, 2008 - ieeexplore.ieee.org
Recently, 3-dimensional (3D) memories have regained attention as a potential future memory
solution featuring low cost, high density and high performance. We present a 3D double …
solution featuring low cost, high density and high performance. We present a 3D double …
Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure
W Cho, SI Shim, J Jang, H Cho, BK You… - 2010 Symposium on …, 2010 - ieeexplore.ieee.org
The performance and reliability of 3-D NAND cells fabricated by TCAT (Terabit Cell Array
Transistor) technology have been improved significantly via a damascened metal gates and a …
Transistor) technology have been improved significantly via a damascened metal gates and a …
A fully performance compatible 45 nm 4-gigabit three dimensional double-stacked multi-level NAND flash memory with shared bit-line structure
A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with
shared bitline structure have successfully developed. The device is fabricated by 45 nm floating…
shared bitline structure have successfully developed. The device is fabricated by 45 nm floating…
65nm high performance SRAM technology with 25F2 0.16/spl mu/m/sup 2/S/sup 3/(stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high …
…, W Cho, J Park, B Son, J Jeong, H Cho… - Proceedings of 35th …, 2005 - ieeexplore.ieee.org
For the first time, the 65nm high performance transistor technology and the highly compacted
double stacked S/sup 3/ SRAM cell with a size of 25F/sup 2/, and 0.16/spl mu/m/sup 2/ has …
double stacked S/sup 3/ SRAM cell with a size of 25F/sup 2/, and 0.16/spl mu/m/sup 2/ has …
Soft error immune 0.46/spl mu/m/sup 2/SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM
SM Jung, H Lim, W Cho, H Cho, H Hong… - IEEE International …, 2003 - ieeexplore.ieee.org
The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim
mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm …
mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm …
[CITATION][C] Yangsoo Son, Junbeom Park, Min-Sung Song, Kyoung-Hon Kim, Jin-Soo Lim, and Kinam Kim. Three dimensionally stacked nand ash memory technology …
SM Jung, J Jang, W Cho, H Cho, J Jeong, Y Chang… - Electron Devices Meeting, 2006