A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming
H Nobukata, S Takagi, K Hiraga… - IEEE Journal of Solid …, 2000 - ieeexplore.ieee.org
We report a fast-programming, compact sense and latch (SL) circuit to realize an eight-level
NAND flash memory. Fast programming is achieved by supplying optimized voltage and …
NAND flash memory. Fast programming is achieved by supplying optimized voltage and …
A variation-aware MTJ store energy estimation model for edge devices with verify-and-retryable nonvolatile flip-flops
…, D Yokoyama, K Usami, K Hiraga… - … Transactions on Very …, 2023 - ieeexplore.ieee.org
While the spin-transfer torque (STT) magnetic tunnel junction (MTJ) is a promising technique
for enabling nonvolatile flip-flops (NVFFs) to perform power gating to reduce leakage power …
for enabling nonvolatile flip-flops (NVFFs) to perform power gating to reduce leakage power …
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops
…, H Miyauchi, K Usami, K Hiraga… - 2021 IEEE 14th …, 2021 - ieeexplore.ieee.org
In this study, a second-generation coarse-grained reconfigurable array with non-volatile flip-flops
(NVFFs), known as the non-volatile cool mega array with multi-context (NVCMA/MC), is …
(NVFFs), known as the non-volatile cool mega array with multi-context (NVCMA/MC), is …
Proposal for Non-Volatilization of Logic Cell Architecture for eFPGA IP
K Hiraga, K Seto, K Bessho, M Iida - IPSJ Transactions on System …, 2025 - jstage.jst.go.jp
As eFPGAs shift from hard IP to soft IP, this study presents the non-volatilization of PAE, a
new programmable logic cell architecture replacing conventional LUTs. PAE achieves high …
new programmable logic cell architecture replacing conventional LUTs. PAE achieves high …
Proposal for Non-Volatilization of eFPGA Core
K Hiraga, K Seto, K Bessho… - 2025 IEEE Symposium on …, 2025 - ieeexplore.ieee.org
In the development of embedded FPGA (eFPGA), a novel programmable AND logic cell
architecture termed programmable AND element (PAE) has been reported to reduce the …
architecture termed programmable AND element (PAE) has been reported to reduce the …
Optimized two-step store control for MTJ-based nonvolatile flip-flops to minimize store energy under process and temperature variations
Introducing a magnetic tunneling junction (MTJ) into a flip-flop enables nonvolatile power
gating (PG) but large store energy to MTJ is a critical concern. We propose an optimized two-…
gating (PG) but large store energy to MTJ is a critical concern. We propose an optimized two-…
Energy efficient write verify and retry scheme for MTJ based flip-flop and application
…, M Kudo, H Amano, T Ikezoe, K Hiraga… - 2018 IEEE 7th Non …, 2018 - ieeexplore.ieee.org
A non-volatile flip-flop (NVFF) introducing MTJ has many strong points in high endurance and
read/write performance, and hence is very attractive as a component to be used for power …
read/write performance, and hence is very attractive as a component to be used for power …
A non-stop fault-tolerant real-time system-on-chip/system-in-package
…, N Yamasaki, K Suzuki, K Hiraga… - … on Computing and …, 2023 - ieeexplore.ieee.org
Today, embedded real-time systems such as automobiles, spacecraft, and sensor networks
are parts of social infrastructures. Since a system failure in these systems may lead to a …
are parts of social infrastructures. Since a system failure in these systems may lead to a …
A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops
…, J Akaike, K Usami, M Kudo, K Hiraga… - 2018 International …, 2018 - ieeexplore.ieee.org
Recent IoT devices are required to be an extremely low power in idle time, while a certain
performance is required in active time. NVCMA (Non-volatile Cool Mega Array) is a coarse-…
performance is required in active time. NVCMA (Non-volatile Cool Mega Array) is a coarse-…
A 144 Mb 8-level NAND flash memory with optimized pulse width programming
H Nobukata, S Takagi, K Hiraga… - 1999 Symposium on …, 1999 - ieeexplore.ieee.org
Recently, the demand for high density flash memory for mass storage applications has grown.
The most effective approach to improve memory density is a multi-level cell, however, the …
The most effective approach to improve memory density is a multi-level cell, however, the …