LVDS serial AER link performance

L Miro-Amarante, A Jiménez-Fernandez… - … on Circuits and …, 2007 - ieeexplore.ieee.org
… This paper presents a testing platform for AER systems that allows analysing a LVDS
Serial AER link produced by a Spartan 3 FPGA, or by a commercial LVDS transceiver. The …

An AER handshake-less modular infrastructure PCB with x8 2.5 Gbps LVDS serial links

T Iakymchuk, A Rosado… - … on Circuits and …, 2014 - ieeexplore.ieee.org
… in detail the LVDS serial interface and presenting its performance. … call “AER-Node” PCB,
for high speed serial communications between boards that does not limit the performance of …

LVDS interface for AER links with burst mode operation capability

C Zamarreno-Ramos… - … on Circuits and …, 2008 - ieeexplore.ieee.org
… simulation of a serial AER LVDS communication link. It converts … LVDS-AER link has been
implemented in a 90 nm STMicroelectronics technology and simulated to verify its performance

High-speed serial AER on FPGA

HKO Berge, P Hafliger - 2007 IEEE International Symposium …, 2007 - ieeexplore.ieee.org
… Developing a high performance LVDS serial transceiver on a custom … of LVDS serial
links, and their applicability to AER signaling, we implemented a parallel to serial and serial to …

On multiple AER handshaking channels over high-speed bit-serial bidirectional LVDS links with flow-control and clock-correction on commercial FPGAs for scalable …

A Yousefzadeh, M Jabłoński… - IEEE transactions on …, 2017 - ieeexplore.ieee.org
LVDS links have also been reported recently using either current-mode [22] or voltage-mode
[23] drivers.These use 4 wires: two for high-speed 1GHz bit-serial LVDSperformance of up …

An instant-startup jitter-tolerant Manchester-encoding serializer/deserializer scheme for event-driven bit-serial LVDS interchip AER links

C Zamarreno-Ramos… - … on Circuits and …, 2011 - ieeexplore.ieee.org
… some nonVLSI serial AER realizations. Table I compares the performance figures of several
… Other researchers have reported serial LVDS links developed specially for AER systems, …

A 1.5 ns OFF/ON switching-time voltage-mode LVDS driver/receiver pair for asynchronous AER bit-serial chip grid links with up to 40 times event-rate dependent …

C Zamarreno-Ramos, R Kulkarni… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
This paper presents a low power fast ON/OFF switchable voltage mode implementation of a
driver/receiver pair intended to be used in high speed bit-serial Low Voltage Differential …

Low power LVDS transceiver for AER links with burst mode operation capability

C Zamarreno-Ramos, T Serrano-Gotarredona… - 2009 - digital.csic.es
LVDS transceiver intended to be used in serial AER links. Traditional implementations of
LVDS serial … 90 nm STMicroelectronics technology and simulated to verify its performance. The …

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems

N Qiao, G Indiveri - 2018 24th IEEE International Symposium on …, 2018 - ieeexplore.ieee.org
AER data transmission in neuromorphic systems calls for the development of a new fully
asynchronous clock-less event-based switchable bit-serial AER LVDS link… shows a performance

Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems

A Yousefzadeh, M Jabłoński… - … on Circuits and …, 2017 - ieeexplore.ieee.org
AER links use parallel physical wires together with a pair of handshaking signals (Request
and Acknowledge). Here we present a fully serial … for testing link performance between two …