Reliability-aware runahead
A Naithani, L Eeckhout - 2022 IEEE International Symposium …, 2022 - ieeexplore.ieee.org
… runahead execution and by initiating runahead execution early. Across a set of memory-intensive
applications — the primary target for runahead … We explore the runahead design space …
applications — the primary target for runahead … We explore the runahead design space …
Amdahl's law for lifetime reliability scaling in heterogeneous multicore processors
WJ Song, S Mukhopadhyay… - 2016 IEEE international …, 2016 - ieeexplore.ieee.org
Heterogeneous multicore processors have been suggested as alternative microarchitectural
designs to enhance performance and energy efficiency. Using Amdahl's Law, …
designs to enhance performance and energy efficiency. Using Amdahl's Law, …
On performance optimization and quality control for approximate-communication-enabled networks-on-chip
… The runahead NoC [34] relaxes the constraint of lossless communication by using an additional
… His research interests include power-efficient and reliabilityaware design for network-on-…
… His research interests include power-efficient and reliabilityaware design for network-on-…
Evaluating the Effectiveness of Microarchitectural Hardware Fault Detection for Application-Specific Requirements
KN Papadopoulos, C Giannoula… - arXiv preprint arXiv …, 2024 - arxiv.org
Reliability is necessary in safety-critical applications spanning numerous domains. Conventional
hardware-based fault tolerance techniques, such as component redundancy, ensure …
hardware-based fault tolerance techniques, such as component redundancy, ensure …
Adaptive cache design to enable reliable low-voltage operation
The performance/energy trade-off is widely acknowledged as a primary design consideration
for modern processors. A less discussed, though equally important, trade-off is the reliability…
for modern processors. A less discussed, though equally important, trade-off is the reliability…
Achieving flexible global reconfiguration in NoCs using reconfigurable rings
… load latency is not as low as SMART and Runahead for most of the synthetic traffic patterns.
The … His research interests include power-efficient and reliability-aware design for network-on…
The … His research interests include power-efficient and reliability-aware design for network-on…
Enabling atomic durability for persistent memory with transiently persistent cpu cache
Persistent memory (pmem) products bring the persistence domain up to the memory level.
Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU …
Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU …
A deflection-based deadlock recovery framework to achieve high throughput for faulty nocs
… His research interests include reliability-aware design for network-on-chip and many-core …
His research interests include power-efficient and reliability-aware design for network-on-chip …
His research interests include power-efficient and reliability-aware design for network-on-chip …
[BOOK][B] Fault tolerant computer architecture
D Sorin - 2009 - books.google.com
For many years, most computer architects have pursued one primary goal: performance.
Architects have translated the ever-increasing abundance of ever-faster transistors provided by …
Architects have translated the ever-increasing abundance of ever-faster transistors provided by …
Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence Domain
Persistent memory (pmem) products bring the persistence domain up to the memory level.
Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU …
Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU …