User profiles for Wonsun Ahn
Wonsun AhnUniversity of Pittsburgh Verified email at cs.pitt.edu Cited by 681 |
POSH: a TLS compiler that exploits program structure
As multi-core architectures with Thread-Level Speculation (TLS) are becoming better understood,
it is important to focus on TLS compilation. TLS compilers are interesting in that, while …
it is important to focus on TLS compilation. TLS compilers are interesting in that, while …
Improving JavaScript performance by deconstructing the type system
Increased focus on JavaScript performance has resulted in vast performance improvements
for many benchmarks. However, for actual code used in websites, the attained …
for many benchmarks. However, for actual code used in websites, the attained …
BulkCompiler: High-performance sequential consistency through cooperative compiler and hardware support
A platform that supported Sequential Consistency (SC) for all codes --- not only the well-synchronized
ones --- would simplify the task of programmers. Recently, several hardware …
ones --- would simplify the task of programmers. Recently, several hardware …
Live code update for IoT devices in energy harvesting environments
The number of Internet of Things (IoT) devices is exhibiting explosive growth. These devices
are often closely coupled to the physical world, and may harvest energy as a power source, …
are often closely coupled to the physical world, and may harvest energy as a power source, …
A depth-aware swap insertion scheme for the qubit mapping problem
The rapid progress of physical implementation of quantum computers paved the way of realising
the design of tools to help users write quantum programs for any given quantum devices…
the design of tools to help users write quantum programs for any given quantum devices…
SoftSig: software-exposed hardware signatures for code analysis and optimization
Many code analysis techniques for optimization, debugging, or parallelization need to perform
runtime disambiguation of sets of addresses. Such operations can be supported efficiently …
runtime disambiguation of sets of addresses. Such operations can be supported efficiently …
Scalablebulk: Scalable cache coherence for atomic blocks in a lazy environment
Recently-proposed architectures that continuously operate on atomic blocks of instructions (also
called chunks) can boost the programmability and performance of shared-memory …
called chunks) can boost the programmability and performance of shared-memory …
The bulk multicore architecture for improved programmability
… BY JoSEP toRRELLaS, LuiS CEzE, JamES tuCK, CaLin CaSCaVaL, PaBLo montESinoS,
WonSun ahn, anD miLoS PRVuLoViC … Wonsun Ahn (dahn2@uiuc.edu) is a graduate …
WonSun ahn, anD miLoS PRVuLoViC … Wonsun Ahn (dahn2@uiuc.edu) is a graduate …
Dynamically detecting and tolerating if-condition data races
An IF-Condition Invariance Violation (ICIV) occurs when, after a thread has computed the
control expression of an IF statement and while it is executing the THEN or ELSE clauses, …
control expression of an IF statement and while it is executing the THEN or ELSE clauses, …
[PDF][PDF] Automated Fingerprinting of Performance Pathologies Using Performance Monitoring Units ({{PMUs}})
Modern architectures provide access to many hardware performance events, which are
capable of providing insight into architectural performance bottlenecks throughout the core and …
capable of providing insight into architectural performance bottlenecks throughout the core and …