A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
…, D Murray, N Vallepalli, Y Wang… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
Column-based dynamic power supply has been integrated into a high-frequency 70-Mb
SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully …
SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully …
15.3 A 351TOPS/W and 372.4 GOPS compute-in-memory SRAM macro in 7nm FinFET CMOS for machine-learning applications
Compute-in-memory (CIM) parallelizes multiply-and-average (MAV) computations and
reduces off-chip weight access to reduce energy consumption and latency, specifically for Al …
reduces off-chip weight access to reduce energy consumption and latency, specifically for Al …
16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications
…, K Akarvardar, HJ Liao, Y Wang… - … Solid-State Circuits …, 2021 - ieeexplore.ieee.org
From the cloud to edge devices, artificial intelligence (AI) and machine learning (ML) are
widely used in many cognitive tasks, such as image classification and speech recognition. In …
widely used in many cognitive tasks, such as image classification and speech recognition. In …
Thermal explosion hazards on 18650 lithium ion batteries with a VSP2 adiabatic calorimeter
Thermal abuse behaviors relating to adiabatic runaway reactions in commercial 18650 lithium
ion batteries (LiCoO 2 ) are being studied in an adiabatic calorimeter, vent sizing package …
ion batteries (LiCoO 2 ) are being studied in an adiabatic calorimeter, vent sizing package …
A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous …
…, TL Chou, ME Sinangil, Y Wang… - … Solid-State Circuits …, 2022 - ieeexplore.ieee.org
Computing-in-memory (CIM) is being widely explored to minimize power consumption in
data movement and multiply-and-accumulate (MAC) for edge-AI devices. Although most prior …
data movement and multiply-and-accumulate (MAC) for edge-AI devices. Although most prior …
Thermal runaway potential of LiCoO2 and Li (Ni1/3Co1/3Mn1/3) O2 batteries determined with adiabatic calorimetry methodology
Thermal runaway hazards related to adiabatic runaway reactions in various 18650 Li-ion
batteries were studied in an adiabatic calorimeter with vent sizing package 2 (VSP2). We …
batteries were studied in an adiabatic calorimeter with vent sizing package 2 (VSP2). We …
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
…, D Murray, N Vallepalli, Y Wang… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl
mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage …
mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage …
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry
Future product applications demand increasing performance with reduced power consumption,
which motivates the pursuit of high-performance at reduced operating voltages. Random …
which motivates the pursuit of high-performance at reduced operating voltages. Random …
An RNN-based prosodic information synthesizer for Mandarin text-to-speech
SH Chen, SH Hwang, YR Wang - IEEE transactions on speech …, 1998 - ieeexplore.ieee.org
A new RNN-based prosodic information synthesizer for Mandarin Chinese text-to-speech (TTS)
is proposed in this paper. Its four-layer recurrent neural network (RNN) generates …
is proposed in this paper. Its four-layer recurrent neural network (RNN) generates …
A 7-nm compute-in-memory SRAM macro supporting multi-bit input, weight and output and achieving 351 TOPS/W and 372.4 GOPS
In this work, we present a compute-in-memory (CIM) macro built around a standard two-port
compiler macro using foundry 8T bit-cell in 7-nm FinFET technology. The proposed design …
compiler macro using foundry 8T bit-cell in 7-nm FinFET technology. The proposed design …