Search Results for "automation"
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Showing 7 open source projects for "automation"
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SciTECO
Advanced TECO dialect and interactive screen editor based on Scintilla
SciTECO is an interactive TECO dialect, similar to Video TECO. It also adds features from classic TECO-11, as well as unique new ideas. Project development takes place here: https://git.fmsbw.de/sciteco The download archive is mirrored at Sourceforge, but for nightly builds check out: https://sciteco.fmsbw.de/downloads/nightly/ -
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Madedit-Mod
MadEdit-Mod is a cross platform Text/Hex editor based on MadEdit
Madedit-Mod is a cross platform text/hex editor base on MadEdit with a log of critical bug fix from me or other developers. A lot of new features were added, such as Drag-Drop Edit(cross platform), Highlight word, etc. The reason that I maintained this project is that the author of MadEdit had not worked on it for for a long time and I really like it and need more features. Find more information on Wiki pages. Currently supported Languages: English Chinese Simplified... -
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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RPTParse
Quartus project compilation reports parsing tool
Altera Quartus creates .rpt files during synthesis, place&route and bitstream generation stages of FPGA project compilation. Verification engineer checks these reports, finds warning messages and put them into own report. But big projects can contain a lot of warnings, and manual warning search is very boring and long process. That's why this parsing tool was created. This software parse report file, classifies warning types and place them into own report, where types of warnings and their... -
Our Free Plans just got better! | Auth0You asked, we delivered! Auth0 is excited to expand our Free and Paid plans to include more options so you can focus on building, deploying, and scaling applications without having to worry about your security. Auth0 now, thank yourself later.
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PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
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Provides a set of Python scripts that allow client apps to automate Notepad++ using the excellent Python Script plugin and the Python SimpleXMLRPC modules. Demo apps in IronPython, C#, and now a "pure"-Python2.7 console app. No .Net required!
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Analysis and improvement of text documents. Helps choosing appropriate words, checks against dictionaries and glossaries.
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