Should veditor 0.5.0 be supporting `ifdef?
In an ASIC dev there are ifdefs to choose target platform; like FPGA emulation real ASIC.
How about module declarations with parameters, such as:
module new #( parameter pin1, parameter pin2) (
input blah,
output blah
);
It is very odd that it will create instantiations with this notation but now allow a module declaration with it.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Logged In: NO
I would like to see SystemVerilog support.
Logged In: YES
user_id=986836
veditor 0.3.2 supports Verilog-2001 language specific
parser. System Verilog is not supported yet.
Logged In: NO
Are multidimensional arrays supported on veditor 0.3.2
parser?
Logged In: YES
user_id=986836
Do you mean this?
reg [15:0] array [0:255][0:255];
Unfortunately it is not supported. I will support it in
next release.
Logged In: YES
user_id=1669512
Originator: NO
Should veditor 0.5.0 be supporting `ifdef?
In an ASIC dev there are ifdefs to choose target platform; like FPGA emulation real ASIC.
How about module declarations with parameters, such as:
module new #( parameter pin1, parameter pin2) (
input blah,
output blah
);
It is very odd that it will create instantiations with this notation but now allow a module declaration with it.