Merge Turkish translations update
Fix typo in translation for number of copies
Update Turkish translations in qtgeneric_tr.ts
Refine Turkish translations in qtgeneric_tr.ts
Is there a version for Apple Silicone. I have a Mac Mini M4.
improve wire label dump/parse
fix port access in position dump
fix position in graphics item dump
dump wire labels as nodes
cleanup Schematic::dumpVerilogComponent
fix comment
bump ref. missing connections
Reading Verilog: Wire labels
Update Tests: Verilog Dump
Verilog Dump: Dump Wire Label position
net label test
fix indent. went wrong in 386426dd8eaf
Removing unused code
test status
Parse attribut DRY fix
Merge preamble
Introducing preample loading
Fix DRY violation
Element "center and relative boundings" are private
Merge experimental Verilog-S dump/load
Verilog Parsing: Parse visibility
Regenerating Verilog Schematics
create sch and vs round trip diffs during tests
superficial testing
Verilog Schematic: Visibility of properties
Paintings: Introducing setter and getter for attributes
sync ctos with gnucap/develop & test
fix S__text type
ROADMAP, TODO update
cleanup prj_log_compiler
Verilog Dump: Painting/GraphicText dumping
Updating the Verilog schematics
bugfix lang_verilog. always prefer qucs_type attribute
fix include in lang_verilog
errors and warnings in component
Adding integrity check
Add label name getter method
Write nodes out as wires
fix compile warnings, add Wire::port
Add a warn method to Schematic
Add nodename_at function
Adding set_port_by index functionality
Bug fix: Solving save-as issue
Bugfix: Open .vs files as schematic
fix qt rules in various qucs-*/Makefile.am
Merge 'comp_loading'
Using dump/parse identifier from Gnucap
missing lib test
Positioning components without ports
more cleanup
Move code over to correct compilation unit
smart pointer conversion fix
Merge wire_cleanup
cleanup node interface a bit
missing test file
split off LegacyComponent
move up "Component" class
prepare Wire ports cleanup
hello world ngspice
hello world example
more Verilog_File cleanup and disentangle
"Verilog" device. initial fixes
some more parameters are attributes
Makefile fixes
Merge wire placement
Initial code for wire placement
Component placement
Merge 'lib'
cleanup/fix Sub
cleanup/fix Lib
more
Merge read_verilog
fix parameter parsing
fix out of range Props access, try #2
Solve crash when dumping netlists/fix refs
fix compile warnings
Solving uninitialized value warning
cleanup, disentangle dumpDeclaration
cleanup, disentangle dumpDeclaration
Verilog Dump: Change order
Component "text position" is private
Solving ref bug: Text position to zero
add missing ref for unittests
reopen QTextStream after file.reset
trying to narrow down on bogus QTextStream::atEnd
import vanilla trace header, trace readVerilog
review readVerilog
Schematic::readVerilog
review lang_verilog.cpp
Add separate files for verilog reading
review Component::attr_get & bump ref
back out Component::set_attribute
Verilog Dump/Parsing: Qucs metadata
annotate few bugs. plans.
cherry pick from 8448e366cb597e, review