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High-Performance CMOS Current Mirrors: Application To Linear Voltage-to-Current Converter Used For Two-Stage Operational Amplifier

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151 views6 pages

High-Performance CMOS Current Mirrors: Application To Linear Voltage-to-Current Converter Used For Two-Stage Operational Amplifier

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Shaheer Durrani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Circuits and Systems, 2012, 3, 311-316

http://dx.doi.org/10.4236/cs.2012.34044 Published Online October 2012 (http://www.SciRP.org/journal/cs)

High-Performance CMOS Current Mirrors: Application


to Linear Voltage-to-Current Converter Used for
Two-Stage Operational Amplifier
Radwene Laajimi, Mohamed Masmoudi
Department of Electrical Engineering Electronics, Micro-Technology and Communication (EMC) Research Group Sfax (ENIS),
University of Sfax, Sfax, Tunisia
Email: radwene_fac@hotmail.fr

Received May 3, 2012; revised June 28, 2012; accepted July 5, 2012

ABSTRACT
This paper presents two schemes of high performance CMOS current mirror, one of them is used for operational trans-
conductance amplifier (OTA) in analog VLSI systems. The linearity, output impedance, bandwidth and accuracy are the
most parameters to determine the performance of the current mirror. Here a comparison of two architectures based on
same architecture of the amplifier is presented. This comparison includes: linearity, output impedance, bandwidth and
accuracy. These two circuits are validated with simulation in technology AMS 0.35 µm. An operational amplifier based
on the adapted current mirror is proposed. Its frequency analysis with large bandwidth is validated with the same tech-
nology.

Keywords: Analog Circuits; Current Source; Current Mirror; Low Voltage; Operational Transconductance Amplifier

1. Introduction This circuit has higher output impedance than the sim-
ple current mirror and moderately high input impedance.
In the last few years, the demand for analog circuits
Equation (3) of input impedance is:
which can operate at low voltage is an established fact
and does not need any further justification. In particular 1 1
Z in   (3)
structures of current mirrors which have increased rap- gm11 gm12
idly and become one of the most interesting areas of re-
Equation (4) of output impedance is:
search [1]. Many configurations of current mirror are
discussed and used for many applications. Especially gm9
Z out  (4)
cascode current mirror which is one of the main building go9 . go10
blocks of analog and mixed-signal integrated circuits.
(where gm and go are the small-signal transconductance
For low voltage design circuit and high speed application,
gain and the conductance of the MOS transistor, respec-
the important parameters to determine high performance
tively.)
current mirror are [2-4]:
A simple variation of this circuit is shown in Figure
 Low input and output voltage.
1(b) [5]. In this scheme the variable voltage Var with re-
 Low input impedance.
sistance R1 are added. They are injected between the
 High output impedance.
drain of transistor M12 and the source of transistor M11.
 Minimum error of copying accuracy and settling time.
The drain source voltage of the mirror transistor M12 is
The four transistors circuit shown in Figure 1(a) is a
forced to a constant value by means of transistor M11,
simple cascode current mirror and it is characterized by
current Iin and variable voltage Var. Thus, on one hand, a
moderately low input and output voltages.
reduction of the input impedance by the gain of M11. On
Equation (1) of input voltage is:
the other hand, it reduces the input voltage requirements.
Vin  2VDSAT  2VT (1) In this case, the input voltage can be set to its minimum
Equation (2) of output voltage is: value by proper selection of the variable voltage Var.
Hence, this scheme achieves low input impedance with
Vout  2VDSAT  VT (2)
low input voltage requirements but with some limitation
(VDSAT and VT denote is the minimum drain-source satu- due to the difference between the current in M11 and M9.
ration voltage and the transistor’s threshold voltage.) This difference causes a mismatch in the drain source

Copyright © 2012 SciRes. CS


312 R. LAAJIMI, MED. MASMOUDI

rent (V-I) converter. In the third section, the design of


proposed version 1 of V-I converter is presented with
simulations results. The proposed version 2 of V-I con-
verter is presented in section four. Section 5 presents an
application of V-I converter in two-stage operational
amplifier. Conclusion is drawn in the last section.

2. Amplifier Structures
In order to achieve high current copy accuracy, it is nec-
essary to use an amplifier between the mirror’s input and
output transistors.
The amplifier architectures are: simple differential
amplifier [6] and amplifier proposed by [5]. As shown in
Figure 2(a), this structure is formed by the input differ-
ential pair (MP1 and MP2) and the active charge (MN1
and MN2). The Figure 2(b) shows a differential ampli-
fier with two MOS transistors (MN1 and MN2) in which
(a) MN1 is operated in the weak version region (source gate
voltage of MN1 equal to zero). This version can operate
either in the linear region or in the saturation region for
achieving low voltage and low consumption.
Moreover, the amplifier, which has many transistors,
causes the increase of the power dissipation and the chip
area. The advantages of the scheme proposed by [7] are
low voltage operation, small chip area, high output resis-
tance and no bias current. For this reason we use this
structure in our two versions of voltage to current con-
verter which are more described in the following para-
graph.
Vdd Vdd

MP1
MN1
1 2
MP2 3

3
MN2
MN2

(b) MN1

Figure 1. Current mirror configuration. (a) Simple cascode Vss 1 2


current mirror; (b) Cascode current mirror with regulated
(a) (b)
voltage.

voltage of M10 and M12 and results in a loss of accuracy,


so degraded linearity (due to channel length modulation).
To overcome this limitation, we are proposing two
novels structures of current mirror which offers both the
low compliance voltage and a minimum error of copying 3
accuracy. The two proposed approaches are based on
using a differential amplifier to compare the drain volt-
ages of the input and output mirror transistors, to force
the equality between these voltages, thereby improving 1 2
the accuracy of the current copy, and improving linearity. Figure 2. Amplifier configuration. (a) Simple differential
The paper is organized as follows. The second section amplifier structure [6]; (b) Two-transistor apmlifier struc-
presents the amplifiers structures used for voltage to cur- ture [7].

Copyright © 2012 SciRes. CS


R. LAAJIMI, MED. MASMOUDI 313

3. Proposed Version 1 of Voltage to where gm and ro are the small-signal transconductance


Current Converter gain and the output resistance of the MOS transistors. In
this case we assume that the amplifier have an input
3.1. Description
open-loop gain Aolinp and output open-loop gain Aolout
According to Figure 3 the version 1 of V-I converter is (Aolout = AvMC2·Avomp). AvMC2 and Avomp denote the volt-
composed of three blocks: polarisation, correction and age gain of the transistor MC2 and amplifier gain respec-
output load. tively.
The polarisation block is formed of four transistors On the other hand, the drain source voltage of the
(MP1, MP2, MP3, MP4) with variable input voltage Vin mirror transistor M1 achieves a small constant value
and input resistance Rin. The correction block is com- thanks to current source Iin and variable voltage source
posed of three transistors (M1, M2, MC2). It character- Vin. Drain source voltage can be decreasing to a mini-
ized by minimum error of copying accuracy due to the mum value, by selection of Vin and consequently a very
equality of drain source voltage between M1 and M2. low input voltage of the circuit.
This equality thanks to an amplifier between the mirror’s
input and output transistors M1 and M2 and causes high 3.2. Simulations Results
accuracy and good linearity. High output impedance is
obtained by the output current of amplifier and passes to Different schemes are simulated using Tspice based on
the gate of transistor MC2. The output load block is a BSIM3V3 transistor model for the technology AMS 0.35
simply resistance (Rout). µm at ±1.5 V power supply voltage.
This scheme offers a comparison between drain source Tspice simulations are carried for an input voltage Vin
voltage of M1 and M2 by using a differential amplifier to varied from −1.1 V to 0 V, Figure 4 shows the DC char-
provide higher accuracy of the current copy. The input acteristic for the V-I converter for different values of
injection current signal Iin is replaced by another source resistance (Rout = 100 Ω, Rout = 1 KΩ, Rout = 5 KΩ) in
formed by variable input voltage Vin with resistance Rin. which the full input voltage swing capability is evident
On the one hand, we obtain a reduction of the input im- with truly linearity.
pedance which given by this relation: As shown in Figure 5, from DC output characteristics
Equation (5) of input impedance is: simulations, the output resistance presents a moderate
value of 0.18 MΩ.
1 The Figure 6 shows the AC characteristic of the pro-
Z in  (5)
gm1 . Aolinp posed V-I converter. For a resistance of 100 Ω, we
Equation (6) presents moderate output impedance achieved a common gain bandwidth (GBW) equal to
750 MHz for different values of resistance (Rout = 100
Z out  ro2  Aolout  ro2  AvMC2  Avomp (6) Ω, Rout = 1 KΩ, Rout = 5 KΩ) and variable gain (Av) from
53 dB to 80.2 dB at minimum resistance (Rout = 100 Ω).
According to Figure 7, the deviation of the DC output
current from the ideal characteristic for different values
of resistance Rout. The large error is reached for the low-
est input voltage Vin of −1.1 V. On the other hand the
variation of Vin between −0.9 V to 0 V provide a small
current error under 0.1% for different values of resistance
(Rout = 100 Ω, Rout = 1 KΩ, Rout = 5 KΩ). Moreover for
the maximum current error of 0.5%, Vin varied from −1.1
V to −0.95 V in particular for output resistance Rout = 5
KΩ.

4. Proposed Version 2 of Voltage to


Current Converter
4.1. Description
The version 2 of V-I converter is presented in Figure 8. It
is like the structure of version 1 shown in Figure 3 and
composed of three blocks: polarisation, correction and
Figure 3. Proposed version 1 of voltage to current con- output load. The main difference is in the correction block.
verter. In which there are three transistors (M1, M2, MC2)

Copyright © 2012 SciRes. CS


314 R. LAAJIMI, MED. MASMOUDI

150
For Vin = - 1V Iout=10µA
Output Current (μA)

100

Rout= 100 Ω
50 Rout= 1 KΩ
Rout = 5 KΩ

-1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 -0.0

Vin (v)
Vin (V)

Figure 4. DC characteristics of V-I converter for different


values of resistance Rout.

(-1.00, 57.16u) (1.30, 69.17u) dx=2.30 dy=12.01u m=5.22u


70

60

50
Output Current (μA)

40
Figure 8. Proposed version 2 of voltage to current con-
V out
30 R out   0 . 18 Meg verter.
I out
20
with an amplifier between M1 and M2 in order to mini-
10
mise error of copying accuracy.
0 In this case of structure an approach is used to increase
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
the output impedance without sacrificing the equality
Vout (v)
Vout (V) between input and output of drain source voltage (M1
Figure 5. Output current vs output voltage variation of and M2), consists in integrating a connection between the
proposed V-I converter. gate of transistor MC2 and the gate of transistor M2. We
achieved very high output impedance due to the output
80
current of amplifier. This current is passed through each
75 Rout= 100 Ω gate of transistors MC2 and M2. Equation (8) shows the
Rout= 1 KΩ
value of output impedance which is:
Current Gain (dB)

70
Rout = 5 KΩ
65 Z out  ro2  Aolout  ro2  AvMC2  AvM2  Avomp (8)
60
ro2 denote the output resistance of the MOS transistor
55
M2. The amplifier has an output open-loop gain Aolout.
50 Equation (9) give this relation:
45 Aolout  AvMC2 . AvM2 . Avomp (9)
100 1k 10k 100k 1M 10M 100M 1G 10G
We assume that AvMC2, AvM2 and Avomp denote the
Frequency (Hz)
voltage gain of the transistor MC2, M2 and amplifier
Figure 6. Frequency response of proposed V-I converter. gain respectively.

4.2. Simulations Results


From Tspice simulations, an input voltage Vin varied
from −1 V to 0 V, the DC characteristic for the V-I con-
verter for different values of resistance (Rout = 100 Ω, Rout
= 1 KΩ, Rout = 5 KΩ) is shown in Figure 9. We find that
the linearity is evident for each value of resistance.
To confirm the high output resistance given by the
proposed version 2 of V-I converter, Figure 10 shows
the DC output characteristics simulations. The value of
Figure 7. Current error of V-I converter. the output resistance in this case is equal to 0.34 MΩ.

Copyright © 2012 SciRes. CS


R. LAAJIMI, MED. MASMOUDI 315

version 1 of V-I converter, it is possible to use this ap-


For Vin = - 0.85 V Iout=10µA proach for Operational amplifier [9,10]. The Figure 13
100
shows a practical implementation of the two-stage Op-
erational amplifier.
Output Current (μA)

The simulated output frequency response of our appli-


50
cation is shown in Figure 14. The bode diagram gives an
Rout= 100 Ω
Rout= 1 KΩ open loop gain of 60 dB with a large GBW of 82 MHz, a
Rout = 5 KΩ 97 KHz of cut-off frequency and a phase margin of 62˚.
0 We note that the input current passes through M8 using
for polarisation is equal to 10 µA and this corresponds to
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 -0.0
an input voltage Vin of −1 V.
Vin (V)
Vin (V)

Figure 9. DC characteristics of V-I converter for different 70


values of resistance Rout. Rout= 100 Ω
65 Rout= 1 KΩ

Current Gain (dB)


(1.30, 55.75u) (-1.00, 49.02u) dx=-2.30 dy=-6.73u m=2.92u

55
60
Rout = 5 KΩ
50
45 55
Output Current (μA)

40
35 50
V
30 R out  out  0 . 34 Meg 45
25 I out
20 40
15
100 1k 10k 100k 1M 10M 100M 1G 10G
10
5
Frequency (Hz)
0
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 Figure 11. Frequency response of proposed V-I converter
Vout (V)
Vout (V)

Figure 10. Output current vs output voltage variation of


proposed V-I converter.

From AC characteristic, we note an improvement of


the gain (Av). Its maximum value is 73 dB but it is 80.2
dB for the proposed version 1 of V-I converter. The
bandwidth responses for different values of resistance are
presented in Figure 11.
From Figure 12, we present a current error of V-I
converter for different values of resistance Rout. On the
one hand, the variation of Vin from −0.9 V to 0 V give the
same characteristic of error for different values of resis-
Figure 12. Current error of V-I converter.
tance (Rout = 100 Ω, Rout = 1 KΩ, Rout = 5 KΩ). On the
other hand for the maximum current error of 0.35%, Vin
is lower than −0.95 V.

5. Application of V-I Converter in


Two-Stage Operational Amplifier
Voltage to current V-I converter becomes the most inter-
esting element of interface measurement in the field of
mixed signal systems [8].
The most important parameters to determine high per-
formance of current V-I converters are:
 High linear range.
 Large bandwidth and gain. Figure 13. Proposed two-stage operational amplifier with
Because the large bandwidth and gain of the proposed proposed version 1 of V-I converter.

Copyright © 2012 SciRes. CS


316 R. LAAJIMI, MED. MASMOUDI

Systems, Vol. 2, 2001, pp. 565-568.


50
[3] K.-H. Cheng, T.-S. Chen and C.-W. Kuo, “High Accu-
Magnitude (dB), Phase (deg)

racy Current Mirror with Low Settling Time,” Proceed-


0 ings of the 46th IEEE International Midwest Symposium
on Circuits and Systems, Vol. 1, 2003, pp. 189-192.
[4] M. S. Sawant, J. Ramirez-Angulo, A. J. Lopez-Martin
-50 and R. G. Carvajal, “New Compact Implementation of a
Very High Performance CMOS Current Mirror,” 48th
Midwest Symposium on Circuits and Systems, Vol. 1,
-100 2005, pp. 840-842. doi:10.1109/MWSCAS.2005.1594232
[5] J. Ramirez-Angulo, R. G. Carvajal and A. Torralba, “Low
100 1k 10k 100k 1M 10M 100M
Supply Voltage High Performance CMOS Current Mirror
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Transactions on Circuits and Systems-II Express Briefs,
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[6] A. N. Mohieldin, E. Sánchez-Sinencio and J. Silva-
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Copyright © 2012 SciRes. CS

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