BASICS OF CURRENT MIRRORS

• Biasing in ICs
• Simple Current Mirror
• Cascode Current Mirror
• Low-Voltage Cascode Current Mirror

2
Current Source Properties
• Output Resistance

• Finite output resistance degrades current source

accuracy and amplifier gain
• Other important properties:
• Voltage headroom (compliance voltage)
• Accuracy
• Noise
3
How Should We Bias Our Circuits?
• Resistive Biasing
• Assuming saturation
 nCox VG  VTn 2
1 W
ID 
2 L
2
1 W  RG 2 
  nCox  Vdd  VTn 
2 L  RG1  RG 2 

• ID is sensitive to
• Supply (Vdd)
• Process (VTn and nCoxW/L)
• Temperature (VTn and n)
4
IC Biasing
• In IC design we often assume that we
have one precise current source and we
copy its value to our circuits

5
Simple Current Mirror
• That copy circuit is a current mirror
• Simple Current Mirror
What is VG ?
W 
 nCox   VG  VTn 2
1
I D  I REF 
2  L 1
2 I REF
VG   VTn
 
W
 nCox  
 L 1
• If VG is applied to another transistor
W 
2
   
 
W   L 2
  n Cox     VTn  VTn  
1 2 I REF I out I REF
I out  
W
2  L 2  C  W   
 n ox     L 1
  L 1 
6
Ideal Current Mirror Example

I1=1mA

I2=1mA

I3=0.5mA

I4=1.5mA

• This bias scheme reduces sensitivity to

process, voltage, and temperature variations

7
CS Amplifier w/ Current Source

What is ID?

• Need to insure that M3 remains in saturation

 
 
 RG 2 
Vs  VG  Vov1  VTn    Vdd   
2I D
  V 
 RG1  RG 2  W 
Tn

  nCox   
  L 1 
8
Small-Signal Output Resistance:
Simple Current Mirror/Source (Finite ro)

• A simple current mirror/source

has an output resistance equal
to a single transistor ro
• In order to maintain a high
output impedance we need a
minimum output compliance
voltage 1
rout 
Compliance Voltage  VDSAT 2  VGS 2  VT 2 go

9
Simple Current Mirror Accuracy

• While VDS1=VGS1=VGS2, VDS2 may not equal VDS1

• This causes an error in the mirroring ratio
• To improve accuracy we can (a) force VDS2 to be
equal to VDS1 (Cascode Current Mirror), or (b) force
VDS1 to be equal to VDS2 (Low-Voltage Cascode
Current Mirror)
10
Cascode Current Mirror

• A cascode device can shield a current source, thereby

reducing the voltage variations across it.
• But, how do we ensure that VDS2 = VDS1?
• We can generate Vb such that Vb - VGS3 = VDS1(= VGS1)
with a stacked diode connected transistor

11
MOS Cascode Topology Output Resistance

vx  io ro1
Writing a KCL at the output node
v v
 io  g m3  vx   o x  0
o

ro3
io ro1 v
 io  g m3io ro1   o m3 x o3
o
ro3 ro3 x

vo
Rout   ro3  ro1  g m3ro3ro1  g m3ro3ro1
io
o1
The dominant term is the bottom effective resistance
boosted by the gain of the top transistor (gm3ro3) 12
Cascode Current Mirror Compliance Voltage

• What is the minimum output voltage VP

such that all the output transistors remain
in saturation?

VP  VY  VDSAT 3  VGS1  VGS 3  VT

Compliance Voltage  VGS1  VDSAT 3

• Note that this output stage biasing technique “wastes”

one threshold voltage, as VY could potentially be lower by
a VT and M2 would still be in saturation

13
How Can We Get a Lower Compliance Voltage?

• The left figure uses the minimum possible Vb such that M2

and M3 remain in saturation
• However, as VX≠VY, the output current does not accurately track IREF

• The right figure (our original cascode current mirror)

achieves good accuracy, but again wastes a threshold
voltage relate to the left figure
14
Low-Voltage Cascode Current Mirror

Compliance Voltage  VDSAT 3  VDSAT 4

• M2 and M4 should be sized such that

• VGS2 = VGS4
• M1 and M3 biased near edge of saturation
• VDS1 ≈ VDS3 ≈ VDSAT
• Vb = VGS2+(VGS1-VT1) = VGS4+(VGS3-VT3)

15
Alternative Vb Generation

[Razavi]

• Saves one current branch

• M5 sized such that VGS5 ≈ VGS2
• Some body effect error here

• Size M6 and Rb such that

• VDS6 = VGS6-RbI1 ≈ VGS1-VT1
16
 MOSFET Current Mirror and Active Load
Various bias techniques for MOSFET circuits

(Razavi 9.2.3)

How do we make
a constant current source
with MOSFETs?
Lect. 22: MOSFET Current Mirror and Active Load

Constant current source: 1 ' W 

 kn   VGS  Vt 
2
I D1
2  L 1

VDD  VGS
I D1  I REF 
R
Assuming Q1, Q2 have same properties (kn’),

1 ' W 
kn   VGS  Vtn 
2
IO  I D 2 
2  L 2

IO W / L  2

 Current mirror
I REF W / L 1
Limitation on Vo? VO  VGS  Vt
Lect. 22: MOSFET Current Mirror and Active Load

Mismatches between IREF and IO

Due to channel-length modulation For Q1 and Q2
IO = IREF only if VDS1= VDS2  V0=VGS

As VO increases, IO increases from IREF

VO  VGS
I O  I REF 
r0
 Lect. 22: MOSFET Current Mirror and Active Load
VDD=3V, Q1, Q2 identical 1 ' W 
I D1  I REF  kn   (VGS  Vt )2
L= 1m, W=100m, Vt=0.7V, kn’=200A/V2, 2  L 1
ro = 200k
1
100   200  10  (VGS  Vt )2 ,
1. Determine R for IO=100A. 2
2. What is the lowest value for VO?
3. How much IO changes when VO changes 1V? (VGS  Vt )  0.316, VGS  1.016

VDD  VGS 3  1.016

R   19.84k
I REF 0.1mA

VO min  VGS  Vt  0.316 V

VO 1V
I O    5 A
ro 2 200k 

Electronic Circuits 1 (13/2) Prof. Woo-Young Choi

 Lect. 22: MOSFET Current Mirror and Active Load
(Without r0 consideration)

W / L  2
I 2  I REF
 W / L 1
W / L  3
I 3  I REF
 W / L 1
I3  I4

W / L  5
I5  I4
W / L  4
Current-steering circuits: current source (Q5), current sink (Q2)
Lect. 22: MOSFET Current Mirror and Active Load

CS amplifier

Where is RD ?

Current source as a resistor  Active load

(Remember Q2 has rO)

Lect. 22: MOSFET Current Mirror and Active Load

Small-signal model for Q1 and Q2

Gain: -gm1 (rO1 || rO2)

PMOS current mirror provides

large resistance (Active Load)
as well as bias current!

 Good for IC!

 Lect. 22: MOSFET Current Mirror and Active Load

VDD=3V, Vtn=|Vtp|=0.6V, kn’=200A/V2, kp’=65A/V2,

1. A   gm 1 ( ro1 || ro 2 )
L=0.4m, W=4m, ro1=200k, ro2,3 = 100k,
IREF=100A.
W  4
gm 1  2kn'   I REF  2  200   100  0.63mA/V
1. What is the small-signal voltage gain, vO/vI?  L 1 0.4
2. What is the maximum vO for which the above is valid?
 A  0.63(mA/V)  (200 || 100)(k )  42

1 ' W 
 
2 VSD ,3
2. For Q 3 , I REF   Vtp 
2 p  L  3 SG ,3
k V
ro
1  4  VSG ,3
 
2
100   65   SG
V  0.6 
2  0.4  100 K

VSG ~ 1.12V

For vO ,max , VSD 2,min  VSG  | Vtp | 1.12  0.6  0.52V

 vO ,max  VDD  VSD 2,min  2.48V

Lect. 22: MOSFET Current Mirror and Active Load

Homework:

Determine Icopy in following circuits. Assume all MOS transistors are in saturation
and the influence of r0 can be ignored.
 CURRENT SOURCES, CURRENT SINKS AND CURRENT MIRRORS

1 Introduction:
Current sources and current mirrors form
one of the most important components in
Analog Circuits. When a source of current
flows from the highest positive potential
(VDD) into a load it is designated a current
source while when the source of current
flows from the load to the ground, it is
designated a current sink. A schematic of a
current source and a current mirror is shown
in Fig. 1. A simplest current source/sink can
be constructed using a fixed gate voltage to a P-MOS Transistor / N-MOS
Transistor respectively. When a P-MOS Transistor is used with a fixed gate
voltage VGG to obtain a current source, we will get a near constant current so
long as the transistor is in saturation, i.e so long as the source to drain voltage
VSD ≤ VSG + VTH
P
. Similarly for a current sink with N-MOS Transistor the drain to
source voltage VDS ≤ VGS + VTH
N
we will get a near constant current. The voltage VSD
and VDS for the P and N Transistors respectively represent the voltage across
the current source and sink respectively. The minimum voltage magnitude across
the source/sink defines one of the important characteristics of the current

Fig.2 Basic characteristics of a current source and a sink.

source/sink (see Fig. 2), the other characteristics of interest is the reciprocal
of the slope of the I-V curve in the region of near constancy of output current,
the output impedance rout. In the Current source/sink circuits shown in Fig. 2,
the role of the diode connected transistors is to provide the necessary bias
voltage VGG. The required VGG can be obtained by choosing the appropriate sizes
for M1 and M2. Before proceeding to evaluate the output impedance and identify
methods to improve rout, let us recollect the equivalent circuit of an NMOS
transistor.

Fig. 3 Equivalent circuit of a NMOS Transistor.

It is evident that the output impedance of both the current source and the sink
are rds of the output transistor that acts as the constant current source/sink.
Before proceeding further it is essential to obtain an answer to the question of
how do we obtain the exact value of VGG required to obtain a designated value
for the current source/sink. Since it involves the proper sizing of the M and P
transistors it raises the question about how accurate can it get to be. An
interesting way around this problem is to replace M2 in Fig. 2(a) with a current
sink of required current value and retain M3 as a diode connected P Transistor
and replace M3 in Fig. 2(b) with a current source of required current value and
retain M2 as a diode connected N Transistor as shown in Fig. 4.

Fig. 4 Modified current source and sink of Fig. 2.

The configuration of current source and sink given in Fig. 4 are called Current
Mirrors. A name derived from the fact that the gate to source voltage of M1
and M3 in Fig. 4(a) and the gate to source voltage of M1 and M2 ensures that M1
mirrors the current Iref. This configuration of current mirror is also called the
Simple Current Mirror.

Sources of error in a simple Current Mirror:

Fig. 5 represents the operative part of a simple current
mirror shown earlier. Let us now look in to the sources
of error in the mirroring action of M1 of Iref flowing in
M Assuming that both the transistors are in saturation,
we can write the ratio of currents Iout/Iref as
2
Iout β1 ⎛⎜ (VGS1 − VTH1 ) ⎞⎟ ⎛ (1 + λVDS1 ) ⎞
= ⎜ ⎟ (1)
Iref β2 ⎜⎝ (VGS2 − VTH2 )2 ⎟⎠ ⎜⎝ (1 + λVDS2 ) ⎟⎠
With VGS1 = VGS2 by connection, if the two transistors are perfectly matched,
⎛ (1 + λVDS1 ) ⎞
Iout W1 L2
= ⎜ ⎟ (2)
Iref W2 L1
⎜ (1 + λV ) ⎟
⎝ DS2 ⎠
that reduces to (W1L2/W2L1), if VDS1 equals VDS

2 Configurations of Current Mirrors:

The simple current mirror shown in Fig. 4 has an output impedance limited to rds.
In this configuration, Vmin is determined by the drain voltage required to ensure
that the transistor M1 is in saturation for a gate voltage VGG i.e Vmin = VGG - VTH.
Furthermore, the drain to source voltage of the mirroring transistor VDS1 will
depend on the load and hence the mirroring action. Various modifications have
been suggested to the simple current mirror configuration to improve some or
all of he above features. We will now look in to some of the configurations to
obtain as good a current mirror as possible, i.e with a low Vmin, a large output
impedance and as good a mirroring as possible (VDS1 ≈ VDS2).

Fig. 6 A Current Mirror with a source resistance (a) the

circuit (b) the small signal equivalent circuit.
Fig. 6 shows a current mirror with a source resistance to improve the output
impedance. From the equivalent circuit we can write
 [ (
vout = iout − gm vgs + gmb vsb rds + iout r )] (3)
vout
and rout =
= rds + r ( gm rds + gmb rds + 1 ) ≈ ( gm r )rds (4)
iout
We see that by the introduction of a resistance in the source lead, we obtain
output impedance increased by a factor gmr. In the presence of the resistance
r, the reflected current in M2 is also modified. We now have
𝐾!
𝐼!"# = 𝑉!"! − 𝑉!" !
2
where VG2=VG1–(IOUT)r, reducing the mirrored current. This is a very useful
configuration to obtain lower current in the mirroring branch. This configuration
was very popular during design with Bipolar Transistors for low current design.

2.1. Wilson Current Mirror:

(a) (b)
Fig. 7 Development of Wilson Current Mirror.
Fig.7a shows a modification of Fig. 6 with resistance r replaced with a MOD
diode for increasing the output impedance. However as said earlier it reduces
the magnitude of mirrored current. A further modification is done as in Fig.
7(b) to mirror the current completely. This circuit is called a Wilson current
mirror. From the equivalent circuit of the circuit in Fig. 7(b) we can obtain the
output impedance of the Wilson current mirror as
rds 1 g m 2 rds 2 g m 3 rds 3
rout =
rds 1 g m 1
(
≈ rds 2 g m 3 rds 3 ) if g m 1 = g m 2 (5)

This modification to the Simple Current

mirror does ensure an increased output
impedance, but does not ensure VDS1 = VDS2.
Vmin obtained in this configuration is the sum
of the voltage, VDS1(sat) and VDS3(sat), the
minimum drain to source voltage required to
keep M3 and M1 in saturation. Defining VON
= VGS – VTH, and assuming that all transistors
have same W/L ratio, we have VDS1 = VGS1 =
VON + VTH and VDS3(min) = VON and Vmin =
2VON + VTH. To ensure that the VDS of the gate tied transistors M1 and M2 to be
equal we introduce another transistor M4 in series with M1 as shown in Fig. 8.
The circuit in Fig. 8 is called the Modified Wilson Current Mirror. The potential
at point A, assuming that all transistors have identical W/L ratios, will be 2VGS.
It is evident from the circuit that with the gate to source voltage of M4 being
VGS, the VDS of M2 will also be VGS as in M1. The output impedance and Vmin of the
modified current mirror is the same as Wilson current mirror.

2.2. Cascode Current Mirror:

Fig. 9 Cascode Current Mirror.

In Fig. 5, including a source resistance in the mirroring circuit modified the
simple current mirror. Instead, if we insert another mirror pair in series with a
simple current mirror, we obtain a cascode current mirror shown in Fig. 9. In the
cascode current mirror, if we choose W/L ratios of all the transistors equal, we
have the potential at A equal to 2VGS. With the gate to source voltage of M4
being VGS the voltage at C and hence VDS of M1 will also be VGS thus giving a very
good mirroring. The output impedance in this case will also be given by eqn. 3. In
a cascode current mirror, with the gate of M2 being at 2VGS = 2VON + 2VTH, we
obtain Vmin = 2VON + VTH.

2.3. Regulated Cascode Current Mirror:

In Fig. 10 we present the development of a high output impedance current

mirror called the regulated Cascode Current Mirror from Wilson Current
Mirror. In Fig. 10 (a) we have the normal Wilson Current Mirror that has been
recast as in Fig, 10(b). If we dis connect the gate of M1 from the source and
apply a potential VGS, the circuit will be functionally the same but with a
different output impedance. It is evident, comparing the circuit with the circuit
shown ibn Fig.5, in the Wilson current mirror the value of R realised is 1/gm
while for the modified circuit in Fig. 10(c) it will be the drain to source
impedance. Fig. 10(d) presents the complete circuit with VGS for M1 generated
through another branch using the principle of a current mirror. While Vmin and
the matching of VDS for good mirroring is same as in an improved Wilson current
mirror, the output impedance will be different. It can be easily obtained from
the equivalent circuit that the output impedance of Regulated Cascode Current
Mirror will be
 rout = rds3 + rds2 (1 + rds3 (gm3 + gmb3 )gm1 rds1 gm3 rds3 )
≈ rds2 gm1 rds1 gm3 rds3 (6)

Fig. 10 Development of Regulated Cascode Current Mirror

We see that in a Regulated Cascode Mirror the output impedance is increased

by a factor gm1rds1. We see from Fig. 10(d) that if all transistors have the same
size, VGS2 = VDS1 = VGS = VDS4, giving us a very good match in mirroring.
We have so far looked in to approaches that could give us high output
impedance. Let us now consider a few modifications to get a good match and a
low Vmin with reasonably high output impedance with some modification to the
cascode structure.

2.4. Current Mirror with low Vmin and good mirroring property.

Fig. 11 represents the schematic structure of a

Cascode Current Mirror. We see that in the Cascode
Current Mirror in Fig. 2.9, the voltage VGG2 was
obtained as 2VGS and hence we had a Vmin of 2VGS – VTH
= 2VON +VTH. However if we can obtain VGG2 = 2VON +
VTH, Vmin can be reduced to 2VON. This can be achieved
by introducing another branch with iref current as
shown in Fig. 2.11. A scheme to implement this to
obtain a lower Vmin = 2VON + VTH is shown in Fig. 2.12. Here we have introduced
 Fig. 12 A scheme to improve the Vmin of the current mirror.

another current branch containing MOS transistor M4 with a W/L ration ¼ of all
other transistors. This is done at a cost of a slight mismatch in the mirroring as
VDS3 ≠ VDS1 while VGS3 = VGS1. A matching can be obtained if we can modify the
branch containing M3 to obtain VDS3 = VON = VDS1. A circuit incorporating this is
shown in Fig. 2.13 wherein we have added an additional transistor M5 to achieve
this. We can see from the figure that the Vmin achievable with this circuit is
2VON. This circuit is called Wide Range Cascode Current Mirror.

Fig. 13 Wide range Cascode Current Mirror.

We summarize the salient properties of all the current mirrors in the table
below.
Current Mirror Accuracy Output impedance Vmin
Simple Poor rds VON
Wilson Poor g r2 2VON + VTH
m ds
Improved Wilson Excellent 2
gm rds 2VON + VTH
Cascode Excellent 2
gm rds 2VON + VTH
Regulated Cascode Good gm2 rds
3 2VON + VTH
Wide Range Cascode Excellent 2
gm rds 2VON