Current Mirrors
David Johns
University of Toronto
david.johns@utoronto.ca
Current Source
Current sources are often used for general circuit biasing and
used as loads for amplifiers
A current source is created using a current mirror
IB
Current source symbol
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Current Source Specs
Vx IB
Ix
3 main specs
− IB - value of current source
− Ro - output impedance (ideally ∞)
− Vmin - minimum voltage required (ideally 0)
If Ro → ∞, then Ix = IB for Vx > Vmin > 0
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Current Mirror
VDD
Iref R
Io
ID1
M1 M2
VGS1 VGS2
Here, M2 is the current source while M1 sets the voltage VGS2
which sets the current for M2
We will start by assuming λn = 0
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Current Mirror
For current mirror, we assume M1
and M2 are matched
VDD
− µn ≡ µn1 = µn2
− Cox ≡ Cox1 = Cox3
Io
Iref R − Vtn ≡ Vtn1 = Vtn2
Vo
ID1 − This is achieved by having the 2
M1 M2 transistors on the same integrated
VGS circuit and relatively close to each
other.
We also have
VGS ≡ VGS1 = VGS2
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Current Mirror
For M1
− Since VDS1 = VGS1
VDD In either cutoff or active region
(not triode)
Io
Iref R In cutoff ONLY IF VDD ≤ Vtn
Vo
ID1
− ID1 = 0.5µn Cox (W /L)1 (VGS − Vtn )2
M1 M2 − ID1 = Iref = (VDD − VGS )/R
VGS − Combine above 2 eqn to find VGS
and Iref
For M2
− ID2 = 0.5µn Cox (W /L)2 (VGS − Vtn )2
Comparing ID1 and ID2 equations, we have
ID2 (W /L)2
= (1)
ID1 (W /L)1
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Current Mirror
The above is valid as long as both transistors are in the active
region
For M1
− VDD ≥ Vtn
For M2
− VDS2 ≥ Vmin where Vmin = Vov 2 = VGS − Vtn
− So M2 remains active as long as its drain voltage is high enough
− So it depends on what is attached to the M2 current source
Also, in general, the length of M1 and M2 are also matched
− This would make the above ID2 /ID1 equation accurate even when
λn 6= 0 for the case VDS2 = VDS1
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Current Mirror with λn 6= 0
For the case λn 6= 0 we have
ID1 = 0.5µn Cox (W1 /L1 )(VGS − Vtn )2 (1 + (λ0n /L1 )VDS1
0 )
ID2 = 0.5µn Cox (W2 /L2 )(VGS − Vtn )2 (1 + (λ0n /L2 )VDS2
0 )
0 ≡V
Recall VDS DS − Vov
So if L2 = L1 then we have ID2 precisely equals (W2 /W1 )ID1 at the
time when VDS2 = VDS1
So when the drain source voltages of the 2 transistors are equal,
our current mirror output, ID2 will be accurately related to the
reference current, ID1 .
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Current Mirror Plot
VDD
Io
Iref R
Vo
ID1
M1 M2
VGS
The non-zero slope for Vo > Vmin is due to the finite output
impedance of M2
This slope equals 1/Ro where in this case, Ro = ro2
Io precisely equals our desired IB when VDS2 = VDS1 which is
higher than Vmin
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Small Signal Impedances
We know the impedance looking into the drain of M2 is ro2
What is the impedance looking into the gate/drain of M1 ?
ix
Ro1
Ro1 vx
M1 gm1 vgs1 ro1
vgs1
Ro1 ≡ vx /ix
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Small Signal Impedances
ix = gm1 vx + (vx /ro1 ) = (gm1 + (1/ro1 )vx
1
Ro1 = vx /ix = (gm1 + (1/ro1 ))−1 = gm1 ||ro1
1
Ro1 = gm1 ||ro1
This configuration is often referred to as a ”diode connected
transistor”
− The term ”diode connected” comes from Bipolar transistors
− Bipolar transistors (npn or pnp) are back to back diodes and in this
case, one of the diodes is short circuited.
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Current Mirror Example 1
Given Iref = 40µA, W1 = 2µm and
µn Cox = 120µA/V2 ; Vtn = 0.3V; λ0n = 50nm/V
L1 = L2 = 200nm
(a) Find W2 so that ID2 = 20µA
(b) Find the output impedance, Ro , of the current source for M2
(c) Find the lowest possible output voltage, Vo , for the current source
while keeping M2 active
(d) At what value of Vo does ID2 = 20µA?
(e) Estimate the value of ID2 if Vo = 1V based on small signal analysis
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Current Mirror Example 1
Solution
(a) ID2 = (W2 /W1 )ID1 and we have
ID1 = Iref = 40µA; W1 = 2µm; ID2 = 20µA
Solving, we find W2 = 1µm
(b) The output impedance of the current source is the output
impedance of M2 which is ro2
ro2 = L/(λ0n ID2 ) = (200e − 9)/(50e − 9 ∗ 20e − 6) = 200kΩ
So Ro = ro2 = 200kΩ
(c) Since we are finding a dc bias voltage, we will assume λ0n = 0
ID2 = 0.5µn Cox (W2 /L2 )Vov2
2
20e − 6 = 0.5(120e − 6)(1/0.2)Vov 2
2
Solving for Vov 2 , we find Vov 2 = 0.258V
(we ignore the negative solution since that would make the
transistor cutoff)
For M2 to remain active, VDS2 ≥ Vov 2 and since Vo = VDS2
the minimum output voltage for Vo is 0.258V 13/28
Current Mirror Example 1
Solution
(d) The current mirror will be perfectly matched when VDS2 = VDS1
since all the other values are the same (except for W which scales
the output current).
VDS1 = VGS1 = Vov 1 + Vtn and since VGS1 = VGS2 and the
threshold voltages are the same, Vov 1 = Vov 2 = 0.258V
VDS1 = 0.258 + 0.3 = 0.558V
So the ID2 = 20µA when Vo = 0.558V
When Vo > 0.558, ID2 will be higher than 20µA
When Vo < 0.558, ID2 will be lower than 20µA
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Current Mirror Example 1
Solution
(e) From small signal analysis, we have
∆ID2 = ∆Vo /Ro where Ro is the output impedance of the current
source and we found Ro = 200kΩ
We know from above ID2,0.558 = 20µA at Vo = 0.558V and we
want to estimate the current at Vo = 1V
In this case, the change in output voltage is
∆Vo = 1 − 0.558 = 0.442V
ID2 = ID2,0.558 + ∆ID2 = 20e − 6 + (∆Vo /Ro )
ID2 = 20e − 6 + (0.442/200e3) = 22.2µA
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Sending Bias Currents around a Chip
It is common on an integrated circuit to have multiple analog
circuit blocks far apart on the chip
− Blocks such as analog-to-digital converters, digital-to-analog
converters, RF circuits, phase-locked-loops for clocking, SERDES,
etc...
Normally one main bias block is used to generate a constant bias
current, Iref , and this current needs to be replicated in all the
analog blocks in the chip
The WRONG way to replicate Iref is to send bias voltages to far
away blocks
The CORRECT way to replicate Iref is to send bias currents to far
away blocks
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Sending Bias Currents around a Chip: WRONG way
VDD
Analog
Block 1
Iref
VB1 Analog
M1 Block 2
Wrong because the grounds at Analog Block 1/2 may be at a
different voltage than main bias block
− Ground wires have resistance and current flowing through ground
causes a voltage drop
− Not an issue when grounds are close to each other
− Would result in incorrect bias currents AND the bias currents would
depend on current through ground wire (noisey bias currents)
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Sending Bias Currents around a Chip: CORRECT way
VDD VDD VDD VDD
M3 M4 M5
Iref Analog
IR5 Block 1
IR4
M1 M2
Analog
Block 2
Send a separate bias current to EACH analog block based on
main bias block
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Sending Bias Currents around a Chip: CORRECT way
Matching requirements
− M1 /M2 matched (except for W )
− M3 /M4 /M5 matched (except for W )
− No need to match NMOS with PMOS
IR4 = Iref × (W2 /W1 )(W4 /W3 )
IR5 = Iref × (W2 /W1 )(W5 /W3 )
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Cascode Current Mirror
To increase the output impedance of current mirror
− Use cascode
VDD
Io
Iref
Vo
Ro
VB2
M3 M4
VB1
M1 M2
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Cascode Current Mirror
The output impedance for this current mirror is Ro
Ro = ro4 + (1 + gm4 ro4 )ro2 ≈ gm4 ro4 ro2
It is at least gm ro greater than just ro2
Normally, match M1 /M2 and match M3 /M4 (except for W )
So L2 = L1 and L4 = L3
Also make W4 /W3 = W2 /W1 resulting in
Io = Iref × (W2 /W1 )
Problem with this circuit is Vmin is too large
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Cascode Current Mirror
VB1 = Vov 1 + Vtn
VB2 = VB1 + Vov 2 + Vtn = Vov 1 + Vov 2 + 2Vtn
Vmin occurs when drain of M4 goes below the gate of M4 minus
one threshold voltage
Vmin = VB2 − Vtn = Vov 1 + Vov 2 + Vtn
So in case where Vov = 0.2V and Vtn = 0.3V
Vmin = 0.2 + 0.2 + 0.3 = 0.7V
It turns out, there is a way to reduce Vmin
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Wide Swing Current Mirror
A wide swing current mirror is a cascode current mirror with a
lower Vmin
VDD VDD
Io
Iref Iref Vo
Ro
VB2
M3 M4
M5
VB1
M1 M2
(W /L)5 = 14 (W /L)1
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Wide Swing Current Mirror
To make things easier, assume M3 /M1 matched including their W
Since ID3 = ID1 , Vov 3 = Vov 1 which we will define as Vov
First, we find Vov 5 in terms of Vov
2
− ID1 = 0.5µn Cox (W /L)1 Vov
2
− ID5 = 0.5µn Cox (W /L)5 Vov 5
− Divide the above 2 equations
2
ID5 (W /L)5 Vov
− ID1 = 2
(W /L)1 Vov
5
− But ID5 = ID1 = Iref
q
− Vov 5 = (W /L)1
(W /L)5 × Vov
− If we choose (W /L)5 = 14 (W /L)1 , then
− Vov 5 = 2Vov
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Wide Swing Current Mirror
Now, we find VB2 so we can find Vmin
− VB2 = Vov 5 + Vtn = 2Vov + Vtn
Vmin occurs when M4 goes into triode which occurs when its drain
voltage is lower than the gate voltage minus Vtn
Vmin = VB2 − Vtn = 2Vov
So we have that Vmin = 2Vov which is one Vtn lower than in the
non-wide-swing current mirror
For this reason, the wide-swing current mirror is used in the
majority of cases on a chip.
The downside is that it requires an extra Iref
In practice, (W /L)5 = (1/5) × (W /L)1 to give some margin so that
both M1 /M2 remain in the active region
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Wide Swing Current Mirror Example
Assume a process with
L = 0.18µm; Vtn = 0.4V; µn Cox = 240µA/V2 ; λ0n = 50nm/V
(a) Design a wide-swing current mirror with Vmin = 0.3V and 100µA
output current using 2 current references of 50µA.
(use a practical choice for (W /L)5 )
Assume all L = 0.18µm
(b) Find the output impedance.
Solution
(a) We first assume that W3 = W1 so that Vov ≡ Vov 3 = Vov 1
We find Vov using
Vmin = 0.3 = 2Vov → Vov = 0.15V
Now we find W1
2
ID1 = 0.5µn Cox (W /L)1 Vov
50e − 6 = 0.5(240e − 6)(W1 /0.18)(0.15)2
W1 = 3.33µm and W3 = W1 = 3.33µm
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Wide Swing Current Mirror Example
Solution
(a) continued
W5 = W1 /5 = 0.667µm
Since we want Io = ID2 = 100µA, we have
Io = W2 /W1 × Iref → 100 = W2 /(3.33) × 50
W2 = 2W1 = 6.66µm
Finally, since W3 = W1 , then W4 = W2 = 6.66µm
(b) For the output impedance
ro2 = ro4 = L/(λ0n ID2 )
ro2 = ro4 = (0.18e − 6)/(50e − 9 × 100e − 6) = 36kΩ
gm2 = gm4 = 2ID2 /Vov 2 = (2 × 100e − 6)/0.15 = 1.3mA/V
Ro = ro4 + (1 + gm4 ro4 )ro2
Ro = 36e3 + (1 + (1.3e − 3)(36e3))(36e3) = 1.76MΩ
This is significantly higher than 36kΩ that would have occurred if
the current mirror was not cascoded.
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Topics Covered
Current source and specs
Basic current mirror
Sending bias currents around a chip
Cascode current mirror
− Higher output impedance (better accuracy)
− Wide swing current mirror
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