10/3/2018
(Session-2018-19)
Current Mirror circuit
Common--Emitter Characteristics
Common
Output Characteristics Input Characteristics
03-10-2018
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Fundamental
• Biasing in integrated-circuit design is based on the use of constant-
current sources.
• On an IC chip with a number of amplifier stages, a constant dc current
(called a reference current) is generated at one location and is then
replicated at various other locations for biasing the various amplifier
stages through a process known as current steering.
• This approach has the advantage that the effort expended on
generating a predictable and stable reference current, usually utilizing
a precision resistor external to the chip or a special circuit on the chip,
need not be repeated for every amplifier stage.
• The bias currents of the various stages track each other in case of
changes in power-supply voltage or in temperature.
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BJT Circuits as current mirror
Diode equation; as Q1 is
behaving as diode but it also
inherits property of transistor.
V is replaced by VBE
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Note that as β approaches ∞, Io /IREF approaches the nominal value of unity.
For typical values of β, however, the error in the current transfer ratio can be
significant. For instance, β = 100 results in a 2% error in the current transfer
ratio. Furthermore, the error due to the finite β increases as the nominal
current transfer ratio is increased.
Consider with N-output current mirror.
(N+1)Ic/Beta
Ic
1
I o / I REF
1 N 1
With large
I o / I REF 1 Ic/Beta Ic/Beta
Ic/Beta Ic/Beta
I o I REF
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Set IREF
(N+1)Ic/Beta
Ic
Ic/Beta Ic/Beta
Ic/Beta Ic/Beta
Current mirror circuit using FET
• A current mirror is a circuit
designed to copy a current
through one active device
by controlling the current
in another active device of
a circuit, keeping the
output current constant
regardless of loading.
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Fundamental concept behind current mirror
Fundamental concept behind current mirror
contd..
Vov=Overdrive voltage
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Just for student’s understanding
• As you can see, the drain of Q1 is shorted to its gate. This means that VG =
VD, and thus VGD = 0 V. So, is Q1 in cutoff, the triode region, or the
saturation region? It can’t be in cutoff, because if no current were flowing
through the channel, the gate voltage would be at VDD, and thus VGS would
be greater than the threshold voltage VTH (we can safely assume that VDD is
higher than VTH). This means Q1 will always be in saturation (also referred
to as “active” mode), because VGD = 0 V, and one way of expressing the
condition for MOSFET saturation is that VGD must be less than VTH.
• If we recall that no steady-state current flows into the gate of a MOSFET,
we can see that the reference current IREF will be the same as Q1’s drain
current. We can customize this reference current by choosing an appropriate
value for RSET. So what does all this have to do with Q2? Well, the drain
current of a MOSFET in saturation is influenced by the width-to-length
ratio of the channel and the gate-to-source voltage.
• Now notice that both FETs have their sources tied to ground and that
their gates are shorted together—in other words, both have the same
gate-to-source voltage. Thus, if we assume that both devices have the
same channel dimensions, their drain currents will be equal,
regardless of the voltage at the drain of Q2. This voltage is labeled VCS,
meaning the voltage across the current-source component; this helps
to remind us that Q2, like any well-behaved current source, generates
a bias current that is not affected by the voltage across its terminals.
Another way to say this is that Q2 has infinite output resistance:
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Q2
Q2
Ideal
Practical
Mathematical Fundamental for current mirror
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Example
