ANALOG & DIGITAL

ELECTRONICS
Amplifiers 2
Number Systems 38
Codes
42
Boolean Aigebra 45
Logic Gates 50
Karnaugh Map 55
Quine MCCluskey's 68
Combinational Circuits 73
Arithmetic Circuits 112
Flip-Flop 124
Register & Counter 145
Program Logic Devices 172
Memory Device 176
A/D& DjA Converter 183
Logic Families 194
POPULAR PUBLICATIONS

AMPLIFIERS

Chapter at a Glance
amplifiers, which are designed to give power gain with
Power Amplifiers are large signal (i) Class A , (ii) Class B, (i)
types of power amplifiers:
reasonable cfficiency. There are three
Class AB and (iv) Class C. fraction of a output quantity of a system to its
input.
Feedback: Feedback means transfer of a
oscillation
It can be of two types.
feedback: positive feedback enhances the output and is required for
Positive
a.
the output.
while negative feedback reduces circuits are used for increasing stability, reducing
Negative feedback
b. Negative feedback: bandwidth and error correction.
distortion. increasing signal is called
circuit which is used to generate a.c voltage without a.c input svstem
Oscillators: any feedback
Oscillation means gain * feedback fraction = 1. For a positive internal
an oscillator. the gain of the
overall gain can be written as. A, = A/ I - AB where, A is
the -AB is the loop gain.
amplifier. B is the feedback ratio, and that follows the basic development
of a
example of an oscillator circuit
Phase shift: An operational amplifier provides aphase shift
is the phase-shift oscillator. The
feedback circuit produce by three
mode and remaining 180° phase shift is
of 180 as it is used in the inverting the total
network. This form of RC layout is usually referred to as ladder network. Thus
RC greater than unity at this particular
phase shift around the loop is 360°(or 0°). If AB is
function of the RC network can be
calculated as:
frequencv, oscillations can start. The transfer

6 6
1+RC+ RC+ R°C
S

Let, s =jo:
1
..ß=. where. , = 2TRC

coupled amplifier which

Wein-Bridge oscillators: The circuit consists of two state RC
used as the feedback network
provides the phase shift of 360° or 0°, A balanced bridge is
which has no need to provide any additional phasce shift.
Multivibrators are classified as:
which neither state 1s
a. Astable nultivitrators: Astuble multivibrator is a multivibrator in
stable. These are twO quasi-stable (temporary) states.
state. Wnen
b. 1onostable multivibrators: It has one stable state and one auasi stable state for a
pulse is applied to the input circuit. the circuit state changes to unstable
predeternined time. switches
Schmitt Trigger Circuits: The Schmitt trigger is a comparator application which
Itthen
the output negative when the input passes upward through a positive reference voltage. passes
uses negative feedback to prevent switching back to the other state until the input
through a lower threshold volkage. thus stabilizing the switching against rapid riggeme
noisc as it passes the trigger point.
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 ANALOG &DIGITAL ELECTRONICS

Very Short Type Questions

1. A class B push-pull power
amplifier has an a.c. output of 10 watts. The d.c.
power drawn from the power supply
a) 10 watts under ideal condition is [WBUT 2007]
b) 12.75 watts c) 15 watts
Answer: (b) d) 20 watts

2.Astable multivibrator may be used as

a) frequency to voltage converter [WBUT 2010, 2014]
c) squaring circuit b) voltage to
frequency converter
Answer: (c) d)comparator circuit

3. Schmitt trigger is also known as

a) squaring circuit [WBUT 2010]
b) blocking oscillator
c) sweep circuit
d) astable multivibrator
Answer: (a)
4. For a wide range of oscillations in the
audio range, the preferred oscillator is
a) Hartley b) Phase shift c) Wien-bridge [WBUT 2010]
d) Hartley and Colpitt
Answer: (c)
5. If the input ofa Schmitt trigger is a sawtooth wave, the output is
a) sine wave
b) triangular wave WBUT 2010]
c) pulse waveform d) without any change but
Answer: (b) amplified
6. The net phase shift of
Wien-bridge oscillator around the loop is
a) 90° b)180° c) zero
[WBUT 2010, 2017]
d) 360°
Answer: (d)
7. Maximum efficiency of transformer coupled class
a) 78.5% Apower amplifier is
b) 50% c) 25% d) 100%
Answer: (b) [WBUT 2011]
8. A 2-transistor class B power amplifier is
a) push-pull b) dual commonly called WBUT 2011, 2012]
c) differential d) none of these
Answer: (a)
9. ClassCamplifiers are used as
a) AF
amplifiers b) detectors
WBUT 2011]
c) RF amplifiers d) none of these
Answer: (c)

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[WBUT 2011]
circuit has
10. A bistable multivibrator b) two stable
states
a) two unstable states d) none of these
c) quasi-stable states
Answer:(b)
[WBUT 2011, 2012, 2014]
has a frequency
11. A Wien-bridge oscillator c) 1/2x RC d) none of these
a) 1/2rRC b) 1/RC
Answer: (c)
oscillators is used at audio frequency?[WBUT 2011, 2012]
12. Which of the following
b)Wien-bridge Oscillator
a) Crystal.Oscillators d) Colpitt's Oscillator
Oscillator
c) RC Phase-shift
Answer: (c)
[WBUT 2012]
has
13.Astable multivibrator b) one stable state
a) No stable state d) none of these
c) two stable states
Answer: (c)
[WBUT 2012, 2014]
generates
14. Schmitt trigger circuit b) square wave
a) Triangular wave d) none of these
c) saw tooth wave
Answer: (b)
[WBUT 2012]
an amplifier is
15. Negative feedback in b) increased noise
a) reduced gain d) reduced bandwidth
phase
c) increased frequency &
Answer: (c)
WBUT 2013]
operates in the linear region at all times is d) Class C
16. An amplifier that b) Class B c) Class AB
a)Class A
Answer: (a)
2013]
efficiency of Class A power amplifier isd) WBUT
17. The maximum theoretical c) 75% 98%
a) 50% b) 25%
Answer: (a)
WBUT 2013]
problem for
18. Cross-over distortion is a b) Class B amplifiers
a) Class Aamplifiers
c) Class C amplifiers d) Class AB amplifiers
Answer: (b)
[WBUT 2014]
19. A2-transistor class-B amplifier is usually called
b) inverting amplifier
a) dual amplifier d) push-pull amplifier
c) symmetrical amplifier
Answer: (d)
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 ANALOGe DIGIIAL ELECTRONICS
20. The gain of an amplifier in general is wBUT 2014)
a) imaginary b) complex c) real d) none of these
Answer: (d)
21. For critical modulation the value of modulation index is
[WBUT 2014]
a) 0.5 b) 1 c) 0.75 d) 0.1
Answer: (d)
22. The Q point in avoltage amplifier is selected in the middle of the active region
because WBUT 2014]
a) it gives better stability
b) the biasing circuit then needs less number of resistors
c) the circuit needs a small d.c. voltage
d) it gives a distortion less output
Answer: (a):
23. The output voltage of the circuit [WBUT 2014)
10 Q
V,
V, =|V

10 2 20 2

a) 0 v b)1 V c) 2 V d) 3 V
Answer: (a)
24. A 2-transistor class B power amplifier is commonly called WBUT 2015]
a) push-pull b) dual
c) differential d) none of these
Answer: (a)
25. Astable multivibrator has WBUT 2015)
a) no stable state b) one stable state
c) two stable states d) none of these
Answer: (a)

26. Schmitt trigger circuit generates [WBUT 2015]

a) triangular wave b)square wave
c) saw tooth wave d) none of these
Answer: (b)
27. A Wien-bridge oscillator has a frequency [WBUT 2015]
a b) c) d) none of these
2rRC RC 2rRC
Answer: (c)

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28. Which of the following oscillators is used at audio frequency?

b) Hartley oscillator
WBUT 2015]
a) Crystal oscillator
c) RC phase-shift oscillator d) Colpitts oscillator
Answer: (c)
29. Negative feedback in an amplifier is [WBUT 2015]
a) reduced gain b) increased noise
c) increased frequency and phase d) reduced bandwidth
Answer: (c)
30. Cross-over distortion occurs in (WBUT 2016, 2018]
a) Class A amplifier b) Class AB amplifier
c) Class C amplifier d)Push pull amplifier
Answer: (b)
31.The minimum distortion during amplification is obtained in WBUT 2016]
a) Class A amplifier b) Class B amplifier
c) Class Camplifier d) Class AB amplifier
Answer: (b)
32. A class C amplifier conducts for WBUT 2016]
a) b) 27 c) <I d) 0
Answer: (d)
33. A pure sine wave output is possible with (WBUT 2016]
a) Hartley oscillators b) Wien bridge oscillators
c) RC phase shift oscillators d) Colpitt oscillators
Answer: (b)
34. The Barkhausen criterion for sustained oscillation is [WBUT 2016]
a) Aß= 1 b)48|21 c) |48|<1 d) NOT
Answer: (b)
35. Multivibrators WBUT 2016, 2018]
a) Generate square wave b) Convert sine to square wave
c) Convert triangular to sine wave d)Convert triangular to square wave
Answer:(a)
36. The output pulse width for a monostable multivibrator using IC 555 where
external resistance and capacitance are 20 k2 and 0.1 uF is WBUT 2016, 2018]
a) 2.1s b) 2 ms c) 2.5 ms d) 2.2 s
Answer: (d)

37. Inorder to generate a square wave form a sinusoidal input signal one can2016]
[WBUT uGe
a) monostable multivibrators b) clipper and amplifiers
c) Schmitt trigger circuit d) both (b) and (c)
Answer: (d)
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 ANALOG& DIGILAL iLLIRONICS
38. The efficiency of Class A
a) 0.5
amplifier is (WBUT 2017]
b) 1 c) 0.25 d) 0.1
Answcr: (a)
39. If the Q of a single stage single turned amplifier is doubled, then bandwidth will
a) remain the same
b) become half WBUT 2017]
c) become double d) become four times
Answer: (a)
40. Which of the following mode of BJT can be used as an amplifier? [WBUT 2018]
a) CB b) CC c) CE d) None of these
Answer: (c)
41. Apure sine wave output is possible with [WBUT 2018]
a) Hartley oscillators b) Wien-bridge oscillators
c) RC phase shift oscillators d) Colpitt oscillators
Answer: (b)
42. How is a conducting diode biased? [WBUT 2019]
a) Forward b) Inverse c) Poorly d) Reverse
Answer: (a)

43. The current gain of a p-n-p transistor is [WBUT 2019]

a) the negative of the n-p-n current gain
b) the collector current divided by the emitter current
c) near zero
d) none of these
Answer:(d)

44. The control terminal in a BJT transistor is [WBUT 2019]

a) The collector b) The base c) The emitter d) none of these
Answer: (a)

45. For the operation as an amplifier the base of an n-p-n transistor must be
[WBUT 2019]
a) +ve with respective to emitter b) -ve with respect to the emitter
c) 0 V d) +ve with respect to collector
Answer: (a)

46. The input resistance of a common base amplifier is [WBUT 2019]

a) very low b) very high c) same as CE d) same as CC
Answer: (a)

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emitter byns.
common-emitter amplifier has voltage gain 100. If the
47. A certain WBUT 2019)
capacitor is removed, voltage gain wll decrease
unstable b)
a) circuit will become d) q-point will shift
increase
c) voltage gain will
Answer: (b)
from BJT mainly because of WBUT 2019]
JFET differs performance
48. A
a) power rate b) high frequency
d) higher speed
c)higher input impedance
Answer: (c)
used as
WBUT 2019)
49. BJT in CC mode carn be c) Intermediate stage
a) Amplifier b) Buffer
Answer: (b)
2022]
what voltage the capacitor charges? WBUT
50. In the astable amplifier, up to
Answer: 5.4 volt
of the
Schmitt Trigger is sawtooth wave, what will be shape
51. The input of a WBUT 2022]
output?
Answer: Triangular wave
efficiency (low to
Classes of power amplifier according to their WBUT 2023]
52. Arrange the Class C, Class AB
high)Class A, Class B,
Answer: Class AB Class C
Class A Class B
Class 50% - 7S.5% High 100%
25% or 50% 78.5%
Efficiency
as an Astable
following figure shows an IC 555 Timer connected
53. The circuit of of the resistors
The value of the capacitor C is 10nf. Find the values
multivibrator. output voltage.
duty cycle of 0.75 for the [WBUT 2023]
10kHz and a
R, and R, for a frequency of

RA

Th

Ri
Tr
R

555 Timer
IC

Discharge

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Answer:
Duty cycle. a =
Ton =aT = 0.75T
=0.75x10 =75u scc.
As Tn =0.7C(R, +R,)
75x 10
0.7x10
= R, + Ry
R, + R, = 10.714 kQ
and ToFF =0.7CR,
25x10
R, = =3.57 k2
0.7x10 %
R, =7.25 kQ

54. The a.c. output power of a Class B push-pull power amplifier is 10 watt. What
will be the d.c. input power drawn from power supply when the efficiency of the is
maximum. [WBUT 2023]
Answer:
The maximum power output is given by

Pac( mas) 2R,

The relationbetween the maximum power output and the maximum power dissipation in
each transformer is given by
Pdcl mas)
atma) 5Pde( max)
For an ideal class B push-pull amplifier. the maximum output power is five times the
maximum power dissipation in each transistor.
Power dissipation across each transistor= 10 W
The maximum power output one can obtain at the load from this circuit =5x 10 =50 W
55. Statement 1: Astable Multivibrator can be used for generating Square Wave.
Statement 2: Bistable Muitivibrator can be used for storing binary information.
Please state whether both the statements are true or false. [WBUT 2023]
Answer:
Both the statements are true

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Short Answer Type Questions

astable multivibrator using 555 Timer.
1. Draw and explain the operation of (WBUT 2011]
Answer:
The following figure shows the 555 timer IC that is
operated in astable mode. R

The three internal resistances (R) divide the voltage into

three parts. So =2V,/3; V, =V,/3while the R:
capacitor is changing and capacitor voltage in between
2>,/3 and V/3, the output of resistor of the
comparator undergoes a change in sign of their output,
, which is negative and therefore logic 0. If the capacitor is
charging and its voltage .tends to rise above 21,3. comparator 1 output jump to
positive saturation value, i.e., it is logic I at Rinput of flip-flop. Similarly when capacitor
isdischarging and its voltage tends to fall below V/3 and comparator 2 output jumps to
positive saturation value or logic Iat Sinput of flip-flop.
2. Define upper threshold, lower threshold, hysteresis voltage and centre voltage
related to a Schmitt trigger circuit. [WBUT 2011]
Answer:
Üpper threshold voltage: It is the voltage for low to high transition.
Lower threshold voltage: It is the voltage for high to low transition.
Hysteresis voltage: It is the difference of two voltages.
Centre voltage: It is the intermediate to V, and V.
3. Draw and explain the operation of Monostable multivibrator using 555 Timer.
WBUT 2012, 2015, 2017, 2019)
Answer:
The monostable multivibrator using 555 timer is shown in figure I. When a negative
going pulse is connected to trigger input (pin no.2) the output goes high. The terminal 7S
shorted by capacitor C. When the voltage across the capacitorCcomes Vre. then the
3

upper comparator in figure I changes the output from high voltage value to low voltage
value. The three internal resistance in figure I act as voltage dividers and it provides the
bias voltages of (2/3)Vçc to the upper comparator and (1/3)Vc to the lower comparato.
Since these two voltages fix the nccessary comparator threshold voltages. they also auds
in determining the timing interval. The input output voltage waveform is shown n
figure 1.

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 ANALOG &DIGITAL ELECRONICS

R
Negatne cdye 8
trigyets the tmer

Ouput

Fig: IMonostable Operation

The voltage across the external capacitor changes exponentially from 0 to
given by.

at time t=T.

2
Therefore. 3
V =V(|-ekr;
2 -TIR
A

or.T =1.1R,C...2)
Therefore. when the output is high, the time interval becomes, thuh = T
Therefore.

'high =1.IR,...3)
Figure 2 shows the wide range of output pulses that are obtained fromn the values of Ra
and C. Since the changing rate and comparator thresholds are both proportional to the
supply voltage. the timing interval given by equation (2) is independent of the supply
voltage.

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(uF)
100+t+
C.Capacitor
10
L.0 AOMQ
B1OKA0OKe
01R=18e
0.01
0.001 I.0S I00S
10uS 100uS IOnS 1OmS 100mS

time delay
Fig: 2 Graph of RC Combinations for different
+Vc
8
5K
RA cl 6r2/3Ve

Trigger Contrd!
input S
2

$SK
C Power
amp
Output T
Fig: 3Functional Block diagram
4. Draw and explain the Schmitt trigger circuit. WBUT 2012, 2015, 2019]
Answer:
V
-Vec

R
7
-Ve

V:

R:
R

Symbol

The Schmitt trigger is a comparator application which switches the output negative we
the input passes upward through a positive reference voltage. It then uses negative
feedback to prevent switching back to the other state until the input passes throug a
lower threshold voltage. thus stabilizing the switching against rapid triggering by nose a
ilpasses the trigger point.
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 ANALOG& DIGITAL ELECIRONICS

Application:
Schmitt irigger devices are typically used in open loop configurations for noise immunity
and closed loop negative feedback configurations to implement bistable regulators.
triangle/square wave generators, ctc.
5. What is the basic principle of oscillation? WBUT 2014)
What is Barkhausen criterion? [WBUT 2014, 2017]
Answer:
Oscillation means gain x feedback fraction = |
A
For apositive feedback system the overall gain can be written as. A, |- AB
Where, A is the gain of the internal amplifier. B is the feedback ratio. and -AB is the loop
gain. If AB = 1, from this equaion 4, tends to infinity. The amplifier then gives an
output voltage without requiring any externally applied input voltage. In other words. the
amplifier becomes an oscillator. This condition of unity loop gain, i.e. AB = 1is called
the Barkhausen Criterion.
This condition means that AB=l, and the phase angle of AB is zero or an integral
multiple of 360º. Therefore, the basic conditions for oscillation in a feedback amplifier
are (i) the feedback must be regenerative, and (ii) the loop gain must be unity.
6. What are the advantages of push-pull amplifier? Why the push-pull circuit is
called so? WBUT 2014]
Answer:
1" Part:
A push-pull amplifier possesses the following advantages:
1. There isno DC saturation of the core of the output transformer because th DC plate
currents flow through the output transformer in opposite directions due to the two
transistors. This reduces the size of the output trarnsformer.
2. As the AC signal frequency current does not pass through the common supply, the
push-pull amplifier has no regenerative effect on other stages. The common emitter
resistor for the two transistors doies not require a bypass capacitor.
3. It has less amplitude distortion in the output due to cancellation of all even order (2d
4th etc.) harmonics.
4. Any AChum or ripple currents from the DC power supply sources balance out in the
circuit and there is no hum in the output.
A
Class Bpush-pull amplifier without input signal draws very litle collector or plate
current resulting in great economy in battery power. The system is.therefore, suitable
for battery operated equipment including transistor radio receivers.
2nd Part:
Apush-pullamplifier is a combinationof two Class Aor Class B amplifiers so connected
that one amplifier amplifies the positive half and the other apmplifies the negative half of
the input signal and the amplified replica of the input voltage. Push-pull amplifiers give
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distortion than a single ended amplificr. In transistors. push-ndt

higher output with less with one PNP and the other NPN transistor
amplifiers having complementary symmetry
any transformers.
are used which do not need
Hz anda capacitance of 100 nE
has a frequency of 1000 resistanco
7. A Wien bridge oscillator
If the amplifier gain is 10, obtain the ratio of
the
Find the resistance. WBUT 2016]
the other arms.
Answer:

f= 10° H:C=(10° x10)F

A=10:R=?
1 0.159
f= 27CR 10-xR.
10 x10lxR=0.159
R= .159 =.159x10'2
l0-7
timer. [WBUT 2016, 2018]
Schmitt trigger circuit using 555
8. Draw and explain
Answer: Vcc (5 to 15V)

Reset

100K
R
6
output
7 555

.0luk 2
Fig. shows timer IC555 as
a Schmitt Trigger

100K R GND
.0lut

3/2 VH

1/2 V!

Input and output where forms

The input of two compilation threshold input (6) and trigger input (2) are connected
formed by R and R, .
together and externals biased at V, /2 therefore a voltage divider

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 ANALOG & DIGITAL ELECTRONICS

As upper comparator will trip at /3V and lower

comparator (2) at i/3V the bias
provided by resistances R, and R, is cantered within there too
The circuit can convert wave form of thresholds.
shape.
9. Calculate the width of the generated pulse.
Answer: [WBUT 2019]
Following formula or equation is used for
Monostable multivibrator pulse width: Monostable multivibrator pulse width.
T, =1.| *R|* CI Where
CI=Capacitance and RI = Resistance.
10. Find the oscillation frequency f of the phase shift
and C=6.5 nf.
oscillator when R=10k2
[WBUT 2022]

HE
R R R

Answer:
The frequency produced by the above shift oscillator is given by:
1
f=
2rRCW6
frlkHz.
11. Derive the maximum efficiency of a class B amplifier.
[WBUT 2023]
Answer:
The power efficiency of class Bamplifier:
For the hal f-sine loop, I, is
The output of I,. isfrom 0to n and z to 27 it is zero

Therefore. input power P. for the input voltage of transistor V,. is

P. =2x

Here. factor 2 is introduced as therce are two transistors in the push-pull amplifier.
R.M.S. value of collector current (). mas

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(V)
R.M.S. value of output voltage=
Output power P, is
(.-)x
P= 2

Overall efficiency. n=
(P) x 100= 251 =78.5%
P.)! amplifier is 78.5%
maximum conversion efficiencv of aclass B push-pull
The
amplifier. [WBUT 2023]
the operation of
transformer coupled Class A
12. Explain
Answer:
Power Amplifier also sometimes referred to as single
Transformer CoupledClass A only one transistor) is used
ended (denoting
ended power amplifier. The term "single a direct
push-pull amplifier using two transistors. In case ofcollector
to distinguish it from theamplifier, the quiescent current flows through the
the
coupled class A power
wastage of dc power in it. This dc power dissipated in
resistive load and causes large the useful ac output power.
Furhermore, it is
contribute to coil of a
load resistor does not the output device such as in a voice
pass the dc through
generally inadvisable to
loudspeaker. For these reasons
an
NN:
suitable
arrangement using
transformer for coupling the load (say, Loudspeaker
amplifier is
a loudspeaker) to the
R
figure
usually employed, as shown in Class
below. This Transformer Coupled Cn Step-down
transformer
A Power Amplifier arrangement
enhances the conversion efficiency by a
factor of 2 by eliminating the dc power
the
dissipation in the load. Since R
transformer has
primary of the
negligible dc resistance. there is
negligible dc power lost at this point.
The ac power is, however,
coupled Transformer Coupled Class A Power Amplifier
magnetically across the transformer Class A Power Amplifier method also
load R. This Transformer Coupled be
into the through the load. which otherwise could
prevents a large dc current from flowingsince it would cause saturation of the magnetic
harmful if the load were a loudspeaker,
audio signal.
circuit and impair the reproduction of the matching.
This arrangement also permits impedance divider
above figure, R andR provide potential bypasS
power amplifier circuit shown in
In a for bias stabilization. The emitter
biasing and emitter resistor RE is meant feedback in the emitter circuit. The input
capacitor Cç is meant for preventing negative
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 ANALOG &DIGITAL ELECTRONICS

capacitor Cin couples ac signal voltage to the base of the transistor but biocks any dc from
the previous stage. A step-down transformer of suitable turn ratio (a =N/N, ) is
provided to couple the high impedance collector circuit to low impedance load.
Long Answer Type guestions
1. a) Draw the circuit diagram of a transformer coupled Class Apower amplifiers
and explain its operation.
b) Calculate the total efficiency of this amplifier.
c) What is cross-over distortion found in Class Bpower amplifiers? How it can be
eliminated? (WBUT 2011]
Answer:
a) Transformer coupling becomes nccessary when the load impedance is smaller than the
one needed in the collector for matching o, when the load is to be isolated and cannot
carry the dc collector current.
4Vc
Vo

R
R

Fig: 1. Transformer coupled class Aamiplifier

Fig. 1. shows a class Aamplifier circuit with transformer coupling. Since it is a class A
amplifier and same fixed biasing scheme is used, the operation is similar to the normal
class A amplifier as described previously. The only difference is, here load is coupled
with a transformer.

b) Maximum conversion efficiency

2
P
-x100% =
0.ac V/2R,-x 100% =50%
P.i.dc

c) The advantages of class Bamplifier over class Aamplifier are

Higher Conversion efficiency (Class B-78.5% while for Class A-50%)
Greater Power output
No power loss in the absence of ac input signal.
However, there are some disadvantage also, (i) self Bias cannot be used with class B
configuration (ii) Amplifiers are Bulky &expensive.
Major draw back of class B operation is crossover distortion. For class B operation, the
BE junction voltage must be greater than cut-in voltage (V#> 0.65 V) so that linear
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guaranteed. Whenever there is a zero crossing at the input. we get output o.

operation is th
becomes ON) only after the input voltage reaches +VB; (or. -Va: for
the transistor results in a distortion occurs which is
known
negative half-cycle). This phenomenon
crossover distortion.
Input
1oltagc
-V

Output
voltage

Crossover
Crossover distortion
distortion
oscillation?
What are the conditions necessary for the generation of circuit
2. a) Bridge oscillator using Opamp with a
b) Explain the operation of a Wien
diagram. frequency of oscillation. [WBUT 2011, 2013, 2017]
c) Derive an expression for its
Answer: A
overall gain can be written as. A,
a) For a positive feedback system the |- AB
feedback ratio, and -AB is the loop
Where. A is the gain of the internal amplifier, B is the
amplifier then gives an
gain. If AB = 1. from this equation A, tends to infinity. The the
any externally applied input voltage. In other words,
output voltage without requiring gain. i.e. AB = | is called
amplifier becomes an oscillator. This condition of unity loop
the Barklhausen Criterion.
integral
This condition means that|AB=1, and the phase angle of AB is zero or an
amplifier
multiple of 360°. Therefore. the basic conditions for oscillation in a feedback
are (i) the feedback must be regenerative. and (ii) the loop gain must be unity.
b) Figure shows the circuit ofa Wien-bridge oscillator. The circuit consists of atwo-state
RCcoupled amplifier which provides a phase shift of 360° or 0°, A balanced bridge is
used as the feedback network which has no need to provide any additional phase shifi.
The feedback network consists of a lead-lag network (R-C and Ry-C:) and a voltage
divider (R,-Ri). The lcad-lag nctwork provides a positive feedback to the input of the first
stage and the voltage divider provides a negative feedback to the emitter of O,.

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 ANALOG &DIGITAL ELECTRONICS

-o V
Lead-lag B
network
RS R.
R,

R R,
Ri RS

Feedback sigmal
Wien Bridge oscillator
c) If the ridge is balanced, R,/R, =(R, -jx, R.(-X,R,- jX)} where X1
and X(2 are the reactances of the capacitors. Simplifying equation and equating the real
and imaginary parts on both sides, we get the frequency of oscillation as,
1

2rR, R,C;C,
IfR, = R, =R and C=C= C, then fo =:
2TRC
The ratio of R; to R4 greater than 2will provide asufficient gainfor the circuit to oscillate
at the desired frequency. This oscillator is used in commercial audio signal generators.

3. a) What are the advantages of negative feedback? WBUT 2012]

b) Explain the operation of a phase shift oscillator with circuit diagram.
c) Derive an expression for its frequency of oscillation.
Answer:
a) Advantagesof negative feedback:
1. Transfer Guin
Anegative feedback system can be represented with the following block diagram shown
in Fig. From the diagram we can easily deduce the transfer gain of the system with
feedback.
Xyor X,
X, = Input signal from source X X.
A
X= Difference signal fed to amplifier
X, = Output signal
A =Transfer gain of amplifier or, Open loop gain X,= BX,
B =Feedback ratio
B

Fig: Gain. with Feedback

With negative feedback. X= X,-X,. But. X, = BX,
X,=X,- BX,
Also. from the transfer characteristics of the basic amplifier. N, =AX,
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From above equatons.X, = A(X, - BX)

or. X, =AX, - ABX,: or, X, =A (X, - BX) :
A
or.
X, 1+ AB
We define. transfer gain with feedback
A
. i.e. A,= 1+ AB
On the
X, and the transfer gain reduces.
For negative feedback, j+AB>1 4, <|4 4
4, >A. Considering a special case when |
feedback
other hand. for positive feedback. The system produces output
= o for positive
B=0 or, A.B = -1 we get A,
(X) in the absence of inputprinciple of oscillator.
(X, =0). This is the basic This factor is called reurm
gain is reduced by a factor I +AB.
For negative feedback
difference (D).
gain.
The factor - AB is called the loop
Feedback can be expressed in dB,
(1
F = 20 log| =20 log
A 1+AB)
2. Sensitivity
We define, Sensitivity, S =
dA, lA,
dA/A
equation
where D= desensitivity factor. Rearranging above
dA,
A,
A, is less than that in A.
As, |D >l(for negative feedback) the percentage change in
is less pronounced in a
From the above equation, it is clear that the effect of changefeedback. Hence, negative
negative feedback system compared with the system withthenoratio of fractional change in
feedback increases stability of an amplifier. Sensitivity is
gives a measure of the
close loop gain to the fractional change in open gain. It
improvement in stability.

3. Input Impedance
the type of mixing network.
Input impedance of a negative feedback system depends on
For Series Mixing, opposes V,. So the input
From the circuit in figure it is obvious that feedback voltage V
current I, is less than it would be ifV, was absent.

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 ANALOG &DIGITAL ELECTRONICS

When feedback was absent.

In the presence of feedback, V, =V,-V,

= V,- ABV, ’V, =(1+ AB)V, -V, +
R.

Hence, R, V,_(+AB)V, =R(1+ AB)

1, Fig. Input impedance with series mixing
Input impedance increase by a factor (1 +AB). This analysis is valid for voltage-series
topology with voltage amplifier (A = A,) and for current-series topology with trans
conductance Amplifier (A =Gy).
4. Output lmpedance
Output impedance of a negative feedback circuit depends on the type of sampling
network.

5. Band Width
From the frequency response of an amplifier in Fig., we can write, low frequency gain,
A,
I-j,/)
Ay
and high frequency gain, A,
1+jf/S)
where, A = mid band gain; f.= lower cut-off frequency; f = higher cut-off frequency
A

AmN2

frequency
Figure: Frequency Response of an Amplifier
b) & c) An example of an oscillator circuit that follows the basic development of a
feedback circuit is the phase-shift oscillator. Figure I shows the circuit of a phase shift
oscillator. The operational amplifier provides a phase shift of 180° as it is used in the
inverting mode and remaining 180° phase shift is produce by three RC network.. This
form of RC layout is usually referred to as ladder netvork. Thus the total phase shit
around the loop is 360°(or 0°). If Aß is greater than unity at this particular frequency.
oscillations can start. The transfer function of the RC network can be calculated as:

B= 6
V, 1+- RC+ R'C'. R'C

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Let S =j0:

..ß=
1+S(4,//) -j)-U,//N
where. , =
2R
Ampl1tier
R

Roa

Feedback network

Fig: IPhase shift Oscillator Circuit

For A,ß =1, Bshould be real. So the imaginary term in the above equation must be equal
to zero, that is, =0; 0r,

The frequency of oscillation fo is given by, f, =

Vo(2nCR)
Also, the loop gain 4,ß=1;
or,
A, =1; or, A, 2-29
1-sf,/L}
From this expression, we observe that the gain of the inverting op-amp should be at least
29 or feed back resistance, R,=29 R,
The gain A, is kept greater than 29 to ensure that variations in circuit parameters will not
make |4,ß<1, otherwise oscillations will die out.
Since there are three stages, the total loss for the feedback network will be 0.125.
Therefore, the inverting amplifier needs a gain of 8 in order to set the Aß product unity.
Phase shift oscillator is particularly suited to the range of frequency from several hertz to
several hundred kilohertz.

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 ANALOG& DIGIHAL. EIECTRONICS
4. Explain the operation of a class-B push-pull power amplifier with a neat circuit
diagram. Determine its collector circuit efficiency. Explain why even harmonics are
not present in push-pull amplifier. [WBUT 2015]
Answer:
T
0000000000

H Ve
R

Fig: Push Pull.configuration

With only one class Bamplifier, the output is not a faithful reproduction of input as only
one half cycle is present. For both cycles, we go for push pull arrangement (figure) where
two class B amplifiers are used for two half cycles.
No even harmonics are present at the output due to push-pull configuration. This can be
proved in the following way. Say collector current i, is the current flowing through load
which contains allthe harmonics when T, conducts.
1F, +a t a, cos Ol +u, cos2ot + a cos3ot
similarly when T, conducts current i, flows through load which is 180 phase shifted
with respect to içl:
iFi,(olT + n)=1, +a, - a, cos Ol +a, cos2 ot - a,cos3 ot
Total current, i, =ia -i2
as i and i, flows in opposite directions. So even order harm-onics get cancelled.
From the expressions above, we see that dc components of the collector currents i, !
and i, oppose each other magnetically in the transformer core. This eliminates anv
tendency toward core saturation and consequent nonlincar distortion that might arise
from the curvature of the transformer magnetization curve.
The effects of ripple voltages that may be contained in the power supply because of
inadequate filtering willbe balanced out.
V

n-p-n

V.

R
pn-p

Vc
Fig: Complementary symmetry push-pullconfiguration
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Eficicncy
180° phase difference exists so harmonic produced by each transistor cancel out thereby
almost distortion frec output is bcing obtained.
i,=(., -1,) I, =

So.
So. total , current for two transistor

1, =21, = 21, P, (de) =V, xly = 2lmV

mn
AC power delivered to load, P(dc) = 2
Totalcollector dissipation
P(de)= 21, 4

P(de) 2
-nloverall)= P(dc) x100= 21,.

Under ideal condition, maximum P or in load =V,.

.:. Maxinna = -x100 =78.5%
4

5. What is the Barkhausen criterion for a feedback amplifier to function as an

oscillator? Give a neat circuit diagram of Wien bridge oscillator and explain how it
works. Find an expression for the frequency of oscillation of the astable
multivibrator. WBUT 2015]
Answer:
1" Part:
A
For apositive feedback system the overall gain can be writen as, A, =
|- AB
Where. A is the gain of the internal amplifier. B is the feedback ratio, and -AB is the loop
gain. If AB -1. from this cquation A, tends to infinity. The amplifier then gives an
output voltage without requiring any externally applied input voltage. In other words. the
amplifier becomes an oscillauor. This condition of unity loop gain, ie. AB = I is caled
the Barkhausen Criterion.
This condition means that 4B =1, and the phase angle of AB is zero or an integral
multiple of 360°. Therefore. the basic conditions for oscillation in a feedback amplifier
are (i) the feedback must be regenerative. and (i) the loop gain must be uity.
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 ANALOG &DIGITAL ELECTRONICS

2nd Part:
Figure shows the circuit of a Wien-bridge oscillator. The circuit consists ofa two-state
RC coupled amplifier which provides a phase shift of 360° or 0°. Abalanced bridge is
used as the feedback network which has no need to provide any additional phase shift.
The feedback network consists of a lead-lag network (R-C and Ry-C) and a voltage
divider (R-R4). The lead-lag network provides a positive feedback to the input of the first
stage and the voltage divider provides anegative feedback to the emitter of Q,.

Lead-lag B
network R SRel R Re
R C. C.

R:
R R Ri R
D

Feedback signal
Fig: Wien Bridge oscillator
If the bridge is balanced,
R&JR, =(R -jXR,-jX)R,- jX(:}
where X1 and X( are the reactances of the capacitors. Simplifying equation and equating
the real and imaginary parts on both sides, we get the frequency of oscillation as,

2r R,R,C,C;
If R, =R-R and C=C-C, then fo =
2RC
The ratio of R; to R4 greater than 2 will provide a sufficient gain for the circuit to oscillate
at the desired frequency. This oscillator is used in commercial audio signal generators.
3rd Part:
Figure I.(a) shows a basic symmetrical Bipolar Junction (BJT) astable multivibrator in
which components in one half of the circuit are identical to the components in the other
half. The square wave output can be taken from collector point of T, or T;, The
waveforms at base and collector of transistors TË and T; are shown in figure 1.(b).

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p--Vee

SR:$R:

(a)

Totf

T
on

VVB

Diseharge
-Vc L----, of BC,
lofr

off
Ve
T:

T-on

-Vie Discharge (b)

B,C; T: ofl
Fig.l.(a) Astable miltivibrator (b) Waveforms at the
Collector and base of transistors T; and T in astable multivibrator
In figure l(a). R, and R, are the collector resistances for transistor TË and T:
respectively C and C; are coupling capacitors. R, and R, provide on state base current
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 ANALOG& DIGIAL ELECIRONICS
to the NO transistors respcctively during saturation region. In symmctrical multivibrator
R, = R, .R, = R, and C,= C ic., the componcnts in one half of the circuit are
considercdto be cqual to their components in thc other half.
Frequency of Oscillutions
The frequency of astable multivibrator or free running multivibrator is given by.
0.7
Total time period (T) 1.39 RC RC
6. a) What are the advantages and disadvantages of negative
b) Anegative feed back amplifier has the following feedback?
parameters:
Open loop Gain A=200; feedback ratio B=0.02 and input voltage I = 5 mV
Compute the following
i) Gain with feedback
ii) Output voltage
ii) Feedback factor
iv) Feedback voltage.
WBUT 2016]
Answer:
a) Advantages
1. Gain sensitivity. Variations in the circuit transfer function (gain) as a result of changes
in transistor parameters are reduced by feedback. TIhis reduction in sensitivity is one of
the most attractive features of negative feedback.
2. Bandwidth extension. The bandwidth of a circuit that incorporates negative
feedback is
larger than that of the basic amplifier.
3. Noise sensitivity. Negative feedback may increase the signal-to-noise ratio if noise is
generated within the feedback loop.
4. Reduction of nonlinear distortion. Since transistors have nonlinear characteristics,
distortion may ap-pear in the output signals, especially at large levels. Negative feedback
reduces this distortion.
5. Control of impedance levels. The input and output impedances can be increased or
decreased with the proper type of negative feedback circuit.

Disudvantages
1. Circuit gain. The overall amplifier gain, with negative feedback. is reduced compared
to the basicamplifier used in the circuit.
2. Stability. There is a possibility that the feedback circuit may become unstable
(oscillate) at high frequencies.

b) 4= 200. B=.02, V, =5mV

200 200
i) A, = =40
|+ AB |+200 x.02 1+4

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ii) Gain = =200 = =, =l0 x10=|V

5x]0
iii) Feedback factor =B..= 200 x.02 =4
types of
7. a) What do you mean by power amplifier? How different push-pull
are made in power amplifier? Explain the operation of
Class B claampl
ssificifatieiro?n
b) What is crossover distortion? WBUT 2016])
Answer:
a) 1 Part:
Power Amplifiers are large signal amplifiers, which are des1gned to give power gain witk
reasonable efficiency. This gain in output ac power is achieved by converting dc power
from supply to ac power at the output.

2" Part: Different power amplifiers are

Class A. Class B.Class AB and Class C

Questions.
3* Part: Refer toQuestion No. 4 ofLong AnSwer Type
Questions.
b) Refer to toQuestion No. 10(b) of LongAnswer Type
the
8. a) What are the possible classification of power amplifiers depending on
position of their Operating point?
b) For a Transformer coupled class A amplifiers draw the AC load line. Hence
calculate the maximum value of efficiency. efficienc.
c) For class B push-pull amplifier calculate the maximum value of
[WBUT 2018]
Answer:
a) On the basis of mode of operation i.e. the portion of the input cycle during which
collector current flows, the power amplifiers may be classified as follows:
Class A Power Amplifier:
When the collector current flows at all times during the full cycle of the signal. the power
amplifier is known as class APower Amplifier.
Class B Power Amplifier:
When the collector current flows only turing the positive half cycle of the input signal.
the power amplifier is known as class B Power Amplifier.
Class C Power Amplifier:
When the collector current flows for les than half cycle of the input signal, it is known a5
class C Power Amplifier.
There forms another amplifier called Class AB amplifier. if we combine the class Aand
class B anplifiers so as to utilize the advantages of both.
Before going into the details of these amplifiers, let us have a look at the important terms
that have to be considered to determine the efficiency of an amplifier.

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 ANALOG kDIGIIALELECTRONICS

b) Refer to Question No. lla) &(b) of Long Answer Type Questions.

c) Refer to Question No. 4(7" &2d Part) of Long Answer Type Questions.
9.voltage.
Calculate duty Cycle. Draw Hloop and find the expression for Hysteresis
(WBUT 2019]
Answer:
1" Part:
A Schmittrigger is a circuit which generates an output waveform of a square wave of a
particular duty cycle. Itcan be implemented on several devices. however most commonly
on the operational amplifier.
-\

UTP

V.
W
LTP
R

+V,
R

-V,

When we give a positive feedback to the opamp. it nomore behaves as a linear IC. If the
input voltage difference (i.e. Vp-Vn) is greater than 0, then it gives a +Vsat output and if
the input voltage difference is lesser than 0V, i gives a -Vsat output.
This is the idea behind the Schmitt trigger. Now the output of the opamp is fed back to
the non inverting terminal of the IC. This is used to control the upper and lower threshold
voltages in the case of a Schmitt trigger. To vary the duty cycles, we use diodes and more
resistors.

2nd Part:
H loop:
Circuits with hysteresis are based on the fundamental positjve feedback idea: any active
circuit can be made to behave as a Schmitt trigger by applying a positive feedback so
that the loopgain is more than one. The positive feedback is introduced by adding a part
of the output voltage to the input voltage.
out

in

-M

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Expression for hystercsis Voltage:

The difference between the two threshold voltage is known as the hysteresis
two threshold voltages. the noise immunity of the circuit can be increased Because
by of
this Schmitt trigger. The Schmit trigger circuit is characterized by the hysteresis
the voltage transfer curve
using
Curve or
Schmitt Trigger - Input Characteristics
Hysteresis Voltage Plot

Vigi
V

-Ve

AVT = (VupT- - VigT- )Volt = Hysterisis Voltage.

10. a) Define voltage, current and power amplifier.
b) Write the different classes of power amplifier.
c) Draw the circuit diagram of a class B push pull transistor amplifier. Explain the
operation.
d) Derive the maximum efficiency of a class B amplifier. [WBUT 2022)
Answer:
a) Avoltage amplifier is the one that produces an output signal with increased voltage
level when a low voltage signal is input to it. A voltage amplifier is used in such
applications where we need signal trans1mission at higher voltage through a long wire.
Acurrent amplifier is an electric device that is used to increase the magnitude of an
input signal's current by a preset signak.
As its name implies. a power amplifier is an electronic device which boosts the
power
level of an input signal.

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 ANALOG& DIGITAL ELECTRONJS
b)
Class A Class B

Conduction Conduction
Angle 360° Angle 180°

Class AB Class C

Conduction Conduction
Angle 180°-200° Angle 100°-1 50°

Classes of Power Amplifiers

c) Refer to Question No. 4 of Long Answer Type Questions.

d) A push-pull circuit uses two transistors working in class B operation. For class B
operation, the Q-point is located at cut-off on both d.c. and a.c. load lines. For maximum
signal operation, the two transistors in class Bamplifier are alternately driven from cut
off to saturation. This is shown in Fig.1 (). It is clear that a.c. output voltage has a peak
value of VCE and a.c. output current has a peak value of lc'haye The same information is
also conveyed through the a.c. load line for the circuit (as shown in Fig. 1(ii))
: Peak a.c. output voltage = VCE
Since the two transistors are identical. half the supply voltage is dropped across each

transistor's collector-emitter terminals i.e. V.,=

Ve.
Also peak voltage across each transistor is , and it appears across R, .
2 R, 2R,
Peak a.c. output current ua)=
2R,
Maximum average a.c. output power ms 1S

Pomas) = Product of r.m.s values of a.c. outputvoltage and a.c. output current
V

2 2 4 2 )
. Pamas) 0.25 V,, 1, (w)
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The input d.c. power from the supply I,, is

2R

Cload line
2

Q-pont

()
()
Fig. I
where I is the average current drawn from the supply V.Since the transistor is on for
alternating half-cycles. it effectively acts as ahalf-wave rectifier.

..Max. collector n= Pamas) 0.25 V,) - x100 =0.251 x 100 = 78.5%

Pa
Thus the maximum collector efficiency of class B
power amplifier is 78.5%. Recall that
maximum collector efficiency for class A transformer coupled
amplifier is 50%.
11.a) Draw the circuit diagram of a
b) Derive the expression duty cycle Astable Multivibrator using IC 555 timer.
c) Explain why this is called Free and frequency of oscillation.
running oscillator. (WBUT 2022]

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 ANALOG &DIGITAL ELECIRONICS
Answer:
a) V

R
8
3 O Output

555
R
6

0.01uF

Astable Multivibrator Using 555 Timer IC

b)The charging and discharging time constants depends on the values of the resistors RI
and R2. Generally, the charging time constant is more than the discharging time constant.
Hence the HIGH output remains longer than the LOW output and therefore the output
waveform is not symmetric. Duty cycle is the mathematical parameter that forms a
relation between the high output and the low output. Duty Cycle is defined as the ratio of
time of HIGH output i.e., the ON timne to the total time of a cycle.
If TON is the time for high output and T is the time period of one cycle, then the duty
cycle D is given by:
D=Tox/T
Therefore, percentage Duty Cycle is given by:
%D=(TonT) *100
T is sum of ToN (charge time) and ToFF (discharge time).
The value of Tox or the charge time (for high output) Tc is given by:
Tx =T. =0.693 *(R, +R,)c
The value of ToF or the discharge time (for low output) Tp is given by
Tor =I, +0.693 *(R +R,)C
Therefore, the time period for one cycle T is given by
T=T +T;ny =T, +I,
T=0.693 *(R +R,)C+ 0.693 *R,C
T= 0.693 *(R+2R,)C
Therefore, %D=(T|T)*100
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oD=(0.693"(R -R))/(o.693-(R +2R)C)"100

%D=(R - R)/(R -2R.))"100
If T= 0.693*(R + 2R. )C, then the frequency fis given by
f=/T=/0.693"(R +2R, )C
f=14/(R +2R)C)
multi-vibrator. I is called
c) An as table multi-vibrator is also known as a free-running
levels during the
free-running because it alternates between two different output voltage
period of time. If vou
time it is on. The output remains át each voltage level for a detinite
looked at this output on an oscilloscope, you would see continuous square or rectangular
waveforms. The as table multi-vibrator has two outputs. but no inputs.

12. Write short notes on the following:

a) Voltage comparator using Op-Amp [WBUT 2014]
b) Cross over distortion WBUT 2015]
c) 555 timer [WBUT 2015]
d) Phase shift oscillator WBUT 2016, 2018]
e) Current shunt feedback [WBUT 2016, 2018]
Answer:
a) Voltage comparator using Op-Amp:
Avoltage comparator is an electronic circuit that compares two input voltages and lets
you know which of the two is greater. Its easy to create a voltage comparator from an op
amp, because the polarity of the op-amp's output circuit depends on the polarity of the
difference between the two input voltages.

In the voltage-comparator circuit. first a reference voltage is applied to the

(V ); then the voltage to be compared with the reference voltage is inverting input
applied to the
noninverting input. The output voltage depends on the value of the input voltage
1othe reference voltage, as follows: relative
Input Voltage Output Voltage
Less than reference voltage
Equal to reference voltage Negative
Zero
Greater than reference voltage Positive

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 ANALOG& DIGITAL ELECTRONICS
b) Cross over distortion:
Input
voltage
+V:
-V

Output
voltage

*,.

Fig: Crossover distortions Crossover

distortion
For class Boperation, the BE junction voltage must be greater than cut-in
0.65 V) so that linear operation is guaranteed. Whenever there is a zero voltage (VBE
crossing at the
input, we get output (or, the transistor becomes ON) only after the input voltage reaches
+VBE (or, -VB[ for the negative half-cycle). This phenomenon results in a distortion
occurs which is known as crossover distortion (see figure).

c) 555 timer:
The functional block diagram and 555 timer connection diagram are shown in figure
1.(c), 1.(a) and 1.(b).
Vcc

Ground
2 7 Discharge
555

3 6 Trigger
Threshold

4 5
Control Voltage
(a) Output
(b)
Reset
Fig.: 1.555 timer connection diagram (Top View)
(b) Metal Can package (Top View)

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V,

AAL
Control
NComparator I
voll R
6 Oer-rid1ng
Threshold Reset Cr
FF Dschar
41
7
Reset

Internal Rcf

Comparator 2
Trigger
R

Ground
diagram of 555 timer
Fig.: 1(c) Functional block
timer is available in two package styles, 8-pin circular style, TO-99 can or8.
The IC 555 important features of the 555 timer are given
below:
pin mini DIP or as 14-pin DIP. The
(1) Operating voltage ’ +5 V
to +18V
200mA.
(2) Capacitor to source or sink current of
short (monostable) modes.
(3) It has in both free-running (astable) and one microseconds through hours.
(4) It has an adjustable duty cycle and timing is from
The operating temperature of SE 555 is designed for the range from -55° to
(5)
+125°C while the NE 555 operates over a temperature range of0° to +70°C.
(6) The IC 555 timer is a very reliable, low cost and easy to use.
(7) Turn off time less than 2 sec.
(8) Compatible with both CMOS and TTL circuits.
(9) Maximum operating frequency greater than 500 KHz
(10) Nomally on and normally off output.
Application of timer IC SENE 555
Application of IC 5S5 are given below:
1. Monostable, astable multivibrator.
2. Digital logic probes.
3. In precision timing instruments/applications.
4. DC toDC converters.
5. Pulse generalion.
6. Tachometers.
7. Analog frequency meters.
8. Waveform generator.
9. Pulse width modulation.
10. Pulse position modulation.
| . Infrared transmitters.
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 ANALOG& DIGIAL ELECTRONICS
d) Phase shift oscillator:
Refer to Question No. 3(b) of Long Answer Type Questions.
e) current shunt fecdback:

Amplifier
A
R

The above figure is called current shunt feedback. In this connection, a fraction of output
currents covered into a proportionalvoltage by the feedback network and this applied in
purpled with input voltage.
R
output resistance R =
1+BAy

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NUMBER SYSTEMS

Chapter at a Glance
Anumber system is a framework where a set of numbers are represented by numerals in a
consistent manner. Ex: Decimal Number System, Binary Number System.
Compliments of a number: Complement used in digital computers for simplifying the
subtraction operation and for logical manipulation.There are two types of complements for
each base-r-system:
1. r'scomplement
2. (r-1)'s complement
|I'sConplement of Binary Number
e The 1's complement of binary number can be found by changing all 1 (one) to 0 (2ero) and all d
(zero) to 1(one).

2'S Complement of Binary Number

2's complement of a binary number can be found by addingl to l's complement of binary
number
Example: Find 1's and 2's complement of (1011010),
Changing all 1to 0and 0to 1.
0

0 0
l's complement = 0100101
Adding 1’
2's complement 0100110

Signed binary number representation with 1's and 2's complement method:
1.First, we convert Sand I to binary. 101 (5)
2. Now we add a sign bit to each one. Notice that we have padded 'l' with zeros so it
1()
will have four bits.
0101 (5)|
0001 (1)
3. To make our binary numbers negative, we simply change our sign bit from 0' to '1". I101 (-5)
1001 (-1)|
Here is a quick summary of how to find the l's complement representation of any decimal
number X.
1. Ifx is positive, simply convert x to binary.
2. Ifx is negative, write the positive value of xin binary
3. Reverse each bit.

1. First,we write the positive value of the number in binary. 0101(+5)

2 Next, wereverse each bit of the numberso I's become 0's and 0's become 1's 1010(-5)
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 ANALOG &DIGITAL ELECTRONICS
Here is a çuick summary of how to find the 2's complement representation of any decimal
number x. Notice the first three steps are the same as l's complement.
Ifx is positive, simplyconvert x to binary.
2 If x is negative, write the positive value of x in binary
3. Reverse each bit.
4. AddIto the complemented number.
1. First, we write the positive value of the number in binary. 0101 (-5)
2. Next, we reverse each bit to get the I's complement. 1010
3. Last. we add Ito the number. 1011(-5)

Very Short Type Questions

1. Hoy many 1's are present, in the binary representation of decimal number
(3 x512 +7 x 64 +5 x 8+ 3)?. WBUT 2007, 2018]
a) 8 b) 9 c) 10 d) 11
Answer: (b)

2. If (212) ×= (23) 1o where xis base (+ ve integer), then the value of xis
[WBUT 2007, 2008]
a) 2 b) 3 c) 5 d) 4
Answer: (b)
3. If, (128)10 = (1003) b, the possible base b is [WBUT 2010]
a) 3 b) 4 c) 5 d)6
Answer: (c)
4.The decimal equivalent of (1111100100), is WBUT 2011]
a) 998 b) 568 c) 996 d) none of these
Answer: (c)
5. The decimal equivalent of (AOF9.0EB)6 is WBUT 2011]
a) 44297.0967 b) 67902.8796 c) 41209.0572 d) none of these
Answer: (d)

6. Hexadecimalequlvalent of the binary no. 10111010001111 is WBUT 2013]

a) 2E8F b)1E7A c) 2F3B d) 1E9D
Answer: (a)
7. Two 4-bit 2's complements of binary numbers 1011 and 0110 are added. Then
the result will be (WBUT 2013]
a) 1111 b) 0010 c) 1101 d) 0001
Answer: (d)
8. The value of base Xfor which (211)X = (0.52)8 is WBUT 2014]
a) 08 b) 10 c) 16 d) 07
Answer: (
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9. If (54) =(X),,then the value of Xis WBUT 2017]

a) 123 b)312 c) 213 d) 132
Answer: (b)

10. If (212), -(23), , where X is the base of the number system, find X
[WBUT 2022]
Answer:
2x'+Ix +2x° =2-10 +3-10°
’ 2r+x+2= 23
’2r+x-21=0
>(r-3)(2x +7) =0
So, x=3

11. What is octal value of (2°)..? WBUT 2023]

Answer: (100),
Short Answer Type Questions
1. Find out the 7's complement of (-756) [WBUT 2007]
Answer:
For base R system, with word length =n bits, for a positive number N then R's
complement is N' =R" -N and (R - 1) 's complement is (R" -1)-N.
Here R=8(octal),n=3,then the 8's complement of 756,is 1000, - 756, = 22, and the
7's complement is (1000, -1)-756, =777-756 =21,.
2. Subtract 111001, from (101011), using 2's complerment method. [WBUT 2013]
Answer:
111001, =000110+1 =000111
101011, = 010100 +1 = 010101
011000

3. Carry out the following operation in binary using:1's complement arithmetic:

8-9= -1 [WBUT 2019]
Answer:
(8))0 = (1000)>
(9)10= (I001 )2
-(9)1o in 2's complement= (0110) +l=011
(8),0 -(9)1o = (1000), -(0111)>
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 ANALOG & DIGITAL ELECTRONICS

1000
0111

0001
[0-1=1* (* ’ borrow)]
.. (0001 ); =(-) Proved

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CODES

Chapter at a Glance
BCD (Binary Coded Decimal): Binary-coded decimal (BCD) isa digital encoding method
for decimal numbers in which each digit is represented by its own binary sequence.
In BCD, a numeral is usually represented by four bits which, in general, represent the decimal
range 0 through 9.
BCD Decimal
0000
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111
1000 8
1001
" ASCII (American Standard code for information interchange):
ASCII is the American Standard Code for Information Interchange, also known as ANSI X3.4.
It is quite elegant in the way it represents characters and it is very easy to write code to
manipulate upper/lowercase and check for valid data ranges. It is essentially a 7-bit code which
allows the 8th most significant bit (MSB) to be used for error checking, however most modern
computer systems tend to us ASsCIlvalues of 128 andabove for extended character sets.
" EBDIC code: EBCDIC (Extended Binary Coded Decimal Interchange Code) is a character
encoding set used by IBM mainframes. It uses the full 8 bits available to it, so parity checking
cannot be used on an 8 bit system. It has a wider range of control characters than ASCII.
" Gray Code: The reflected binary code is known as gray code.
2-bit 4-bit Binary
00 0000 0000
0 1 0001 0001
0011 0010
10 0010 0011
0I10 0100
3-bito111
000 0 101
0 101
0110
001 0100 0111
011 1100 1000
010 |101 I001
1010
I10 1011
101 010 I100
100 1011 I101
I001 1110
I000

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 ANALOG & DIGITAL ELECTRONICS

Very Short Type Questions

1.An example of weighted code is [WBUT 2009, 2019]
a) Excess-3 b) ASCII d) 8421
c) Hamming code
Answer: (d)

2. Which of the following is reflected code? [WBUT 2009, 2014]

a) 8421 b) Excess-3 d) ASCII
c) Gray
Answer: (c)

3. Which of the following codes is not a BCD code? [WBUT 2010]

a) Gray b) Xs-3 c) 8421 d) all of these
Answer: (a)

4. (11011), in BCD 8421 code is [WBUT 2010]

a) 00011011 b) 00100111 c) 11011001 d) 01101100
Answer: (a)
5. In which code do the successive code characters differ in only one position?
[WBUT 2010)
a) Gray b) Xs-3 c) 8421 d) Hamming code
Answer: (a)

6. 8421 is a
WBUT 2012, 2015]
a) Weighted code b) non- weighted code
c) complementary code d) none of these
Answer: (a)

7. What is Gray equivalent of the binary 1101? WBUT 2014]

a) 1101 b) 1011 c) 0111 d) none of these
Answer: (d)

8. The state 1110 is a valid state in 8-4-2-1 Binary Coded Decimal counter. State
True / False. WBUT 2022]
Answer: False

Short Answer Type Questions

1. Why gray code is called reflected code? WBUT 2016]
Answer:
In this code, a decimal number is represent in binary form in such a way such that each
grey code number diffrs from the preceding and succeeding number by a single bit
.Then it is called reflcetd code.

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Long Answer Type Questions

1.Write short note on Gray code.
Answer:
WBUT 2016, 2018]
It is anon-weighted code. In this code a decimal number is represented in Binary form in
such a way such that cach gray code number difers from the preceding and succeeding
number by a single bit. This code is a reflected code.

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 ANALOG & DIGITAL ELECTRONICS

BOOLEAN ALGEBRA
Chapter at a Glance
Boolean Algebra: Boolean algebra is an algebraic logic which deals with logic variable. This
logic variable having only two values I and 0alternatively "TRUE" or FALSE".
Boolean Theoremn and Identification:
1. Commutative law
A+B = B+A
A.B= B.A |A binary operation is commutative if changing the order of
AOB = BOA the operands does not change the end result.
AOB-BOA

2. Associative law
|A binary operation is associative if the order in which
the operations are performed does not matter as long as
A+ (B+C) = (A+B)+C
the sequence of the operands is not changed. That is.
A.(B.C) = (A.B).C rearranging the parentheses in such an expression will
A® (BOC=(AOB) C not change its value.
Note: NAND & NOR function are not associative.

3. Distributive law a (btc)= ab + ac This is called the Distributive Law.

(B+C) = A.B+A.C Distributivity is a property of binary operations that
A+(B.C) = (A+B). (A+C)generalizes the distributive law.

4. Double Negation law: A =A

5. Identity law
A.A = A
A+A= A
JA double negative occurs when two forms of negation are
used in the same value.
A+Ã=1
A. =0
6. Redundancy law
A+A.B =A
A.(A+B) =A
Venn diagram: Graphical representation of logical function is called Venn diagram.
1) A+B: First take Bcompletely.

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2) A B: First inciude Acompletely and then take the common part of Bwith universal set.

+ A.B

Representation of SOP (Sum of Product) form:

f(A. B.C)-A BC- AC - B C is known to be in sum of product form. For a n variable
function. if cach product term contains all the n variables (complemented or
uncomplemented). the function is said to be in Standard Sum of Product Form and cach such
product is known as a "mintern" (denoted by m). e.g. f(A. B. C)=ABC- B + BC.
This function is in standard SOP form and it consists of 3minterms ABC. A BCand A BC.
In a standard SOP form. for each minterm an un-complemented variable or literal is treated as
' and a complemented literal is treated as 0. It is denoted by E
Representation of PoS (Product of sum) form:
F{A, B. C) -(A -B -C).(A+C).(B -C )is known to be in product of sum form. For a n
variabie function. if each sum term contains all the n variables (complemented or un
compiemented). the function is said to be in Standard product of sum form and each such
sum is known as a "maxterm" (denoted by M).
e.g. F (A, B, C) = (A+B+C).(A +B+C).(A +B+C)
This function is in standard POS form and it consists of 3 maxterms (A+B-C). (
and (A-B+C).
In a standard POS form. for each maxterm an un-complemented variable or literal is treated as
*0 and a complemented literal istreated as 1'. It is denoted by I.
Very Short Type Questions
1. A + A'B + B' is equal to WBUT 2012, 2015]
a) A b) B' c) 1 d) 0
Answer: (c)
2. AA'B+ A'BC+ A'B'C'D+ equals. [WBUT 2017]
a) A+ B + C+ D b) A'+ B+C'+ D' c) 1 d) 0
Answer: (c)

3. (AB'(C - BD) +AB]C is WBUT 2017]

a) 4B' b) BC c) B'C d) AB
Answcr: (c)

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 ANALOG& DIGITALELECIRONICS
BC
4.Simplify A'B + A + [WBUT 2018]
a) A + BC b) A + B c) A' + BC d) None of these
Answer:(a)

Short Answer Type Questions

1. Simplify the following
form
Boolean function into [WBUT 2011]
i) Sum of product
Product of form: F(A. B, C, D) =)(0,1,2,5.8,9,10).
Answer:

CD CD CD CD
0
AB 2
0

4 7 6
AB 0
0

12 13 15 14
AB 0 0

8 11 10
1 1
AB

BD+ BC+ ÁCD

i) f(4,.B. C, D)= Sm(0. 1, 2, 5, 8,9, 10)

CD
AB 00 01 11 10

00 0

10 (0

f(4, B.C.D) -(8+C)(B+ D)(4+C+)

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Long Answer Type 9uestions

1. Find the simplified form of the Boolean expression Y, where

Y=(4'·BC + D)(AD +B'C) [WBUT 2022]
Answer:
Start
(ABC +D)(AD+ BC)
Apply: Distribution
(AD+ BC)ABC +( +BC) D
Apply: Distribution
+ +(AD+BC)D
Apply the ldempotent Law: AA = A
ABCD +ABCBC +(AD +BC)D
Apply the Complement Lavw: A4 = 0
ABCD +0+(AD +BC)D
Apply the identity Law: A+0= A
ABCD +(AD + BC) D
Apply the Distribution
ABCD + DAD + DBC
Apply the ldempotent Law: AA = A
ABCD + DA + DBC
Apply the Absorption law: | AB= A
DA+ DBC
2. a) Digital input signals A, B, C with A as the MSB and Cas the LSB are used to
realize the Boolean function F=m0 + m2 + m3 + m5+ m7, where mi denotes the
ith minterm. In addition, F has a don't care for ml.Find the simplified expression
for F. WBUT 2023]
Answer:
F=m, + m, + m, + m, t m,
m, is a don't care.

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 ANALOG k DKITALELECIRONCS

BC
A 00 01 10

F=4+C
b) Find the prime implicants in the sum of products function
(X,Y,Z) =X(2.3.4.5). [WBUT 2023]
Answer:

f(x.y.z)= Zm(2.3,4.5)
= y+ +yz + xyz + x
=(7+z)+ x(E +:)
-y+xù
So, there are only two implicants, y and xy.

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LOGIC GATES

Chapter at a Glance
De- Morgan's Theorem:
Statement l: It is state that connplement of the sum of variable is equal to the product of the
complements of the variable.
Proof: ie. A+ B=A .B
A A B A-B A+B
0
0 0 0
0

From the truth table we see that, A+ B =A.B

Statement 2: t states that the complement of the product of variable is equal to the sum of
the complements of the varialole.
Proof: i.e. A.B = A+B
A A+B
io
A B A.B A+ B
0 0 0
0

0 0 0
From the truth table we see that, A.B =A+B

Universal logic gates:By this gate allthe Boolean function can be implemented i.e. all the
digital system can be implenented. NAND and NOR gate are two universal gates.
NANDGate as a universal. logic gate:
NOT Gate using NAND Gute
A

AND gute using NAND Gite A

B Y=A.B

OR Gute using NAND Gale A

Using Demorgan's theoren Y=A.B =A+B = A+B

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 A\ALOG& DIKGITAL ELECIRONICS

ENOR Gate using N4 ND Gote

Tsng Demorgan s 2 theoren.

Y-A ABRAR

-AAB) BAB)
-AA AB- BA BB

-AB

Very Short Type guestions

1. The minimum number of NAND 9ates required to design one XOR gate is
wBuT 2007, 2010)
a) 4 b) 5 c) 6 d) 3
Answer: (a)

2. The operation which is commutative but not associative is

(WBUT 2007, 2008, 2009, 2013]
a) AND b) XOR c) NANDINOR d) NOT
Answer: (c)

3. The number of XOR gates required for conversion of 11011to its equivalent grey
code is WBUT 209, 2019]
a) 2 b) 4 c) 3 d) 5
Answer: (b)

4.The output of a logic gate is 1' when allits ip are at logic o'. The gate is either
wBUT 2009, 2019)
a) NAND or XOR gate b) NOR Or XOR gate
c) AND or XNOR gate d) NOR or XNOR gate
Answer:(d)
6. How many minimum NOR gates is required to implement NAND gata?
(wBUT 2012, 2015]
a) 3 b) 4 c) 5 d) 2
Answer: (b)
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6. Minimum number of NAND gates required to implement the XOR gate of two
variables is WBUT 2013]
a) 5 b) 7 c) 4 d) 3
Answer: (c)

7. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
WBUT 2017)
a) OR gates only b) AND gates, OR gates and NOT gates
c) OR gates and NOT gates d) none of these
Answer: (b)

8.The minimum number of NAND gates required to implement an EX-OR gate is

[WBUT 2017]
a) 2 b) 3 c) 4 d) 5
Answer: (c)
9. A
32:1 MUX can be designed using [WBUT 2018]
a) two 16:1 MUXs and one two input OR gate
b)two 16:1 MUXs and one two input AND gate
c) two 16:1 MUXs and 2 twO input OR gate
d) two 16:1 MUXs only
Answer: (a)
10. What will be the output of the logic gate in figure given below: WBUT 2023]

Answer:
IfA=0, Y=land A= 1,Y =0 Therefore Y=4.
11. In the latch circuit shown, the NAND gates have non-zero, but unequal
propagation delays. The present input condition is: P=Q="0". If the input
condition is changed simultaneously to P=Q="", what will be the outputs Xand
Y now? WBUT 2023]

D
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 ANALOG& DIGIIAL ELECTRONICS

Answer:
Let as assume <I2
xchanges state first then y changes
1" output of X(P =1, y= 0) > X, =1
Next output of Y(Q=1, X= 1) ,=0
2d output of X(P=1, y, =0) ’ 1
Hence output x=1 y=1 (if <)
and output X=0Y=l (if 2<I)

12. If the input to the digital circuit (in the figure) consisting of a cascade of 20
XOR-gates is X. What will be the output Y? [WBUT 2023]

Answer:
The output of the first XOR gate will be:

Now, the output of second XOR gate willbe:

XO=1
For 20 such XOR gates in cascade, the final output will be 1.
Short Answer Type Questions

1. Implement 2- input XOR function using minimumnumber of 2-input NAND gates.

WBUT 2009]
Answer:
EX- OR Gate using NAND Gate
A

A-B

BAB

Y= A.AB. B.AB
Using Demorgan's 2nd theorem
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Y=A. AB +B.AB
=A(A + B) + B(A + B)
=AA+ AB + BA + BB
= AB + AB
=A B

Long Answer Type Questions

1. a) Check the following digital circuit. What will be the equivalent logic gate of the
whole circuit? (WBUT 2022]

Answer:
Exclusive NOR.

b) What will be minimised output F of the circuit. WBUT 2022]

Answer:
A+ B+C

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 ANALOG &DIGII AL ELECTRONICS

KARNAUGH MAP
G Chapter at a Glance
K-map: The Karnaugh map is a tool to facilitate management of Boolean algebraic
expressions. A Karnaugh map is unique in that only one variable changes value between
squares, in other words, the rows and columns are ordered according to the principles of Gray
code.
Functions of K-map:
(i) Minimization of Boolean expression. To obtaining the minimal expression of a Booiean
function require extensive calculations. Karnaugh map reduce the complexity.
(ii) K-maps pemit the rapid identification and elimination of potential race hazards,
something that Boolean equations alone cannot do.
Twovariable k map:
B
B
A 1
A
0 AB AB A +B A+B
AB AB A+B A+B
Three variable k map: Minterms Maxterms

BC 00 01 11 10
A

ABC ABC ABC ABC

0

1 ABC ABC ABC ABC

Minterms
Four variable k map:
CD
00 01 11 10
AB

00 A BCD ABCD ABCD ABCD

01 ABCD ABCD A BCD ABCD

ABCD ABCD ABCD ABCD

10 ABCD ABCD ABCD A

BCD
Minterms

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Very Short Type Questions

[WBUT 2008]
1. The maxterm corresponding to decimal 15 is d) A' B' C'D'
a) ABCD b) A'+B'+C'+D' c) A+ B+ C+ D
Answer: (b)
2. A + A'B + A'B'C + A'B'C'D + [WBUT 2010]
a) A +B+C+.... b) A'+ B' + C' + D' +.... c) 1 d) 0
Answer: (c)

3. Acode used for labeling the cells of a K-map is [WBUT 2010]

a) 8-4-2-1 binary b) Hexadecimal c) Gray d) Octal
Answer: (a)
WBUT 2010]
4. The minimized expression for the K-map is shown below
1

1 1

a) ABCD+4CD b) ABCD +ACD+ABC

c) BCD+CD+ABC d) BC D+CD+ABC
Answer: (b)
5. What will be the minimal product-of-sums function described by the K-map
given in Fig. WBUT 2023]
AB
00 01 11 10

Answer:

AB
00 01 11 10

0 0

So answer is A

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 ANALOG &DIGITAL ELECTRONICS

Short Answer Type Questions

1. Minimize the following expression using K-map and realize the simplified
expression using NAND gates only. [WBUT 2006, 2014]
G(4, B.C. D) =E(1,2,3,5,6,1 1,12) +D(7,8,10, 14)
Answer:

G(A.B,C.D) -Z(1.2,3,5.6,|1,12)+ D(7.8,10,14)

CD
00 01 10
AB

00 1

X
01

X
10

=C+ ÂD+ AD +BC=c(D+B)+(AOD)

A D

B BD (6- D) c)
B+D
D
(A9D) (+ D)c)
(A+ B)+(B+ D)-c
A

2.Simplify the Boolean function using K-map WBUT 2007]

F(W,X, Y, Z) => m(0,4,5,6,8,9) +)d(10, 11, 12, 13, 14, I5).

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Answer:
Given Boolean function is
F(W,X.Y. Z)=>m(0,4.5,6,8,9) +>d(10,11,12,13,14,15) K - man
Ihe function is defined in terms of minterms and don't care conditions.
representation of the given function is fig. below.
YZ 01 10
00

00

01

X X
11
1 X X
10

=W +1Z+WZ +Xø =W +ø(2+X) +WZ

3. Simplify the following function using K-map. [WBUT 2007]
i) F-||m(0, 1,3, 8, 10, 15).|| d(1, 13, 14)
i) F=m(0, 4, 7, 9, 13, 15)+>d(10, 14)
Answer:
i) F=IIm(0.1.38,10,15)-[[a(1L13,14)
CD
00 01 10
AB

3
00

01 4 5 6

X
11 12 13 15 14

X
10 9 11 10

6( +B+)(B+C+D)

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 ANALOG &DIGITAL ELECTRONICS

i) F=m(0,4,7,9, 13,15)+d(10,14)
CD
AB 00

00

0 4 5 7 6
X
12 3 14

X
10
8 11 10

fn = ACD +ACD +BCD =[A+AD)-

min
BCD =C(A OD)+ BCD
4. Simplify the following expression using K-map
Y= r(0,1.,4,5,6,8,9, 12,13,14). [WBUT 2008]
Answer: AB
00 01 11 10

00 0
0

01 0 0 0
4 7 6
11
0
13 15 14

0 0

y=A(B+ D)
5.Simpli•y the following functions by means of K-map:
F= Xm(0,4, 7,9,13,15)+dE(3,5) WBUT 2008]
Answer: CD
10
00 01
AB
0
00
0 3 2

01
4 7 6
0
11 14
12 13 15
X
0
10
8 10

F=ABC+ BD +ABC
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6. Minimize the following expression using Karnaugh Map.
i) F(A,B.C.D) =[|M(0.1,3,8.10.15) - d 1.13.14)
i) F(A.B.C.D) - m0.,1.2.5,8.14) -d4,10,13)
Answer:
i) Refer to Question No. I Short Answer Type Questions.
AB
CD o o1 11 10
i)
0011
01 1
11

s =AC +BD- ACD

7. Simplify the following functions using K-map: [WBUT 201]
a) F{4, B. C. D)=)(7.9.10,11,12. 13, 14.15)
b) F(4, B, C, D) =z, (0. 2,3.6.7) - z,(8. 10. I1, 15).
Answer:
(a) F(4. B.C. D) =)(7.9. 10. I1. 12. 13. 14, 15)
CD
AB CD

AB

f= AB- AD-AC - KD

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 ANALOG& DIGITALELECTRONICS

(b) F(4, B,C, D)=(0.2. 3, 6, 7) +n,(8,10,11,15)

\CD
AB CD CD CD CD

AB 0.
AB

AB d

AB d d

f-(B+ D)(A+c)
8. Obtain the minimal POS expression of the following function and implement the
same using only NOR gates.
F(A, B, C, D) = Em(1, 4, 7, 8, 9, 11) + Ed(0,3,5) WBUT 2018]
Answer:
F(A, B, C, D) = Em(1, 4, 7, 8, 9, 11) + Zd(0,3,5)
Realize the following expression using k map and implement the simplified expression
using NOR gates only.

CD
00 01 11 10
AB
X X
00 0 3 2
1 X
01
4 6

11
12 13 15 14
10 1 1

8 10
ômin = B+AD+AC+CD

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i) F-Em(0.4,7.9.13.15)-d(10,14) CD
10
00 01
AB

3 2
0
00

5 7|
01

14
11 12 13

9
10
10

Sin =ACD+ ACD + BCD =( AD)+BCD =C(AOD)+ BCD

3. a) Determine minterm and maxterm.

What is canonical form? WBUT 2016)
b) Minimize the folowing expression using k-map
f(4, B, C, D) =Zm(3, 4, 5, 6, 7,12, 13, 14, 15).
Answer:
a) 1 Part:
functions in either complemented or not is
A sum term contains all theK variables of the Min term.
called Max term & complement of max terms called
is called minterm and each
Each individual term in a standard (canonical) sOP form maxterm. Representing the
individual term in a standard (canonical) POS form is called
introduce a very convenient
Boolean expression in terms on minterms allows us to
shorthand notation.
representation of three variables A, B and C.
Let us consider the minterm and maxterm
variables, A, Band C.
Table: Minterm and maxterm representation of three Maxterms
No. Variables Minterms
A B m M,
A.B.C= M, A+ B+C= M,
0 A.B.C= m, A+ B+C = M,
2 0 1 A.B.C =m, A+B+C= M,
3 1 A.B.C= M, A+ B+C=M,
4 A.B.C =m, A +B+C= M,
5 1 A.B.C = m, A+B+C= M,
6 1 A.B.C= m, 4+B+C =M,
7 1 A.B.C = m, B+C= M,

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2nd Part:
CannonicalForm:
In Booleah algebra. any Boolean function can be expressed in acanonical form using
the dual concepts of minterms and maxterms. Minternsare called products becausce they
are the logical AND of a set of variables. and maxterms arc called sums because they are
thelogical OR of aset of variables.
b) CD
AB 00 01 10 10

00
0

01
5 6|

1
12 13

10
8 9 11 10

f(4, B,C, D) =m(3,4, 5,6,7, 12, 13, 14,15) =B+ACD

4. Write short note on SOP and POS canonical forms of binary subtraction.
[WBUT 2010]
Answer:
Standard Sum of Product Form
f(A, B, C)=A B C+ AC + B Cis known to be in sum of product form.
For a n variable function, if each product term contains all the n variables
(complemnented or uncomplemented), the function is said to be in Standard Sum
of Product Form and each such product is known as a "minterm" (denoted by
m), e.g. f(A, B, C) -ABC +t A BC+ABC
This function is in standard SOP form and it consists of 3minterms ABC. ABC
and A BC
In a standard SOP form. for each minterm an un-complemented variable or literal
is treated as 1' and a complemented literal is treated as 0°.

Thus for function

f(A,B,C) = ABC+ A BC + ABC we have the values as:
ABC = 1ll=m, (7. decimal equivalent of l|1))
ABC= 010 = m
ABC =001 = m

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The above equation can be written as

f(A.B.C)= m, + mt m,
or, f(A.B.C)= m(1.2. 7).
Standard Product of Sum Fornm
F(A, B, C) - (A +B +C)(A+C).( B+C )is known to be in product of Sum
form.
For a n variable function , if each sum term contains ll the n variables
(complemented or un-complemented ), the function is said to be in Standart
product of sumform and each suchsum is known as a "maxterm" (denoted by
M). e.g. F(A,B, C) =(A+B+C).(A+B+C).(A +B +C).
This function is in standard POS form and it consists of 3 maxterms
(A+B+C),(A+ B+C) and (A+ B+C).
In a standard POS form, for each maxterm an un-complemented variable or
literal is treated as 0 and acomplemented literal is treated as 1'.
Thus for function
F(A,B,C) =(A+B+C).(A +B+C ).(A+B+C) we have the values as:
A +B+C= 000 = Mo(0, decimal equivalent of 000)
A+B+C= 101 = Ms
A+B+C= 110=M6
The above equation can be written as
F (A, B, C) = Mo. Ms. M6
or, F(A, B, C)=|M(0, 5,6).
5. Find the out expression for the Karnaugh Map shown below: WBUT 2023]
CD
AB 00 01 11 10

00

01 0 1

11 0 1

10 0 0

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Answer:
CD
AB 00 01 1 10

00 0
01

11 1

10 0

It can be grouped as follows:

CD
AB 00 01 11 10

00

01 0 1

11 1 |

10 0 L BD

ABC
Outputexpression in the form of SOP (sum of products) =BD +ABC
6. Find the output expression F for the following Karnaugh Map and realise it with
logic gates. WBUT 2023]
AB
00 01 11 10
1 4
1 1 1
Answer:
F=A'C'+ BC

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QUINE MC - CLUSKEY'S
Chapter at a Glance
The Quine-McCluskey method is an exact algorithm which finds a minimum-cost of sum..6
products implementation of a Boolean function.
Determination of prime implicit:
The starting of the tabulation method is the list of minterms that specify the function.
The first operation is to find the prime implicit by using a matching process. This process
Compares each minterm with all other minterms. If two minterms d1ffer onlv one
variable, the variable is removed and aterm with one less literal is found.
This process is repeated for every minterm until exhaustiye search is completed.
The matching process cycle is repeated for those new mintèrms just found.
Third and further cycles are continued until asingle pass through a cycle yields no further
elimination of literals.
The remaining terms and all those terms that did not match during the process comprise
the prime implicit.
Steps for solving Method:
Step 1: Group the binary representation of the minterms according to the number of l's
contained.
Step 2: Any two minterms, which differ by only one bit, can be combined, and unmatched
variable removed. One minterm should be compared with other mintems in next section
only if two minterms differ by more than one bit cannot match. If any two numbers are the
same with every bit position except one, a check (v) is placed to the right of both the
minterms to show they have been used. The minterms eliminated during the matching is
denoted by a (-) in its position. For example, m0(0000) comprises with (0010) to form the
resultant (00-0).
Step 3: Repeat step 2. Compare one minterms to other. Section it with others minterms. In
next section which having (-) in same partition.
Step 4: Repeat the comparing process until the proper matching is encountered.
Step 5: The unchecked terms in the table form the prime implicit.

Long Answer Type guestions

1. Simply the following function by means of tabulation method.
F=)m (0, 1, 4, 7, 9, 11, 13, 15)+ )d(3,5). [WBUT 2007, 2010]
Answer

F= Xm(0.1, 7,9, 11. 13.15)+Xd(3.5)

It is clear from the logic function that the highest minterms is 15. So. the function is a
four variable function. This logic function has two don't care entries. To drive the logic
expression the procedure is given below:

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Step-I
Initially. the table is created representing all minterms and variables of the function. All
the minterms are arranged increasing order considering numbers of l's in binary
representation of minterms as given in Table L.
Tablel
No of
I's Group Minterms Variables

A B D

1
4
0 0
0
0
3 0
11
13 0
4 IV 15 1 1

Step-2
Table 2 shows the all -possible two minterms combinations. The results of combinations
of two minterims consists of the original binary representation with different bit placed by
- as depicted in the same table. The minterms. which are combined with other
minterns, are tick marked in the Table 2.
Table 2 Combinations of two minterms
Combination Variables
A B C
0.1
0,4 0
1.3
1,5 0
1.9 1
3,11
0
4,5
3,7
5,7 0
9.13
5,13
13.15
9.11
0
|1.15
7,15

Step -3 possibility of
Table 3 gives possible combinations of four minterms. There is no
combinations of eight minterms.

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Table 3 Combinations of two minterms

Combination Binary Code
A B D
0, 1, 4, 5 0 0
1, 5, 3. 7 0 0
I, 3,9. 11
3, 7, 11, 1S
1,5,9. 13 0

Step-4
Table 4 isconstructed to find out the essential implicants.
Table 4 Table of prime implicants
Prime
Variables
Implicants
4 11 13 15
0, 1,4, 5*
1, 5, 3, 7
1, 3,9, 11
3, 7, 11, 15*
1, 5,9, 13*
ns
The procedure of selection prime minterms is to cover maximum number of minte
which cover
There are three prime implicants (0, 1, 4, 5); (3, 7, 11, 15)and (1, 5, 9, 13) proper
all compulsory minterms (0, 1, 4, 7, 9, 11, 13, 15). Then put star marks at the
function is
places of the three prime implicants. Hence the minimal form the logic
F=AC+CD+CD

2. Simplify the following function by tabular method: [WBUT 2008]

F= X0,1,3, 5, 7,9, 13, 15) + d E(4,6).
Answer:
is 15. So, the function is a
It is clear from the logic function that the highest minterms entries.
four variable function. This logic function has two don't care To derive the logic
expression the procedure is given below:

Step-1 function. All

Initially, the table is created representing all minterms and variables of the
of 1's in binary
the minterms are arranged increasing order considering numbers
representation of minterms as given in Table 1.

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Table 1
No of
1's Group Minterms Variables
A D
0
e-= 0 0
2 3 0
0
6
9
3 7
13
4 IV 15 1

Step-2
Table 2 shows the all-possible two minterms combinations. The results of combinations
of two minterms consists of the original binary representation with different bit placed by
"' as depicted in the same table. The minterms, which are combined with other
minterms, are tick marked in the Table 2.
Table 2 Combination of two minteris
Combination s
Binary Code
A B D
0, 1 0
0, 4
1,3
1.5
1,9 1
1
4, 5
5, 13
3,7 1
5,7
9, 13
13, 15
7, 6
7, 15 1

Step-3
Table 3 gives possible combinations of four minterms. There is no possibility of
combinations of cight minterms.

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Table 3 Combinations of two minterms

Combination Binary Code
A B D
0 0
0. 1.4. 5
1,5. 3, 7
-

4. 5,6. 7
5. 7. 13, 15
1. 5,9, 13

Step-4
Table 4 is constructed to find out the essential implicants.
Table 4 Table of prime implicants
Prime Implicants Minterms
1 3 13 15

0, 1,4, 5*
1,5, 3, 7
4, 5. 6, 7
5.7, 13, 1s*
1, 5,9, 13*
The procedure of selection prime minterms is to cover maximums. There are three prime
implicants (0, 1, 3, 5); (1, 3, 5, 7); (5, 7, 13, 15) and (1, 5, 9, 13) which cover all
compulsory mintemns (0, 1, 3, 5,7,9, 13, 15). Then put star marks at the proper places of
the three prime implicants. Hence the minimal form of the logic function is
F= 1C+ÃD+ BD +CD.
3. Simplify the Boolean function using Quine McClusky method. [WBUT 2015]
F-X(1.3,4. 5,9,10, 1) +>Z(6. 8)
Answer:

F=E(0.3,4, 5, 9, 10, 11) +>Z(6.8) 8

Primary representation of minternm

Variable
Minterm A B D
0 0 1
1
4 0
0 0
6 0 0
-

8 0
9
0

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COMBINATIONAL CIRCUITS
Chapter at a Glance
A circuit in which output depends up on the present state of the inputs Is called
combinational circuit.
Adder: Digital system required adder circuits for addition of two binary digits and the adder
Circuit gives out two outputs. Sum and Carry. There are two tvpes of adder.(i) Half adder and
(ii) Full adder.
Half adder: A combinational circuit performs the addition of two Boolean variables.
Generate the results SUM and CARRY according to the truth table shown. SUM S= AB
+ AB' CARRY C= AB. We can use Ex-OR gate to implement the circuit for SUM, and using
a AND gate to implement the circuit for CARRY.

A Half
Adder output
input
B

Full adder: It is combinational circuit which adds three binary digits. It consist three input
and two output bits. Out of three input variable tWo are denoted by A & B represent two
significant bits. Third input Ci represents the carry from the previous lower significant
position.
Subtractor: Subractor circuits take two binary numbers as input and subtract one binary
number input with other binary number input. Similar to adders it gives out two output,
difference and borrow (Carry in the case of Adder. There are two types of subtractor. (i) Half
subtractor and (i) Full subtractor.
half subtractor
Half subtractor: Similar to binary half adder circuit we can build binary
circuit. In this circuit two input x & y produced two output D (Difference) and B (Borrow).
subtraction
Full subtractor: A full subtractor is a combinational circuit that performs by a lower
have been borrowed
between two binary digits, tabing into account that a l may
significant stage. This circuit has three inputs and two outputs.
performed by a
Encoder: An encoder performs a function which is inverse to the function
line. The output line
decoder. An encoder has 2" numbers of input & n numbers of output that only one
circuit, it is assumed
generate the binary code for 2" input variables. In encoder active input signal into a
convert an
input line can be equal to l at any time. An encoder
coded output signal information of n input
Decoder: Decoder is a combinational circuit which convert binary
decoded input information has
lines to the maximum of 2" unique output lines. If the n bit
have less than 2 output.
unused or don't care combination , the decoder output will number of
transmits multiple
Multiplexer: Multiplexer is acombinational circuit which
information signal over asingle signal line.
one output signal.
Amultiplexer circuit having multiple numbers of input signals &

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Demultiplexer: The demultiplexer performs the reverse operation of a multiplexer. It acese

a signal input and distributes it over several outputs. Demultiplexer is a combinational cirei
which transmit asingle line signal over multiple line information signals.
Comparator: Adigital comparator circuit is a combinational circuit which compare tu
input digital signal and gives the output as per result. e.g. Let A and B are two input signale
. the circuit compare with Aand B
If A> B output =]
A =B output =l
A<B output =1 Otherwise,output =0.
Parity: Adigital word that is transmitted along with an additional bit is known as the Parity
bit. The form of all the I's in the data and parity bit is even or odd. If the form of the l's is
even, it is known as 'even parity'. If the form is odd it is known as odd parity.
Parity generator / Parity checker: In a digital system, it is often required to reduce the
probability of error in the transmission of digital data by using concept of Parity
generator/Parity checker.
A o
BO Parity generator /
Input P.
Co checker
DO
P, o

Block diagram of 4-bit parity checker/generator

Use: Parity Generator/Parity checker is used to reduce the probability of error in the
transmission of digital data.
Odd parity bit Generator:
State diagram and state table of an odd parity bit generator are shown below.
PS NS
x=1
B,0 C,0
E,0
Coo D,0
D F,0 G,0
D G,0 E,0
F A,1
0/0
A,0
State
State Diagram
Very Short Type guestions
1. Adecoder with enable i/p can used as [WBUT 2007, 2008]
a) Encoder b) Parity generator c) Multiplexer d) DeMultiplexer
Answer: (d)

2. One-bit even parity error detection code fails to detect WBUT 2007]
a) any even number of error b) any odd number of error
c) both (a) and (b) d)none of these
Answer:(d)
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3. The value of F is
WBUT 2008]

a) 0 b) 1 c) A d) A'
Answer: (b)
4. Calculator Keyboard is an example of [WBUT 2008]
a) Decoder b) Multiplexer c) Encoder d) DeMultiplexer
Answer: (c)
5. The minimum number of NAND gates required to design one full Adder circuit is
WBUT 2009]
a) 5 b)9 c) 6 d) 10
Answer: (b)
6. A
decoder with enable input can be used as WBUT 2009]
a) Encoder b) Parity Generator c) NAND d) Demultiplexer
Answer: (d)
7. The number of min. terms of 4 variables is WBUT 2013]
a) 16 b) 8 c) 4 d) 2
Answer: (b)

8. Which one is used for parallel to serial conversion? WBUT 2016]

a) MUX b) DEMUX c) ENCODER d) DECODER
Answer: (a)

9. Parity generator is used for WBUT 2017]

a) error detection b) amplitude detection
c) noise detection d) none of these
Answer: (d)
10. What is the minimum number of NAND gates required to design a Full adder
circuit? WBUT 2022]
Answer:9

11. The output Y of the logic circuit given below is [WBUT 2022]
X

Answer: 1

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to reali,
12. What will be the minimum number of 2to 1 multiplexers required
to 1 multiplexer? WBUT 20231
Answer:
We need to implement 4 to 1Mux using 2to IMux.
4 2
We need-=2infirst leveland =| in second level.
2
Hence, we need three 2 to IMultiplexers to implement 4 to l Mux.
Short Answer Type Questions

1. Implement the following using [WBUT 2011]

8:1 MUX, F(A, B,C, D) =(0,2,4,6).
Answer:
1=Logic high
0= Logic low

4:1 MUX
F

A B
B

4:1 MX

2. What is Multiplexer? Why is it called data selector'? Write the important

characteristics of digital IC. [WBUT 2012, 2015]
Answer:
1"& 2nd Part:
Multiplexer is a combinational circuit which transmits multiple number of infomation
signal over a single signal line.
Amultiplexer circuit having multiple numbers of input signals &one output signal.

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ANALOG & DIGITAL

Block diagram of a multiplexer

input
signal
n:1
o output
Multiplexer

Enable

S: S,

Select input
.A digital multiplexer is a combinational circuit that selects binary information from one
of the many input lines and directs it to a single output line.
Selection of a particular input signal is controlled by a set of selection line. If there are
mselect input then they can have 2M combination. Thus they can identify 2m data input
lines.
Usually multiplexer has one Enable' input, if enable is low or zero then the output is n0t
connected to any input and output will remain zero irrespective of the select input and the
data input.
Multiplexer is also known as data selector or 'MUX.
control line

-o output

Control signal
Necessity
In alarge number of electronic systems digital data is available on more than one lines
and has to be routed through asingle line at final stage. Thus, the circuitry which select
one of several signals at the transmitting end is referred to us a multiplexer just like a
selected one way switch. This is also improve of reliability of the system by reducing the
number of external wired connections.

Important characteristics of digital IC

i)speed of operation
i) power dissipation
iii) figure of merit
iv) fan out
V) current & voltage parameters
vi)noise immunity
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vii) operating temperature

viii) power supply range requirements
ix) flexibilities available.

Implement the function F(4, C)

B, = > m(1,3,5,6) using decoder. What is the
3. and sequential circuit?
difference between combinational circuit WBUT 2012, 2013, 20151
Answer:
Given function: F(4,B,c) = m(1,3, 5,6)
K-Map: BC BC BC BC BC
01 11 10
A 00

A =0
3
A=1 1
4 5 6

..F=AC+BC+ ABC
=C(4+B)+ ABC =C(AB)+ ABC
=ABC+ ABC = ABOC
Implementation using decoder:
A A B BC C

A circuit in which output depends up on the present state of the inputs is called
combinational circuit.
A logic circuit whose output depends not only on the present input but also on the history
of the inputs is called sequential circuit.
4.a) lmplement the following function using 4:1 [WBUT 2013]
multiplexer:
F(4.B,C)=> m(1.3,5,6) .
b) Write the application of
multiplexer.
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Answer:
a) As 4:1 multiplexer is used to implement Boolean function F(4. B. C)
=> m(1,.3,5,6)
two select inputs can be used for selections 4 input
address lines.
Truth table of 4:1 MUX:
Inputs Outputs
X
F

---
0

A
Y F(A.B.C)

b) Itoperates as controlled switch with n inputs at one bit data output. It selects one of
the inputs according to binary signals applied on select pins of combinational circuit
passes the information to output.
5. Design a5:32 decoder using 2:4 and 3:8 decoders. WBUT 2017]
Answer:
Let us consider 5 input lines are ABCDE here A is the MSB & E is the LSB.
1 we have to use 2:4 decoder whose inputs are A &B and output D,D, D,D; are enable
signals of4 3x8 decoder respectively. CDE are the 3 input line of the 3x8 decoder, each
of the decoder produces &output lines.
are the 3 input line of the 3x8 decoder, each of the decoder produces &output lines.

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Y
38

D Y,
3 8
D

D
A(M SB D
24 D
D
D
38
D Y
E

Y::
D
3:8
E D Y:

ELSBL

technology. [WBUT 2018]

using COMS
6. Design NAND and NOR logic gate
Answer:
2input NAND Gate: Truth Table
VA VB VoUT
LOW HIGH
LOW
HIGH HÊGH
LOW
LOW HIGH
HIGH
HIGH HIGH LOW

Ved
Circuit

PMOSI

PMOS2

Vout

NMOSI

NMOS2

Grnd.

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The abov drawn circuit is a 2 input CMOS Nand gate.

2input NOR Gate:
Truth Table
Vi V Vor
LOW LOW HIGH
LOW HIGI| LOW
HIGH LOW LOW
HIGH HIGH LOW
Circuit V

PMOSI

VA

PMOS2
VB Voul

NMOS2
NMOSI

Grnd

7. Explain the working principle of 4:1 MUX with a truth table. Realize it using
NAND gates only. [WBUT 2019]
Answer: A B
A B

N
Output

N, -

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I,. I,. I,.1, are inputs of MUX.

A, B are control input

Output is., I,4B-IAB-1.AB-1.AB = LAB I,AB - 1I,AB +IAB which is the outbuut
MUX.

Truth Table
|Selact Inputs Enable Inputs Outputs
Input
Si So E
X 0
X X X
0 X X X
X X
X 0
0 X 0 X
0 X 1 X X
0
X X X
1 0
X 1 X
0
X 0
0 X X
X X 1
X

1:4 DEMUX with truth table. Realize it

using
8. Explain the working principle of
WBUT 2019]
basic gates.
Answer: same over one of
The process ofgetting information from one input and transmitting the
demultiplexer is a combinational logic circuit
many outputs is called demultiplexing. Ainput and transmits the same information over
that receives the information on asingle
combinations of the select lines control the
one of 2n possible output lines. The bit at given instant. The below
selection of specific output line to be connected to the input switching of the input to
the
figure illustrates the basic idea of demultiplexer, in whichDemultiplexers
instant. are also called
any one of the four outputs is possible at a given which is received at the input to
as data distributors, since they transmit the same data the multiplexer
diferent destinations. Thus, a demultiplexer is a l-to-N device where asdemultiplexer or
of a
is an N-to-I device. The figure below shows the block diagram
simply a DEMUX.
that consists of
The below figure shows the block diagram of a -to-4 demultiplexer YO to Y3.lt is
single input D, three select inputs S2, Sl and SO and eight outputs from input
also called as 1-to-4 demultiplexer due to three select input lines. It distributes one
line to one of 4output lines depending on the combination of select inputs.

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Outputs

Input |:4
D,
DEMUX

Y.

S; Si S.
Data Input Select Inputs Outputs
S Si S Y; Y, Y Yo
(0 0 0 0 (0 D
1 0 D
0 1 D
0 D
0
1
1
D 1 0 (

Truth table shows the equation:

YO= DS2 SI S0
Yl= DS2 S1 SO
Y2 = D S2 SISO
Y3= D S2 S1S0

9. Design a 5 to 32 decoder using 3to 8 decoder and 2 to 4 decoder. WBUT 20221

Answer:
3-t0-8 DO
DEC
D7

D&
3-to-8
DEC
DI5
I3 2-to-4
DEC DI6
3-t0-8
DEC
D23

3-t0-8 D24
DEC
D3I

5-to-32 line decoder

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implement the sum S of a
theused
adder with input bits P and Q and be to 1-bi
carry input Cin Find the combinations
10. Figure shows a 4to 1 MUX to S.
realizethe sum
inputs to ,,,,1, and 1, of the MUX
which will [WBUT 202
4:1
MUX

Answer:
For 4:1 mux

4x1 F
MUX

F=1,AB +,AB+1,AB+1,AB
A C

Full adder

S=AOBC

ABC
Where sum of fulladder is =

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Truth table of full adder

S(A) S(B) Carry(C,) Sum
t+,= C

1
0

11. Design a Full subtractor (X, Yand Borrow) with 4 :1 MUX. WBUT 2023]
Answer:

A
-D= A BeC= Em(1. 2.4.7)
FS
C -B, = AB +BC +CA =Sm(1. 2.3.7)

A0 3
Function Table for Difference, D
A (4) 5 6
AA A A

Function Table for Borrow, Bo

A 4 5

0A A 1
It requires two 4:1 MUX. So we will have to make 4:1 tree from avariable 2:1 MUX
0
A-
2:1
-
2:1 D= ABOC

3 21
A
Logic
2:1
A B

2:1 B, = AB + BC+ CA

A
3 2:1
Logic 1

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Long Answer Type Questions

1. Implement the following function using all 4:1 multiplexers.
F=m(0,2,3,6,8,9. 12,14) WBUT 2007, 2010, 2018]
Answer:
To implement F m(0., 2, 3, 6, 8,9, 12, 14), one 16:1 multiplexer is required. As the
circuit willbe designed by 4:1 MUX, 16:Imultiplexer can be implemented using five 4:1
MUX as shown in Fig. Consequently to implement F=m(0,.2, 3. 6, 8. 9. 12, 14). input
signals ,,I,,I,,l,,,1,, I,, and I,, are connected with 5V and other input signals
I;,1,,1,os4sdg, and I, are grounded.

4:1 MUX

S So

4:1 MUX

4:1 MUX Output

F
C D
S: S:

4:1 MUX
A
S S

4:1 MUX

S; S

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 ANALOG& DIGITALELECTRONICS
2. Implement a full-adder circuit
and one additional logic gate if using 3to 8 decoder with all WBUT
a active-low outputs
Answer:
required. 2007, 2019]

S(x. y. z) =m(1,2,4.7) =sum

C(x. y. z) =m(3,5.6.7) =carry
Since there are 3 inputs and a total of 8 minterms we need a 3 to 8
decoder. Ihe
implementation is shown in figure below.
S
N
3:8
N decoder
C

3. Implement a comparator circuit using decoder and other suitable gates to

compare two 2-bit binary numbers. Assume that the outputs of the decoder are
allactive low type. [WBUT 2008]
Answer:
Design of a2-bit Comparator using Decoder:
Let A(44) &B(BE,) are two-bit numbers and the result whether A>B or A<B is
indicated by the three output.
Inputs Outputs
A B B A>B A<B
0 0
0

0
0

0 0

1 0 1

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Ihe output expressions are obtained below
For A>B B,Bo B, Bo
BË Bo B;B
A|Ao TEIE

AjAo|
AjAo1
4,B,B, + 4B,+4,4,8,
For A<B
BËBo BB, BBo B,Bo

A|Ao 1

A;Ao

A,Ao

AB, +44,B, +A,B,B,

A A B B.

1 A>B

A<B

Logic diagram of 2-bit comparator using decoder

4. Prove that a Multiplexer is auniversally complete logic module. [WBUT 2008]

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 ANALOG & DIGITAL ELECTRONICS

Answer:
Multiplexer as inverter
Vec
S lo Y
0 d 1
2.1
1 d 0 0
MUX

Multiplexer as OR gate
A B Y
0
0 1
4:1
1 MUX
1 1

Si So

S S
d 0
1 d
1 0 d d
1 1 d d d 1

Multiplexer as AND gate Vec

A Y
0 0
4:1 Y

1 MUX

S Y
d d d 0
d 0 d 0
0 d d 0
d d d

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Multiplexer
A
as NOR gate Vc
B
0

4:1
0 MUX
1 0

Y
S Lo
d 0

1 d 0
d 0
1 d

Multiplexer as NAND gate

Y Vcc
A B
0 1
1 1 Y
4:1
1 0 1 MUX
1 1

Multiplexer as EXORgate
Vee
B
0
0 1 1
4:1 Y
1 1 MUX
1 1

Multiplexer as EXNOR gate Vc

A B Y
0
4:1
1
MUX

5. Design a Full-subtractor using two 4-to-1 MUXs and other suitable gates.
WBUT 2008]

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 ANALOG& DIGITAL ELECTRONICS
Answer:
Truth Table of Full-subtractor
A B b(c) d
0

1 0
0 0

Vcc

4:1
MUX Y

A EN

S S
B Y(d)

4:1
MUX Y

EN

6. What will happen to the following circuit if the select(s) of the 2-to-1 MUX is
driven by a clock, the output Yof the MUX is connected to the l, data input Iine
and l, data input line is connected to Xwhere X may be 0or 1. [WBUT 2008]

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Answer: Y
S I(Y) I(X)
o(0)
o(0)
0(0) d
d I(1)
[WBUT 2009]
7. Design 4x16 decoder using 3x8 decoders.
D
Answer:
R 3:8 Decoder

3:8 Decoder

Enable DËs

[WBUT 2013]
using a decoder.
8. a) Design a full-adder
Answer:

S(x, y, z) =)m(1,2,4,7) =sum

C(x, y, z)=) m(3,5,6,7) = carry minterms we need a 3 to 8 decoder.
The
inputs and a total of 8
Since there are 3
implementation is shown in figure below.

3:8
Z
decoer 4

WBUT 2013]
b) Design a logical circuit that will detect illegal BCD code.
Answer:
Design a logic circuit that will detect illegal BCD code

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 ANALOG & DIGITAL ELECTRONICS

A B D Y
0
0 1
0 0
1
0 0
0

0
1
1 1 0
1 1

CD
AB 00 01 11 10
00
01
11
10

=AB + AC= A(B + C)

OR

(AND)
A

Y=ABCD+ABCD+ABCD +ABCD + ABCD +ABCD

C

c) lmplement half-subtractor using MUX. WBUT 2013]

Answer:
Ahalf subtractor is used to subtract two binary digits the minuend (A) and subtraend (B).
Afier subtration of two binary digits Aand B. The difference D= (A-B) and Borrow Bou
generates. The borrow signal may be transferred to the next stage of subtraction.

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Block diagram half subtractor is shown below.

+ Difference (D)
Half
Subtraction
Borroy out (B.)

is shown below.
Logic gates implementation of the above
A

D= 40B= AB+ AB

Bout = AB

Implementation of the above with the help of MUX isshown below

A 5 6 7

A A 1

9. a) Design an 8to 3 line encoder. WBUT 2019]

b) Design a2 to 4 line decoder.
Answer:
a) Refer to Question No. 10(e) ofLong Answer Type Questions.
b) Truth table of 2:4 line decoder
A B Out 1 Out 2 Out 3 Out 4
0 1
0 0
0

out l= AB, out 2 = AB,

out 3=AB. out 4=AB

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-
OUT !

OUT 2
BO

OUT3

OUT 4

Fig: Realization of four output decoder using gates

10. In the given MUX the output is F= AXOR B. What
will be the inputs
I,.Ii,.1;? WBUT 2022]
1,
4x1
MUX

Answer:
Given select lines, Si and So are A and B
To obtain the given expression:
F=40 B= AB +AB
Output Y =I,4-B +1,A-B+ 1,4- B+ 1,A·B
To get the required output of XOR gate, the required input I;ljlo must be 0110.
11. To realize the given truth table from the circuit shown in the figure, find the
input to J in terms of A and B. WBUT 2022]

Combinational
logic circuit
B K

clk

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B
0
1
1

Answer:
Characteristic Table of J-K flip flop
J K Qn Qn+1
0
0
0 0 0

0
1

Excitation Table of JK we make with help of Characteristic Table

Qn Qn+1 J K
0 0
1
0

fill On+1
As function Table mentioned in the question above with the help of that we
And with the help of Excitation table of JK we will JK values
A B On Qn+1 J K
0 0
1 0 1

1 # 0
olol
1 0
#
1 0 0

Minterm of J in form of AB = AB+A'B

Minterm of K in form of AB= A'B'+AB

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Boolean expression.
TITTTI
12. The output F of decoder can be realised with best logic gates. Find out the
[WBUT 2022]
y

(BASE)
B 3 to 8
Decoder

Answer:
F= A(B+C)+ BC
13. Find the out F in terms of A and B. [WBUT 2023]

Answer:
F= AB+ A'B'

14. a) A digital circuit which compares two numbers AsAzAA, (A) B,B,B, B, (B) is
shown in figure. Find the pair A, Btoget output Y=0. WBÜT 2023]
B: A. B A; B A, B., A,

Answer:
AsA,A,A, = 1010 BB,B,B, = 0011

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b) Consider the multiplexer based logic circuit shown in the

Boolean functions are realized by the circuit. figure. Find
W (0

MUX 0
WBUT 20
MUX

S
Answer: S:
F,=S,w+S,T
=S,
Now, the required function f will be:
=F=S,F, +S,
F=S,
F=S, S, ® w
15. a) Find the output Z in terms of Xand Y.
[WBUT 20231
YO

+5VO 4 x I MUX

XO
S So

Answer:
X+Y

b) ABoolean function F(4, B, C,D) =n(1, 5, 12. 15) is to be implemented using an

8x1 multiplexer (A is MSB). The inputs ABC are connected to the select inputs
S,S,S, of the multiplexer respectively. WBUT 2023]

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4 f(A. B.C. D)

6
7
S: S S

A BC

Find the correct inputs to pins 0, 1, 2, 3, 4, 5, 6, 7 in

Answer:
order. WBUT 2023]
Given maxterm
F(4. B.C, D) =n(1.5.12.15)
The minterms of the given max terms will be
f(A, B,C,D) =Xm(0.2.3,4,6.7,8,9.10,11.13, 14)
I, I,
D(0) 2 4 6 8 10 12 14

D() 1 5 7 11 13 15
D D 1 1 D D

Therefore. the correct inputs to pins 0, 1, 2, 3, 4, 5. 6, 7 in order is D',1, D', 1, 1, 1, D, D'

b) A 3 line to 8 line decoder, with active low outputs, is used to implement a 3

variable Boolean function as shown in figure:
Find the simplified form of Boolean function F(4, B, C) implemented in 'Product
of Sum' form. WBUT 2023]
3x 8 Decoder

Y A
F
X A; 4

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Answer:
+T+Z}{(Y+2)
The correct option is (X +z)(X
Let us consider active highinput
yz
01 10
X 00
0

+Z){+I+Z)
F=X(1.3.5. 6) =TIM(0.2.4.7) =(T +z)(X
on the following:
16.Write short notes decoder/driver WBUT 2006, 2010]
a) BCD-to-7 segment [WBUT 2008, 2010, 2015,2018]
and checker.
b) Even parity generator WBUT 2009]
c) Comparator [WBUT 2011]
and Checker
d) Odd Parity Generator [WBUT 2012, 2014]
e) 8:3 encoder [WBUT 2014]
f) Parity generator WBUT 2016]
g) Encoder WBUT 2017]
h) Decimal to BCD encoder
Answer:
decoder/driver:
a) BCD-to-7 segment is
In this decoder, the outputs are used to
drive seven-segment display. The 7 segments
are
DMM, calculators use BCD numbers, which
one of the commonly used displays. The of combinational logic circuit. The
converted into seven segment codes with the helpbelow:
in figure
seven segments a. b, c, d, e, f, g are shown

B889
b
b

8888
a

5 7
4

h h

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 ANALOG &DIGITAL ELECTRONCS

The truth table for BCDto 7 segment decoder is given the following table:
Decimal No. Inputs Seven segments
A B C D a h d f

0 o - o - o1- o0 (0
0 (0 1 1
0 0 (
4 () 1 0
loll 0 0 1 (0 1
0 1 ()

ooa (0 1 1
1 0
The K-maps for these seven segments a. b, c, d, e. fand g as a function of A, B. C and
Dare shown in the following figure.
These maps are reduced as follows:
For segment a
CD 00 01 11
AB
00 0

01

11 X X

1
10

For segent b
Y,= ABD + BD +A+C CD
po 01 11 10
AB
00 1

1 0
01

X X
11 X

X
10

Y,= B + CD + CD
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For segnent c
CD
00 01
AB
00 0

01 1 1

11 X

10

Y,= C+ B+D
For segment d
CD
01 10
AB
1
00

0 0
01

X X
11 X

1 X X
10

Y= CDB+A+CDB +BC +CD

CD For segment e
00 01 10
AB
00

01

X X xX
11

0 X
10

Y, = BD+CD
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 ANALOG & DIGITAL ELECTRONICS

CD For segmentf
AB 00 01
10
00 0

01

11 X

10 X X

Y,= CD+ BC+ BD+ A

CD For segment g
AB 00 01 10
00 0 1

01

11 X X

10 Y

Y, = BC +A+BC +CD

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We can built logic circuit for BCD toseven segment decoder using AND-OR circuit,.
D
B|D

Ya

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 ANALOG& DIGIIAL ELECTRONICS

D
D

b) Even parity generator and checker:

An even paritygenerator willproduce a logic Iat its output if the dataword contains an
oddnumber of ones. If the data word contains an even number of ones then the output of
the parity generator will be low. By concatenating the Parity bit to the dataword. a vword
will be formed which always has an even number of ones i.e. has even parity.

Parity Checker
It checks the bits in the message along with the parity bit for even parity checker there
should be even number of Iand for odd parity checker there should be odd number of I
In the received bits. Otherwise error will occur.

Iruth Table for 4 bit even parity checker:

Received bits Check
X P
0

0 0

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Received bits Check

P
0

1
0
0 0

0
0
1
1 0
P
WX

00 01 11 10
00 1

11 0 1

10 0

.. C=wxyDP

Circuit Diagram

D
P
Fig: 4 bit even parity checker

c) Design of a 2-bit Comparator using Decoder:

Let A (44,) & B(B, B,) are two-bit numbers and the result whether A>B or A<B is
indicated by the three output.

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 ANALOG &DIGITAL ELECTRONICS
Inputs Outputs
A, A. B Bo A>B A<B
0 0 0
0 0 0
0
0
0 1 0
0 0
0

0
0
1 0
0 0
0
1

The output expressions are obtained below

For A>B
B| Bo B|Bo B,B B, Bo
A|Ao

AAo1
A¡Ag 1

AjAo| 1

A,B,B, +4B, +44,B,

For A<B A A B B

B, Bo BBo B,Bo B,Bo

AjAo 1 A>B

AAo
A¡Ay
A<B
A|Ao

4B +44,B, +4,B,B,
Logic diagram of 2-bit comparator using decoder

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d) Odd Parity Gencrator and Checker:

State diapram andstate table of an odd Parity bit pernerator are shown below.
NS
PS

B. 0
D.0 E.0
( E.0 D.0
D F.0 G.0
G.0 F.0
A. I A. I
G A.0 A. 0
Stute table

1/0

State

Parity checker:
Refer to Question No. 9.(b) of LongAnswer Type Questions.
e) 8:3 Encoder:
figure.
The block diagram of cight input and thrce output encoder is given in followingencoder
Table I shows the truth table of an 8 linc to 3 linc decoder. The outputs of the
can be expressed by a Boolean expression as given below:
A=D, - D, - D, D
B-D. D, -D, - D,
C-D - D, - D, - D,
The limitation of the above decoder is that if all inputs D, to D, are 0, all outputs will be
equal to 0. Therefore. onc additional output is sometimes incorporated to point out this
state. Another limitation is that only one of the encoder's inputs must be asserted at a
time, otherwise the output willbe illogical.

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D
’ A
D. > 8Iine to
3 line
Inputs D encoder ’B
Outputs
D.

D.

D,

D;

Block diagram of 8 line to 3 line encoder

Truth table for 8 lines to 3 line decoder
Inputs Outputs
D, D Ds D. D; D, D Do A B
0

0 0 0
0 0
0 0 0
( 0 1 0 0 0
0
0 0 0 0 0
0 0

f) Parity generator:
Aserial parity - bit generator is a two - terminal circuit which received coded message
and adds aparity bit toevery mbits of the message, so that resulting outcome is an error
detecting coded message.
The parity bit are inserted in the appropriate spaces so that resulting outcome is a
continued string of symbols without spaces. For even parity, a parity bit l is inserted if
and only if the number of ls in the preceding string of three symbols is odd. For odd
parity a parity bit 1 is inserted and only if the number of ls in the preceding string of
three symbols is even.

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Odd parity bit Generator

State diagram and state table of an odd parity bit generator are shown below.
PS NS
X=0 X=1
A B.0 C.0
B D,0 E,0
C E,0 D,0
D F,0 G,0
E G,0 F,0
A,l A,1
A,0 A,0

State table
0/0 /0

1/0
1/0
0/0

0/0 1/0 1/0 0/0

State Diagram

Even Parity Bit Encoder

B, B, B0 P
0 0 0 B. B,
00 1 Bo 00 01 11 10
0 1 0 00
0 1 1 1
10 0 1
0 0

1 1 0 1

P=B,B, B, + B, B, B, +B, B, B, =B, B, B, +B, B, B, +B, B, B, +B, B, B,

= B, (B,B, +B, B,)+B,(B, B, +B,B,) = B, (B, B,) +B, (B, ©B,)
g) Encoder:
An encoder performs a function which is inverse to the function performed by a decoder.
An encoder has 2 nos of input & n nos of output line. The output line generate the
binary code for 2" input variables.
In encoder circuit, it is assumed that only one input line can be equal to Iat any time.
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An encoder convert an active input signal into a coded output signal. Fig. Shows block
diagram of a encoder. In this fig. 2" nos of input line only one of which is active. Internal
looic circuit of the encoder convert the active input to a binary output withn nos of DIS.
Block diagrum

2" input Encoder

n nos of output

h) Decimalto BCD encoder: decimal to BCD

One of the most common and, useful input devices for a digital system is
It has set of switches
encoder. Most common example is that of a calculator keyboard. them ON or OFF.
to turning
that generate 1 and 0' logic combination in response
There is one switch for each number between 0 and 9.
circuit in the form of a BCD code, the
When a particular number is fed to the digital
switch corresponding to that number is pressed. NAND gates is shown in the figure below. In
A circuit of decimal to BCD encoder using
circuit, the input is active low and the output is in uncomplemented form.
this AND gates are used]
[If both input and output active-then

Inputs are active law

Closed switch
Means logic 0"
6 8 9
0 2

BCD
Output

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ARITHMETIC CIRCUITS

G Chapter at a Glance
Parallel binary adder: Consider two 4 bit binary numbers: A = A;A;A;A, and B
B,B-B,B¢
Theaddition of A & B will perform as follows:
C3 C C Co Carry
A= A3 A A Ao
B= B; B B Bo
S= S. S; S So
Where So = A+ Bo; S, = A,+B, + Co
Co is carry generated (if any) by'addition ofAo +Bg i.e. Column Iand C, is carry generated (i
any) by addition of Col.2 and so on.
S, = A, +B, +C,:S, = A; + B, +C; S, =C;
Atwo 4-bit binary adder circuit can be designed by using 4full adders. The resulting circuitis
called parallel binary adder.

Circuit diagram
A; B: B, A B A Bu

FA FA FA
FA

C S S.

Full adder circuit from two half adder circuit:

A
A, S; A; S:
Half Halt
adder adder

B |B
c.
Co
Cuz

Fig: Block diagram of full adder circuit using half adder circuit.

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 ANALOG& DIGILAL ELECTRONICS
Circuit diagram

Ci

Boolean expression
S= A BOC ...()
C, = A.B +(4 B).C,
C,= AB+(AB+ AB)C, = AB(1+C)+(AB+ 4B)¬,
=AB+ ABC, + ABC, +ABC, + ABC, =AB+ BC; (4+A)+ AC, (B+ B)
= AB + BC, + AC, ... (2)
The equation 1&2are representing the sum (S) Carry (Co) of a full adder circuit.
Very Short Typeguestions
1.The carry output of a full adder is three input WBUT 2007]
a) majority logic b) minority logic c) XOR logic d) NAND logic
Answer: (d)

2. How many fulladders are required to construct mbit parallel adder?

WBUT 2010, 2011]
a) m/2 b) m-1 c) m d) m + 1
Answer: (b)
3. Acarry look ahead adder is frequently used for addition because, it [WBUT 2010]
a) is faster b) is more accurate
c) uses fewer gates d) costs less
Answer: (a)
circuit is
4. The minimum no. of NAND gates required to design one full adder
[WBUT 2011]
a) 6 c) 10 d) 9
b) 5
Answer: (a)

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Short Answer Type Questions

1. Design a logic circuit which add two BCD sum using binary adders and othe
necessary logicgates. Explain the operation.
Answer:
WBUT 2005, 2010)
While adding two BCD sums, we should keep in mind few points:
i) Whatever the value of 4bit together exceeds the value 9 or when a carry 1S generated
the '6 should be added i.e. (0110) in binary.
Now consider, So, S,. S,, S, as the output after addition ’
S, So Decimal equivalent Correction
Required
a l - - - -S;- 0
0
----- 0
-0 -
0 1 3
4
0 5

7
8
0 1 9
10
0 1 11
1 12
0 13
14
1 15

S,So
S;S;
0 :: *= S,S, +S,S,
S;S,
This gives us the correction
1 circuit

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 ANALOG &DIGITALELECTRONICS

B. B- B, B, A:A;A; A

4bit binary Adder

carry
S: S, S: S

01 I 0 4Bit Adder

+ Final O/P

S; S; S Su

2. Implement a FullAdder circuit using a 3 x 8 decoder and OR gate.

[WBUT 2005, 2006]
OR,
other logic gates.
Implement a full adder circuit using a 3-to-8 decoder and [WBUT 2014]
Answer:

S(x, y, z)=m(1,2,4,7) =sum

C(x, y, z) = )m(3,5,6,7) = carry The
inputs and a total of 8 minterms and we need a 3 to 8 decoder.
Since there are 3
implementation is shown in figure below.

3:8
decoder C

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princ1ple of a serialadder
3. With the help of a block diagram, explain the working
[WBUT 2010)
Answer:
The serial adder accepts as input two serial strings of digits of arbitrary Tength. starting
the two bit streams as its output. The
with the low order bits, and produces the sum of registers clocked simultaneously. ) Thic
shift
input bit streams could come from, say, two
device can be easily described as a state machine.
case of an adder, this is easy: all
-- in the
We first decide what must be 'remembered" there is a carry to be added into the next
or not
that must be remembered is whether
Therefore, the device will have two states, carry =0(Co), and carry =
highest order bits.
shown in the Figure. We next identify the transitions between the states. and
=I(C),as
Figure shown below. input/output
the necessary outputs, also shown in
11/0 01/0
00/0
10/0
01/1
11/1
10/1 00/1
diagram as follows:
We can derive a state table from the state Next state Output
Present state Inputs
0 Co 0

0 1

1
Co 0

Co 1

0 Co 1

C 1

C
1 C 1

two Half-adders. Write the truth table of

Half
4. Implement Full-adder circuit using
WBUT 2012, 2015, 2017]
subtractor.
Answer:
Full Adder Circuit fromHalfAdder Circuit
Block diagram A
A S
A,.HalfS Half
adder adder

B
B B
Co
Cuz

Fig: Block diagram of fulladder circuit using half adder circuit

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Truth table of Halfsubiractor

Input output
D B

1
0
0

5. Draw a BCD adder circuit to add two BCD numbers maximum up to9. The output
of this address should be in BCD. [WBUT 2013]
Answer:
Refer to Question No. IofLong Answer Type Questions.
6. Implement the following using 3 to 8 line decoder. Use active low decoder
outputs:
YO (A, B, C) = Em (0, 1, 2,4). [WBUT 2019]
Answer:
Inputs Outputs
A B C Z
0 0
|--- 1 1
1
0
1 1 0
0
1
1

D(A.B,C) =Em(0,1,2,4)
decoder. The
Since there are 3- inputs and a total of 8 minterms, we need a 3-to-8
implementation is as shown in figure below:

A 38
D
decoder

Fig: 3to8 decoder

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Long Answer Type Questions

1. Design and draw the circuit to add two BCD numbers using 4-bit binary 20081adder
and other suitable gates.
Answer:
WBUT
To start with adding two BCD numbers we must keep in mind the Tolowing points
sum is equal to or less than 9 the sum is valid BCD numbe.
the44bitbit sum is greater than 9 or if a carry is generated from the sum, the
If the
1.2. If
su
sum is invalid BCD number, then, the digit (0110) should be added to the
to produce the valid BCD symbols.
Sums Correction required
S S So
0
1
0
0

1 1 0
0 0 0

0
1

Expression for Y
S,S. 00 01 11 10
S,S;
00

Y= S;S,+S;S,

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 ANALOG &DIGITAL ELECTRONTCS
B, B, B, B, Ai A; A, A.,

C,
4-bit Binury adder Ce.

|s.sSS.

1
Cout
ignored 4-bit Binary adder

S: S: Si So

Logic diagram of BCD adder

2. Design full subtractor using 4:1 multiplexers. WBUT 2009, 2011]

Answer:
Truth table of full-subtractor
B b; (C) d
0
1 1
1
1 1
0 1
1 0
0 0
1 1 1

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4:1
MUX Y;

A EN
S S

Y(O)
B

4:1 Y:
MUX

EN

two 3 bit
Design and implement a comparator circuit, which can compare
WBUT 2015]
3.
binary numbers.
Answer:
Let A= A,4,4, A, B are two inputs
B= B,B,B,

E, = B, A + B, A
E, = B 4 + B 4
E, = B, A, + B, A,
when A= B. E =E, E, E,
when (4> B). F= 4, B, + E,4, B, + E,E, A, B,
when (4< B). G= A,B, + E, 4,B + E,E, 4,B,
ADDERISUBTRACTOR circuit.
4. Design a 3 bit binary parallel combined [WBUT 2015]
OR,
circuit, using a
Design alogic diagram, using logic gates, for addition/subtraction
when P=0, and ful
control variable P such that this operates as full adder WBUT 2018]
subtractor for P=1.

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 ANALOG& DIGITALELECTRONICS

Answer:

D
X Y

ADDSUR

FA FA FA FA

C S S S.

4-bit parallel adder / subtractor

I has two 4-bit X;,X and Y,),YY,. The ADD / SUB control line connected with
C. of the least significant bit of the full adder is used to perform the operation of
Addition/Subtraction. The EX-OR gates are used Control Inverter.
The circuit functions as a 4-bit adder resulting in sum S,S,S,S,
two half
5. Draw circuit of a full adder. How you obtain a full Subtractor using
Subtractor? [WBUT 2016]
Answer:
1" Part: Refer to Chapter at a Glance.
2nd part: Bar in

D
D
Full subtractor using two half
subtractor
-Bar out

[WBUT 2010, 2011, 2012]

6. Write short note on BCD Adder.
Answer:
BCD Adder:
invalid.
In BCD code 0- 9 are valid and 10- 15 are addition. If
result is less than 10 then it is a valid
When two BCD number are adder and
exceeds 9 then we should add 6 to the result to get a valid BCD number. A carry is
Tesult
generated for the next dig1t.
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MSB LSB
Circuit diagram B: B; C; Ci D, D;
A: Ai

Carry Carry Carry Carry

F.A F.A F.A F.A
Cn CC Cin

Carry
to the
next
BCD
adder
D

FA
Carry F.A

Rules for BCD addition

1 Add two BCD number
S; S S Su
2. if the result is greater than 9
3 or, if there is generated carry then add 6 to the digit.
The top row of four full adders add the numbers A1, Bj, Ci, D, and A2, B, Cz, D, one or
the
the other AND gates will find its output at logic 1, whenever the sum generated is incarry
range of 10 to 15 the output of the OR gate will be at the range 10 15 or whenever
6 = 01 10 will be
is generated. Whenever the OR gate output is at logic 1, the number
added as required.

7. Implement a full subtractor using demultiplexer. WBUT 2017]

Answer:
The MUX diagram is shown below:
C
f(A, B, C)

C
Output

C:

A B

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 ANALOG& DIGITAL ELECTRONICS
There aretwo outputs i.e.. Sub and Borrow. So two MUX are to be selected. The truth
Lableoffulssubtractor using K Maps.
T'he truth table is as follow:
A
SUB BOR
0

0 1

0 0
1 1

Connection Diagram:
Subtractor:
Input A

NOT 1 10

4:1
-o Sub
NOT 2 MUX

13 Si S

Input B Input C
Borrow:
10
Input A

NOT I
11

o Borrow
12

13
S S
NOT 2

Input B Input C

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FLIP - FLOP

r Chapter at a Glance
the present state but also depend on the
The sequential circuits, the output not only depend on
state of the system. There are two types of flip-flops. (i) Edge-triggered tlip-flop. (i)
past
level- triggered flip-flop.
the brief instant the clock switches from
An Edge triggered Flip Flop responds only during the positive going edge of the clock. it
one voltage level to another when triggering occurs on
occurs in the negative edge, it is called
is called Positive-edge triggering and when triggering
Negative-cdge triggering.
particular stage i.e. either high or low switching
A Level triggered Flip Flop responds only a
for a time.
Flip Flop, JK Flip Flop and Master Slave
Ex: Flip Flop can be divided into RS Flip Flop, D
JK FlipFlop.
circuit. It can be constructed using NAND or
Latch: A latch is the most basic type of flip-flop
NAND gate latch (ii) NOR gate latch.
NOR gates. There are two types of latches.(i)
information. It has two stable states, which can
RS Flip-flop: RS Flip-flop used as restoring
inputs. The flip-flop will assume one of its
be achièved by giving proper inputs to R and Sin the circuit.
two stable states depending upon any asymmetry
flip-flop. Hear we overcome the race
JK Flip-flop: JK flip-flop is modification of SR called an universal flip-flop because the
condition which occur in JK flip-flop. JK flip-flop is
it.
other flip-flops like D, R-S and T can be derived from
equal to exactly one cycle of the clock.
Dflip-flop: D Flip-Flop is a flip-flop with a delay (D) S, so that input to R is always the
In D flip-flop input to R is through an inverter from
complement of S and never same.
labelled T for toggle. When T is HIGH.
T flip-flop: A T Flip-flop has a single control input,
the flip-flop toggles on every new clock pulse.
Very Short Type guestions
after clock is WBUT 2007]
1. Flip-flop that makes output equals to input d) none of these
a) J-K flip-flop b) Dflip-flop c) T flip-flop
Answer: (b)
be
2. A certain JK Flip-Flop has to = 12 ns. The largest MOD counter that can
constructed from these Flip-Flop and stilloperate upto 10MHz is [WBUT 2008]
a) 255 b) 265 c) 8 d) 10
Answer: 256

3.The characteristics equation of the T-FIF is given by WBUT 2008]

a) Q+ = TQ + TQ' b) Q+ = TQ' + QT
c) Q+ = TQ d) Q+ = TQ'
Answer: (b)

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 ANALOG & DIGIAL ELECTROVICS

Kflip -flop has [WBUT 2009, 2011]

4.J- one stable state b) two stable states
a)
stable state d) none of these
c)no
Answer:(b)
5. The race-around condition does not occur in Flip-Flop [WBUT 2010, 2011]
a) J-K b) Master slave c) T d) None of these
Answer: (b)

e if theflops
inputis tocascade
T-flip - isflop is 100 Hz signal, the final output of the three
T. flip - [WBUT 2012]
a) 1000 Hz b) 500 Hz c) 300 Hz d) 12.5 Hz
Answer: (c))

7A
carry look ahead adder is frequently used for addition, because it
a) is faster b) is more accurate WBUT 201 3]
c) uses fewer gates d) costs less
Answer: (a)

8 If the input to T-flip-flop is 100 Hz signal, the final output of the three T-flip-flop
in cascade is WBUT 2015]
a) 1000 Hz b) 500 Hz c) 300 Hz d) 12.5 Hz
Answer: (c)

9. Master-slave configuration is used in flip-flop to [WBUT 2018]

a) increase its clocking rate b) reduce power dissipation
c) eliminate race around condition d) improve its reliability
Answer: (c)
10. In Asynchronous circuit Race condition always arises. State True / False.
[WBUT 2022]
Answer: True

11. Five JK flip-flops are cascaded toform circuit shown in figure. Clock pulses at
a frequency of 1 MHz are applied as shown. WVhat will be the frequency (in kHz) of
the waveform at Q,? [WBUT 2022]

J4 Q4 J3 Q3 J2 Q2 Q1 JO QU
>clk >clk clk
> clk > clk
KI KO
K4
|K3 K2

clock

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Answer:
from the LSB.
Here asked the frequency at Q3, which is the 4" Flip-flop
..For n =4, the output frequency (fout) will be:
Input frequency =62.5 kHz
ft 24
therace around willoccur or net
12. Consider the given circuit. Explainwhether,
[WBUT 2023]
A O

Cik o

Bo

Sand B =R. In SR flip-flop there is no race

Answer:
The circuit is a SR flip-flop with input A =
around condition for any combination of input.
Note:
11 is a not allowed state because
the output Q and Q' will be 1.
For race. around Qshould toggle.
and there is unequal propagation delay.
It occurs in JK flip-flop when J =K=I
Short Answer Type Questions
[WBUT 2006, 2014]
using NAND gates only.
1. Implement a clocked JK flip-flop OR,
flip-flop using NAND gate.
Draw and explain the master-slave J-K [WBUT 2013, 2017]
Answer: D
A B

0= AD.

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 ANALOG & DIGIAL ELECTRONICS
2. Drawlogic di.agram of Master/Slave JK flip-flop. Why it is called so?
WBUT 2006, 2008, 2009]
Answer:
Logic diagram
-

CLK

Master Slave

The Master-Slave Flip Flop is level clocked. When clock is high: therefore any changes
in IandK can affects and R outputs. For this reason, normally we keep J and K constant
during positive half cycle of the clock. After clock goes low, master becomes inactive
and we allow Jand K to change.

3. What is the main difference between a Latch and a flip-flop? [WBUT 2008, 2019]
OR,
Distinguish between latch and flip-flop. WBUT 2013, 2017]
Answer:
Both flip-flop and latch are bi-stable and are used to store binary data but in flip-flop state
change only occurs on a clock edge or pulse whereas in latch, change state occurs without
being clocked. So it can be concluded that FlipFlops are clocked but latches are not.
4. Convert J-K to S-R and J-K to T. WBUT 2010]
Answer:
To convert JK F/F to SR F/F, we combine the excitation tables of both the flip-flops.
R D| J K
0 0
x
2
0 0 1 x
4 x
0
0
x-o
X
3
x
X
X

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K-maps
SR
00 01 10
K-maps for J
SR
00 01 1| 10
X X X
X

X 1||= S
X
K=R
X

Circuit diagram
J

CLK
K

The truth table is shown below:

T Q K
X

0 X
1 1 X

X 0
K-maps for J: K-maps for K:
T T
0
0
X
J=T
0 K=T

Circuit diagram

CK

5. Explain
Master Slave Flip-Flop.
(WBUT2010]

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Answer:
e J-K
diagramof Master-Slave. Flip-Flop
Block

Master Slave

K K Q

CLK

LogicCircuit
Logicdiagram

CLK

DD
Slave
Master
changes
level clocked. When clock is high; therefore any constant
The Master-Slave Flip Flop isoutputs. For this reason, normally we keep J and K inactive
in J and K can affects
and R
clock. After clock goes low, master becomes
of the
during positive half cycle
change. The truth table is
shown below.
and we allow J and K to
Truth Table K Q
CLR CLK
PR X X
X
0 X X
1 X
0 X
X X
0 0 NC
X
1 0
1 Toggle
1 Master-slave J-K Flip-flop
Truth Table for the
Figure
as shown in
Timing diagram master-slave J-K flip-tlop
operation of the
below examine the
below.

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SET SET :SET!

:RESET
Fig: Operation of master-slave J-k
6. What do you flip-flop
using master-slavemean by race around condition? How
flip-flop? this problem is solved
Answer: WBUT 2016, 2018, by
2019]
Race around condition
occurs when both the input are
undergoes a transition state. For example. Consider the high And the output thus
iej=k=1,the
The remedy for Output q0=0 in normal case will input values in a jk flip flop;
race around problem can be change and vice versa.
to l
flop. eliminated by using a master slave j-k flip
7.
Implement the function of Dflip-flop using J-K
Answer:
In order to create D flip-flop. WBUT 2017]
are taken from J-K flip-flop using-J-K, -inputs
o isare given as Dflip-flop inputs and
flip-flop.D Conversion table shown below, outputs
K
0 0

K Map solution for J: X

0

X
1
X

J=D
K=D

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 ANALOG& DIGITAL ELECTRONICS

LogicDiagram:

D
J-K flip-flop

D flip-flop using J-K fAip-flop

8. Describe the working of S-R flipflop using truth table, logic diagram and
excitation table. WBUT 2017]
OR,
Explain the working of S-R flip-flop. [WBUT 2019]
Answer:
SR Flip-flops were used in common applications like MP3 players, Home theatres.
Portable audio docks, and etc. SR latch can be built with NAND gate or with NOR gate.
Either of them will have the input and output complemented to cach other. Here we are
using NAND gates for demonstrating the SR flip flop.
Whenever the clock signal is LOW, the inputs S and R are never going to affect the
outDut. The clock has to be high for the inputs to get active. Thus, SR flip-flop is a
controlled Bi-stable latch where the clock signal is the control signal. Again, this gets
edge triggered SR flip-flop.
divided into positive edge triggered SR flip flop and negative which have been discussed
Thus. the output has two stable states based on the inputs
below.

Set Pin Output

Inverted
Reset
R Q Output
Pin

Clock

SR Flip-flop
Truth Table: Output
CLOCK State Input
Clock S R
X
Low (0
0
HIGH
HIGH
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0
HIGH
1 1
HIGH

Diagram: S
b3
2
2

CLOCK

1 3
2
R 2

9. a) Difference between seguential circuits and combinational circuits.

b) What is triggering? How many types of triggering are there in sequential
circuits? [WBUT 2018]
Answer:
a) Refer to Question No. 5(I" Part) of Long Answer Type Questions.
b) Refer to Question No. 8 of Long Answer Type Questions.
10. What is the disadvantage of S-R flip-flop? How can it be overcomne? Explain.
WBUT 2019]
Answer:
1" Part:
The one major disadvantage of the S-R flip flop is that in the condition when the clock
is triggered the inputs become high which is an undesirable condition because it causes
invalid input.
2nd Part:
It is avoided by feedback to convert it into JK FF in which making both inputs, J and K
will give one more different output that is toggle. This toggles it's last output so that if
output was earlier 0 by toggling it will become l and vice versa.

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 ANALOG &DIGTAL ELECTRONIS
Toggles on leading cdge
of clock signal SR lip-flop

JO J-K
Filp-flop
CIk O CIk O

KO

R
Symbol
Circuit
conversion of Dflip-flop to J-K
11. Perform
Answer:
flip-flop. [WBUT 2022]
Step1: Write the
truth table of the required flip-flop
Here the required flip-flop is JK flip-flop
Hence you need to write the truth table of JK flip-flop which is
J K
0
0 0 1
0 0
1 0
1
1 1
1 1

Step 2: Write the excitation table of the given flip-flop

In this case the given flip-flop is Dflip-flop
Therefore you need to write the excitation table of Dflip-flop which is

0
0 1
0
1

Step 3: Write the conversion table

conversion table. which is a combination of truth table and excitation table, to
mplement a JK flip-flop using D flip-flop is as follows
D
J K
0 0
0

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0
1 1 0
0 1
1
1
1

Step 4: Find the Boolean expressions for the inputs of the given flip-tlop
In this case the given flip-flop is D flip-flop.
herefore, write the Boolean expressions for Dfrom the conversion table using K-Maps.
K-Map for D:
KON KQN KO,

Expression for D would be

D=KO, +JON
Step 5: Draw the circuit for implementing JK flip-flop from D flip-flop
For this, connect the D input of the D flip-flop to the circuit made for the Boolean
expression for D.
Therefore, the circuit would be:

K
D QN
D-FF

QN

12. Perform conversion of S-R flip-flop to J-K flip-flop.

[WBUT 2022]
Answer:
Step 1: For conversion of SR Flip flop to JK Flip flop at first we have to make combine
truth table for SR flip flop and JK Flip Flop. In bellow see the combine truth table of SR
flip flop and JK FlipFlop.

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 ANALOG &DIGIIAL ELECTRONICS
FF
data Output S-R FF inputs
inputs
J K Q S R
0
X
X
0
1

1
0
X
1
X

From above truth table we can understands what are the different inputs we need to get
the outputQ.

Sten 2: Now from above truth table we can draw the Karnaugh map for input S and R.
Then we can easily get the relation between SR with JK. And we can did conversion of
SR Flip flop to JK Flip flop. For that see bellow.
KO 00 01 11 KQ 00 01 10
J

0 0 X X

For S JQ For R KÌ

Now from this above Karnaugh map we get the relation S= JØ and R= KO.
Step 3: Now as per the relation of S R with J K from Karnaugh map we can easily build
JK Flip Flop using S RFlip Flop.

FF

-
R
K

Realization of a J-K filp-flop using an R-S filp-flop.

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13. In a JK flip-flop, we have J=Q' and K=1 (see figure). Assuming the flip-flop was
initially cleared and then clocked for6 pulses. What will be the sequence at the o
output? WBUT 2023]
Q

K CLK Q

Answer:
Given: Initial state cleared so Q=0
J=Q
K=1
CLK PULSE Present state K Next state
Qn 1 Qnl
1 1 1

3 --- 1
0 0

6 1 0

So the o/p sequence will be 010101.

Long Answer Type Questions

1. Write down the excitation table of JK and D flip-flops. Derive the excitation
equations for these two flip-flops. WBUT 2006, 2008, 2010]
Answer:
Excitation table for J-K flip-flop
Qa-l K
0
1 X

X
x|
X

Excitation table for Dflip-flop

D
0
1
0 0

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 ANALOG& DIGILAL ELECTROSICS
Characteristic cquation for Dflip-flop
. , =D
Characteristic equation forJ-K
. flip-op
Q =/2, +KQ,
2. Perform the conversion from Dflip-flop to JK flip-flop. [WBUT 2006, 2009]
Answer:
The truthtablee of JK Flip Flop and characteristic table for DFlip Flopi is shown in Table
land2,.

J K D
0’0 0
0’1
|’0 0
Qn |’1
Table 1
Table 2
The K.map for DF/F tinal implementation is shown in Table 3and Fig.
KQn 00 01 10

Table 3

D= KQ, + JK
D=Q J+Q K
n

D D

Conversion of.D Flip-Flop to JK Flip-Flop

3. Perform the conversion from S-R to J- Kflip -flop. [WBUT 2009]

OR,
Write down the excitation table and convert SR to JK flip-flop. [WBUT 2013, 2017]
Answer:
To convert SR F/F to JK FF, we combine the excitation tables of both the flip flops.
Flip flop data inputs Output SR F/F inputs
K S R

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0 0 x0
0 x
0 (0
---
1 0

K maps for S:
JK
00 01 11 10

0
S =QJ
X X

JK
00 01 11 10

X X 0
R= QK
S =J.Ì and R=K.Q

Circuit diagram
J
CLK
K
R

4. a) Write truth table, circuit diagram and timing diagram of SR flip-flop

using NOR gate.
b) Convert D flip-flop to JK flip-flop. WBUT 2012]
Answer:
a) RS Flip-flop used as restoring information. It has two stable states, which can be
achieved by giving proper inputs to R and S inputs. The flip-flop will assume one of its
twostable states depending upon any asymmetry in the circuit.

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 ANALOG &DIGIIAL ELECTRONIS
Block diagram

CLK

Logic diagram Block diagram

RO

Truth Table
Inputs Outputs Mode
R

Q No change
Reset
Set
1
Prohibited
(Q, is the o/p of previous state)
b) Convert D
Flip Flop into JK Flip Flop.
The truth table of JK Flip Flop and characteristic table for D FlipFlop is shown in Table
land 2.
K
0 0 -’0 0
0 0-’1
1’0
|’1
Table 1 Table 2

The Kmap for D F/F final implementation is shown in Table 3 and Fig.
KQ, 00 01 11 10

D= KO, + JK
Table 3

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D -Q J+Q K

D
J

K-o
Conversion of D Flip-Flop to JK Flip-Flop

5. What is the difference between a combinational and a sequential circuit? Write

Derive their Boolean expression for
down the excitation table of J-K and T flip flop. [WBUT 2014]
the characteristic equations.
Answer:
1 Part:
Difference between Combinational circuit and Sequential circuit
depend only on present input
() The logic circuits whose output at any instant of time,
state are known as combinational circuit.
depend not only present input state
The logic circuits whose output at any instant of time, circuit.
but also on previous output state are called sequential sequential circuits since the
(ii) Combinational circuits are often faster than whereas the sequential circuit
combinational circuits do not require any memory element
need memory devices to perform their operations in sequence.
2nd Part: K
Qnt1
0 X
1 1 X
0 X 1

1 X
Excitation table for JK flip-flop
Qatt
0 0
1

Excitation table for T flip-flop

3rd Part:
Characteristic Table of J-K Flip-Flop
As we have already discussed about the characteristic equation of S-R flip-flop, we ca
similarly find out the characteristic equation of J-K flip-flop. The characteristic table o
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 ANALOG& DIGITAL ELECTRONTCS

flip-lopis given in table shown here. From the characteristic table we have to find
J-K
outthe characteristic equation of the J-K flip-flop.
Flip-flop lnputs Present Output Next Output
K
0
0
0
1
0 0

0
1
Now we will find out the characteristic equation of the J-K flip-flop from the
haracteristictable with the help of Karnaugh map given in Figure.
K 00 KQ,
01 10

0 0

1 0

JQ,
From the Karnaugh map, we obtain ,., = JO, + KO.
Hence the characteristic equations of J-K flip-flop is ,., =JQ, +KO,
Characteristic Table of T Flip-Flop
As we have alreacy discussed about the characteristic equation of J-K flip-flop, we can
table of T
similarly find out the characteristic equation of T flip-flop. The characteristic
the characteristic
flip-flop is given here. From the characteristic table we have to find out
equation of the T flip-flop.
Flip-flop Input Present Output Next Output

0 1

1 0

flip-flop from the chacacteristic

Now we willfind out the characteristic equation of the T
table with the help of Karnaugh map of Figure.

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Fromthe Karnaugh map. the Boolearn expression of ,. is derived as , =r0. T

Hence the characteristicequations T flip-flop is e,- =T2, +T2,
6. a) Write truth table, circuit diagram and timing
gate. diagram of SR flip-flop using Ne
b) Convert D flip-flop into JK flip-flop.
Answer:
a) RS Flip-flop used as restoring
WBUT 2015]
information. It has twO stable
achieved by giving proper inputs to R and S inputs. The flip-flop states, which can k
will assume one of i
two stable states depending upon any asymmetry in the circuit.
Block diagram R

CLK

Block diagram
Logic diagram
R

So
Logic diagram
Truth Table
Inputs Outputs Mode
S R

Qo Q
|27| No change
Reset
0 0 Set
Prohibited
(Qo is the o/p of previous state)

A&D-142
 ANALOG& DIGIIAL ELECIRONICS
b)Thetruth table of JK Flip Flop and characteristic table for D Flip Flop shown in
is
2,
TableI and
K
0 QnQ D
0’0 0
0 ’1
|’0
|’1
Table 1
Table 2
The Kmap for DF/F final implementation is shown in Table 3and Fig.
KQn 00 01 10

1 0

Table 3
D= KQ, +JK
D=Q J+Q n K

Conversion of DFlip-Flop to JK Flip-Flop

7. Draw the clocked master-save JK flip flop using NAND gate and explain its
operation with truth table. WBUIT 2016]
Answer:
Busic Idea
AMaster Slave flip-flop is constrùcted from two separate flip-flops. The Master-Slave
combination can be constructed for any type of flip-flop by adding a clocked RS flip-flop
with an inverted clock to form the slave.
Rest Answer: Refer to Question No. 5 of Short Answer Type Questions.

8. Write short note on Triggering of flip- flops. WBUT 2009]

Answer:
Inggering means excitation by some means. It is subdivided into two groups namely
i)Edge triggering ii) Level triggering
Ege - triggering Flip-flop: A Flip-flop where state charges on the rising (positive) or
lalling (negative) edge ofa clock pulse
A&D-143
POPULAR PUBLICATIONS

to th
Level triggered Flip-flop: A Flip-Flop that is triggered (i. e. outputs respond
inputs when level of the clock signed is appropriate.
The inputs to the Flip-Flop may change during the presence of the
clock pulse duc
transfoc
certain operating of the system. Incase of edge - triggered Flip-Flop, intorimation
from data input to output of the Flip-Flop occurs at positive or negative edge of the clock
pulse. A Flip-Flop which responds only to rising (or falling) edge is known positive cdoe
triggered or negative edge triggered.
below; explain with
3. a) What is the equivalent flip-flop of the digital circuit given
reason. WBUT 2022)

CLK
Answer:
T flip-flop
X Q() Q(t+1)

1 1
T-FF
0

Truth table of circuit

b) The clock frequency applied to the digital circuit shown in the figure below is
1kHz. If the initial state of the output of the flip-flop is 0, what will be the frequency
of the output waveform Q in kHz? WBUT 2022]

Answer:
The given circuit is in toggle mode, so frequency will get half,
Output frequency = 0.5 kHz
A&D-144
 ANALOG & DIGIA LLECIRONICS

REGISTER &COUNTER
rChapterat. a Glance

Register:A register is a group of memory clements that work together as a unit. It is of two
nanely Buffer register and Shift register.
kinds
register: Ashift register moves the stored bits left or right. There are 4types of shift
Shift
registers.
input serial output (SISO): The data can moved in and out of the register one bit at
Serial
(i)
a time.
(i) Parallel input serial output (PISO): data can be loaded simultaneously but data can be
removed fromthe register one bit at atime by clock pulse.
parallel output (SIPO): data is loaded serially one bit at a time but the data
(ii)Serialinput
storedcan bee read simultaneously.
parallel output: (PIP0): data can be loaded into stages simultaneously
(iv) Parallel input out or read simultaneouslv.
dan also be taken
modes (i.e. SISO, PISO.
tiniversal shift register: A register which is capable to operate all 4
rno sIP0)with bi-directional shifting of data is known as Universal register".
the
counter: A serial output of a shift register is connected back to the serial input then
Ring is referred to as ring counter.
feedback pulse will keep circulating. This circuit tocount the number of clock pulses
Cannter: A counter is a special kind of register, designed
arriving at an input. measurement frequency and time period.
In the digital equipments, counters are used for manipulation.
sequencing of equipment operation, frequency division and
ICs.
Counters are composed of flip-flop or
Asynchronous counter: When the flip-flops are connected serially and output of preceding
asynchronous counter as the change of states
flip-flop clocks the succeeding flip-flop, it is is high than the synchronous
counter the time delay
occurs one after another. In asynchronous
sequential counter.
counter, so frequency is low than the
Synchronous counter: In synchronous counterpulse. alltlip-flops are clocked simultaneously with
parallel to clock
the clock's input connected in counter. The pulse to be counted is applied at the
This increases the speed of operation of the
clock input terminals.
Look ahead adder:
J, Q:
FF; FF
FF FF:

K, Q K, Q:
K, Q

synchronous up counter
Logic diagram of a 4-bit term Ql, Q:, is called carry, i.e. it
is
in figure above, the
A0It up-counter shown throughthe successive AND gates.
brougnt forward to each stage. The carry must ripple
A&&D-145
 POPULAR PUBLICATIONS

Very Short Type guestions

counter. Thefrequency of a
1. A10 MHz square wave clocks have a 5 bit ripple
3° lip-flop's output is
a) 2 MHz b) 1.25 MHz c) 50 kHz
WBUT 2007]
d) 25 kHz
Answer: (b)

2. Which one is the sequential circuit? WBUT 2012, 2015]

c) Encoder d) Counter
a) Multiplexer b) Decoder
Answer: (d)
3. The flip-flop required to design a MOD-18 counter is WBUT 2013]
d) 6
a) 3 b) 5 c) 4
Answer: (c)
counter is
4. The minimum number of flip-flop require to design a MOD-10
WBUT
d) 05
2014)
a) 03 b) 10 c)04
Answer: (c)
problems encountered with
5. Synchronous counters eliminate the delay [WBUT 2016]
asynchronous (ripple) counters because the
only to the first and last stages
a) input clock pulses are applied simultaneously to each stage
b) input clock pulses are applied
c) input clock pulses are applied only to the last stage counter stages
any of the
d) input clock pulses are not used to activate
Answer: (b)
counters indicates that WBUT 2016]
6. A comparison between ring and Johnson path
a) a Johnson counter has an inverted feedback
decoding circuitry
b) a Johnson counter has more flip-flops but less
path
c) a ring counter has an inverted feedback decoding circuitry
d) a ring counter has fewer flip-flops but requires more
Answer: (a)
with [WBUT 2017]
7. Synchronous circuits change their state d) none of these
a) input b) clock pulse c)output
Answer: (b)
[WBUT 2017]
8. The number of flip-flops required to design a Mod 10counter is
b) 4 c) 5 d) 6
a) 3
Answer: (b)

9. To avoid the thermal runaway, qpoint should be such that it satisfied[WBUT 2018]
a) Ve = Veel2 b) Vee < Vecl2 c) Vce >= Vccl2 d) Vee < Vecl4
Answer: (c)
A&D-146
 ANALOG & DIGITAL ELECTRONICS
10. A4-bit mod 16 ripple counter usos JK flip-flop, if the propagation delay of each
flipflopis100 ns, what will be the maximum clock frequency (in MHZ) that can be
counter?
used in the (WBUT 2022]
Answer:5 MHz

11. A mod-n counter using a synchronous binary up-counter with synchronous

clearinput is shown in the figure. What will be the value of n?
WBUT 2022]
Answer:
Sinceitis given that the counter have synchronous clear input. the output of the counter
the zBh clock pulse.
willreset at
The mod of the counter =7

Short Answer Type Questions

4Design MOD-10 synchronous counter and draw the timing diagram.
WBUT 2010]
Answer:
AMod-10counter has 10 possible states, in other words it counts from 0 to 9 and rolls
Over. Let's take a look at how to build a Mod-10 counter.
The first step is to determine how many flip-flops to use. We will use JK FFs for our
design. Since we need 10 states, 4 FFs will be required. The trick is to find a way not to
nse all of those states. There must be a way to force the counter to stop counting at 9 and
rollover to 0. This is where an asynchronous inputs come into play. The asynchronous
inputs can over-ride the synchronous inputs and force the outputs to either LOW or
HIGH.
Looking at the truthtable, the counter should run from 0000 to l001 and roll over to 0000
again. Since the counter has to display 1001, the next binary value 1010will be used to
reset the counter to 0. For a JK FF, we have an asynchronous input called CLEAR, when
you assert this, flop's output goes to 0. Since this CLEAR input is active high, we can use
ANDgate. The 2 FFs where a "' occurs will be tied to an AND gate and the output will
be tied to a CLEAR input. When the counter goes to 1001, the AND gate has a value '1'
on its output and willactivate the CLEAR inputs of all FFs.

A&D-147
POPULAR PUBLICATIONS

(8s) (4s) (1s)

Q,
Clock input Courter 0.
Q

Q,

MR
GND

2. Distinguish between ripple counter and synchronous counter. [WBUT 2013]

Answer:
Asynchronous (ripple) counters:
The simplest counter circuit is asingle D-type flipflop, with its D (data) input fed from
its own inverted output. This circuit can store one bit, and hence can count from zero to
one before it overflows (starts over from 0). This counter will increment once for every
clock cycle and takes two clock cycles to overflow, so every cycle it will alternate
between a transition from 0 to I and a transition from 1 to 0. Notice that this creates a
new clock with a S0% duty cycle at exactly half the frequency of the input clock. If this
output is then used as the clock signal for a similarly arranged D flip flop (remembering
to invert the output to the input), you will get another 1 bit counter that counts half as
fast. Putting them together yields a two bit counter:
cycle Ql Q0 (Q1:Q0)dec
0000
I011
2102
31 13
4 000
You can continue to add additional flip flops, always inverting the output to its own
input, and using the output from the previous flip flop as the clock signai. The result is
called a ripple counter, which can count to 2n-1 where n is the number of bits (flip flop
stages) in the counter. Ripple counters suffer from unstable outputs as the overflows
"ripple" from stage to stage, but they do find frequent application as dividers for clock
signals, where the instantaneous count is unimportant, but the division ratio overall is.
(To clarify this. a 1-bit counter is exactly equivalent to a divide by two circuit - the output
frequency is exactly half that of the input when fed with a regular train of clock pulses).

A&D-148
 ANALOG&DIGIIAL ELECTRONICS

ychronoSCOUNters:
stable count value is important across several bits, which is the casc In most
Wherca
systems,ssynchronous counters are used. These also use flip-flops. either the D-
counter
the more complex J-K type, but here. cach stage is clocked simultaneously by a
pe
or
commonclock signal. Logic gates between each stage of the circuit control data flow
to stagesothat the desired count behaviour is realised. Synchronous counters
fromstage
canbe
designedto count up or down, or both according to a direction input. and may be
presettablevia aset of parallel "jam" inputs. Most types of hardware-based counter are of
thistype.

the basic logic circuit arrangement of a 3 bit ripple counter using flip-flop
3. Draw
andbrriefly describe the operational principle. [WBUT 2013]
Answer:
Counter
3-bit Ripple down
+V +V

CLK K
K

FFo FF FF2

The figure shows the circuit diagram of 3 bit down counter. The truth table is shown
below.
State
0 1 1 1
0
2
3 0
4 1
5 0
6 1
7 0

mually all flip-flop are reset and cantor output will be 111. As soon as the first clock
pulse is applied to FF, it willbe set. The complex output of FFo is 0. Output of FFi will
ve U and in complement is 1output of FF, will be 0at in complement is 1. So counter
uiput is 10. In this way process continues and at the end of seventh clock pulse, center
Output is 000.

A&D-149
 POPULAR PUBLICATIONS

4. Describe the operation of a bidirectional universal shift register (with parallot

load) with a neat diagram. WBUT 2013, 2017
OR,
Draw and explain the 4-bit bi-directional Shift Register using mode control (M
when Mis logic zero then left shift an right shift for Mis logic one.
Answer:
WBUT 2018]
Bi-directional Universal Shift Register
Aregister which is capable to operate all 4modes (i.e. SISO, PISO, PIP0, SIPO) with bi.
directional shifting of data is known as "Universal register".
The operation of bi-directional shift register is controlled by a mode control bit m. When
m=0, register is right shift register andfor m= 1, register is left shift register.
Circuit
D.n
diagram

Right/ Left

|G

D, Q D, O, D, Qi D, Q1
FF, FF FF FF

CLK O
Fig: Logic diagram of a 4-bit bidirectional shift register

The equivalent circuit with m=0 and m=lisshown in the fig.

D Qi D D D,
FF; FF: FF FFo
(m =0)

D D,
Serial 1/P
D D,
FF; FF; FF1 FFo
(m=1)

A&D-150
 ANALOG &DIGIIAL ELECTRONICS

out what will be the modulus of this counter? (WBUT 2023]

6.Find

lo K lo K

CLK O
Answer:

Fora JK flip-flop
., =JQ, +9,K
Inabove combination
Qo,=o and Q,=Q,g
Counter
So. itacts as a Mod-3
(..2):(0,0) ’(1,0)’ (0,1)’(0.0)
Long Answer Type Questions
1. Describe Johnson counter. [WBUT 2005, 2007, 2008, 2010]
OR,
Write short note on Johnson Counter [WBUT 2012, 2016, 2018]
Answer:
The goal is to design a Johnson counter that can count up or dowh, depending on the
setting of a control input UP/DOWN. The block diagram of the counter is given in
Fig I. 000 up
down

up / down 00 100 up 001

01
-02
cLoCK-> I10 01|
RESET

Fig: 1Symbol of the 3-bit up/down Johnson counter

Fig: 2State diagram of the up/down Johnson counter
The Ounter has an asynchronous reset (or clear) input which brings the outputs to 0 as
O ds the RESET signal is asserted. The counter counts at the negat1ve edge of the
clock. When the UP Input is high, the counter counts in one direction and when UP is
low, it counts in the other dircction, as shhown inthe state diagram of Fig 2.

A&D-151
POPULAR PUBLICATIONS

2. Design a 4-bit Up/Down asynchronous counter using all JK flip-flops and other
necessary logic gates. Use one direction control input M. If M= 0, the counter
willcount up and for M=1the counter will count down.
WBUT 2006, 2007, 2010, 20111
Answer:
In certain applications, a counter must be able to count both up and down. Figure show,
the 4-bit up-down counter. It counts up or down depending on the status of the contro!
Signals M. When the M input is at 0, the NAND network between FFo and FF, will gatc
the non-inverted output (Q) of FFo into the clock input of FF,. Similarly, Qof FF will be
gated through the other NAND network
+V
+V
+V

oFF,
K

Qu Q1 Q: Q:
into the clock input of FF,. Thus the counter will count in UP direction. The functional
table of4 bit up counter is shown in Table.

StateM
É----lelee-- FF3 1
FF2 FF FFo

0 3 0
0 4 0 1
0
6

-------|
8
9
10
11
12
1
0 13
14
15
0 16 1

When the control input M is at I, the

inverted outputs of FFo are gated into the Cloch
inputs of FF,. If the flip-flops are initially
the following sequence as given in Table reset to 0's, then the counter will go throug
behaves as DOWN counter. when clock pulses are applied. Then the counte

A&D-152
 ANALOG &DIGIIAL ELECTRONICS
M
State FF, FF, FF
()
15
14
13
12
0
1| 0
10
0
8 0
7 0 1 1
0 0

4 0
3
0 0
1 0 0

3. Draw the circuit for a four-bit Johnson counter using Dflip-flops and explain
operation. Draw the timing diagram for this 4-bit Johnson counter. How do this
timing diagram differ from that of aRing counter? [WBUT 2006, 2011]
Answer:
Johnson Counter
In Johnson counter, inverted output of last state Flip-Flop is fed back to the input of the
first state Flip-Flop. After that an unique sequence is generated due to feed back. The
circuit diagram of the above counter is shown below.

D D D
CLK
FFo FF, FF: FF;

CLR Q CLR Q CLR. Q CLR Q

-CLEAR
Fig: Four bit Johnson counter

The counting sequence of 4 - bit Johnson counter is shown below.

Clock Qo Q Q;
0
1
2

A&D-153
 POPULAR PUBLICATIONS
Clock QQ
5 0 1
0 0
7
Fig: Counting sequence of 4 bit Johnson Counter

The timing diagram of 4 bit Johnson counter is shown in figure.

Q:
The major disadvantage of the counter is that the maximum available states are not fully
utilized and only eight states out of the sixteen used states.
4. a) Design a MOD 40 synchronous binary UP- counter using JK flip- flop &other
necessary logic gates. WBUT 2009]
Answer:
MOD 10 synchronous binary up - counter using JK flip flop.
HIGH
FFO FFI Qi Q2 FF2 Qi Q Qi FF3

Jo J3 D
c
Ko K;

CIk

Counter
b) Calculate the propagation delay for a 4-bit synchronous binary UP
when JK flop- flops are connected in series connection & parallel connection.
Given Propagation delay for Tp(F /F) in 30 nsec & propagation delay of the gates
used in the circuit is 20 nsec (assumed to be equal for all gates). [WBUT 2009]
Answer:
There are ten states in a BCD counter,
.:. Four flip flops are required.

A&D-154
 ANALOG &DIGITAL ELECTRONICS
The count sequence and| the flip flop inputs are as given below.
Present State Next State Flip-Flop inputs
Q,QoQQQoJ 0 0
KoJ K,J, K,J,
0 0 (0
KJ
loolooo|--| 0 xo-xxo-x3
X 1

o---- 0 0
X 0
1
X
X 0
1 0 1 X 0
0 0 X 1
1 1 1
0 X X X X

1 1 X X X

1 0 X 1 X X 1
0 0 0
K -map for Jo K -map for Ko

Jn and Ko does not contain any 0 in K-map ,so Jo = Ko = 1.

K-map for J : K-map for K, :
QiQo QQo
00 01 11 10 00 01 11 10
Q:Q
00 X 00
01 0 1 X X 01 X

11 X X X 11 X X

X X
10 X X 10

K-Q0
K-map for J, : K- map for K, :
QiQo
00 01 11 10 00 01 11 10

00 0.| 1 00 X X X

X 01 0
01 X X

11 X X X 11 X X X X

X X
10 X X 10

J, = 920 K, =99

A&D-155
 Answer:
or Answer:
6.Referoperation.
counter?
ring 5. diagram
Circuit
bidirectional,orADesign PUBLICATIONS
POPULAR
right. Draw
to
A Question the
+p(gute) CLK
four-bitbi-directional a Draw 1 QQ
circuit
10 11 01 00
its K-
reversible,
bidirectional K X 00
Eo. timing for FFo
(30+
20)x10 Qo map
3 X 0 0
shift ofdiagram.4-bit a Fig: for
1
shift Long BCD
shifi registers Logic X J,:
register Johnson counter J
Answer K FF 10
register How 20MHz =diagram X X
&D-156 Q, Q
is and does using
one counter of
using explain
Type 00
J-K the 10 11
in its K
synchronous
flip-flops
which
D Questions. timing FF2 X X X 00
01
flip-flops using map
its
thoperation.
e =o
K, 1 for
diagram D
data flip- K,
is X
shown can :
[WBUT
2010,
2011] FF; J 10
differ flop
be
below. shitt [WBUT &
from
explain
either
2009] that
lett ofits
 ANALOG &DIGITAL ELECTRONICS

LEFT/RIGHT

HDNETO HDs: HDs

Input Data

LIRO
CLEAR

CLS
Input D2ta

Here a set of NAND gates are configured as OR gates to select data inputs from the right
or left adjacent bistables, as selected by the LEFT/RIGHT control line.
counts
7. Design an asynchronous 3-bit up-down counter using J-K flip-flop which
WBUT 2011, 2017]
up when external signal M=l and counts down when M=0.

F
Fo
CLK
K

Down Q:

Q
Answer:
states of the control signal Up and Down.
When
It counts Up or Down depending on the at 0, NAND network between FFo and FF, will
the Up input is at l and Down input is
the non-inverted output ofFFo input the clock input FF1. Similarly Q of FF, will be
gate
input of FF,. This way counter works.
gated through the other network into clock
counter using negative edge trigger JK flip
8. a) Design a 2- bit Asynchronous up
flop and draw timing diagram. [WBUT 2012]
counter using JK flip -flop.
D) Design a MOD -6 Synchronous
Answer:
a) Asynchronous Counter the
flip-flops are connected serially and output of preceding flip-flop clocks after
Wnen the of states Occurs one
asynchronous counter as the change synchronous counter, so
succeeding fli0-flop, it is
time delay is high than the
er. n asynchronous counter the
is low than the sequential counter.
frequency
A&D-157
POPULAR PUBLICATIONS

Block diagram
Clock
As A A A

To Q. Q J,
next
step Q Q, Kl
Asynchronous Counter
b)
Jo Ko J, K, J, KË
So 0 0 1
X
0 0 1 X 1 X
0 1 0 1 X

1 1 X 1 1

S. 1 0 0
Ss 1 0 1. X 0 X

1 1 0 1
S6 1 1 1
X

|0 0 0

00 01 10
1 0

Jo = 9, + , ...1)
Q:Q1
Qo 00 01 T0
X

1 1

Ko = 1 ....(2)

A&D-158
 ANALOG kDIGITAL ELECTRONICS

00 01 10
0 X
X
0

J, = ,go .3)
00
10
X
X

1 X 1

K=Q2tQo ..(4)

00 01 10

0 X X

J, = QQ ..5)

00 01 11 10

1 X

K,=Qo t ..6)

[WBUT 2013]
down counters.
3.a) Design a divide by 5 asynchronouscounter diagram and
a ring with proper circuit
CAplain the operation of
waveform.
OR, WBUT 2016]
Draw the timing diagram of a 4-bit ring counter.

A&D-159
 POPULAR PUBLICATIONS

Answer:
a)

The diagram of Mod 5 counter is shown below.

The counter cannot 0, 1, 2, 3, 4 sequential. After counting 4, it returns to zero so a
conditional circuit is required to reset all flips at the counter state 5. The circuit
and were from is shown below. diagram
CLK
FFo FF, FF:
K

CLR CLR CLR

b) The simplest shift register counter is essentially a circulating shift register connected
so that last flip-flop in the shift register is in some way connected back to the first flip
flop. Most widely used shift register counters are ring counter and Jonson Counter.

A&Ð-160
 ANALOG &DIGITALELECRONCS

Blockdiagram

D Q: D
Q: DQ D

clk clk clk clk

Q

2 3 4 5 6 7 8

Q
Timing diagram

Qu
explain its
for a 4-bit Johnson counter using D flip-flop &
[WBUT 2013]
10. Draw the circuit
operation. OR,
operation of a 4-bit Johnson counter
diagram, explain the WBUT 2017]
With a neat circuit that of Ring
implemented using Dflip-flop. does its timing diagram differ from WBUT 2013]
diagram. How
Draw its timing
counter?
Answer: of the
Johnson Counter state Flip-Flop is fed back to the input
Johnson counter, inverted output of last is generated due to feed back. The
In sequence
state Flip-Flop. After that a unique below.
Iirst counter is shown
Circuitdiagram of the above

A&D-161
POPULAR PUBLICATIONS

D
D
CLK
FE,
FF.

CLR Q CLR Q CLR Q

CLR Q

CLEAR
Fig: Four bit Johnson counter

Ihe counting sequence of 4- bit Johnson counter is shown below.

Clock Qo
0 0
1 1 0 0
2
0
4 1
1

6 0 1
7 0
Fig: Counting sequence of 4 bit Johnson Counter

11. A10 stage ripple counter is constructed using individual flip flops, each having
a delay of 5 ns. What is the maximum allowable frequency of the counter which will
still allowcorrect reading? [WBUT 2014]
Answer:
Assumingtis the propagation delay of each flip-flop.
n= no. of flip-flop
For allowing correct reading clock period will be, Tnxt
.:. Maximum frequency on that can be used in asynchronous counter

n
1 200MH
10x5xi0-g.2 =0.2xl0° Hz =
12. Design an asynchronous 4-bit up-down counter and it will count up when a
signal line M= 0and count down when a signal line M=1. Use only(WBUT
JK flip-flops
2014]
and EX-OR gates.

A&D-162
 ANALOG& DIGITAL ELECTRONICS

Answer:

H, Q
FF: FF: FF,
CIK
K

counter? Draw the circuit diagram and output waveform of a mod 6

43. Whatis a WBUT 2014]
rjgplecounter.
Answer:
COunter is a special
kind of register, designed to count the number of clock pulses
A input.
arrivingatan
In the digital equipments, counters are used for measurement frequency and time period,
sequencing offequipment operation, frequency division and manipulation.
Counterssare
composed of flip-flop or ICs.
+Vcce

FF, FF:
CIk FF

Ko Do Ki K Cr :
Cr

long
the CLEAR (Cr) input of all flip-flop. As
Here output of NAND gate is connected to when NAND
will be no change on the counter,
2s NAND gate output is HIGH, there goes to 000 state.
goes LOW, it willclear all flip-flop and the counter immediately
Output NANDgate will be
MOD-6 counter, count state should be 000 after 101.The output of
M
condition will occur when counter goes from state 101
tOW When , =0, =1i.e., this again
LOW output of NAND gate will clear all flip-flop and it will be HIGH
V0. The
Since , =0, =l condition no longer exist.

A&D-163
POPULAR PUBLICATIONS

NAND
output

14. Design a MOD 4 synchronous counter using J-K flip-tlops and implement a
WBUT2017]
Answer:
K2 J KI Jo Ko
X
1 0 0 X 0
10 0 1 1 0 0 1 X X

11 0 0 00 X 1 X 1
0 00 10 1 1 X 1 X

X X
101 1 1 1 X

K map for J2 Kmap for K2

00 01 10 00 01 11 10
Q2
0 1 X X 0 X X

X X

K-Q0Q,
00 01 11 10 00 01 10
Q2 Q2
x
X 0 X X X X

X X X 1 1

J, = Q2 K= |

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00 01 10 Q
Q: 00 01 10

0 1 X 1 0 X

1 1
X Y
X 0 X

Jo= , Ko = Q1

J Qo

FF; FF; FFo

K: 0,

CLK

Counter, which cycles

Logicdiagram of the synchronous J-K flip- flops.
through the 7-4- 6-0-5-7 using
control
4-bit bi-directional Shift Register using mode
the is logic one. universal
15. a) Draw and explain then left shift an right shift for M How a 4-bit
zero universal shift register?
(M). when Mis logic
facilities available in flip-flops? [WBUT 2018]
b) What are the realized using
multiplexers and
shift register can be
Answer:
of ShortAnswer Type Questions.
Refer to Question No. 4
a)
available in universal shift register: serial converters, which converts the
b)Facilities register is used as
parallel to
shift
) The universal converters. which converts
parallel data into serial data. serial to parallel
universal shift register is also used as
1) The
the serial data into parallel data.

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(onstruction of 4-bituniversal shift register using multiplexers and flip-flops:
B B.
B
B.

S
4x1 4x| 4x| 4x1
S, MUX MUX MUX MUX 4x|
MUX
D:

D, D. O:
Clock FFI FF2 PFa1 D. 0.
CLR Q CLR +CIk
CLR CIk
CLR
Clear
Thiscircuit is the 4bit
universal shift register using 4x1
16. For a multiplexers and flip-flops.
synchronous counter with sequence:
a) Give
b) 265’31’0’2
present state/next state
Write state transition table.
[WBUT 2018
c)
d) Simplify and realize thetablecircuit.
using Dflip-flops.
Draw the state diagram.
Justify where the
e) What should be thedesign counter willgo in lockout condition or not.
Answer: corrective design process toavoid the lockout
a) For a
synchronous counter with sequence: condition?
Present state/next state table: 2’6’5’3’1’0’2
The state transition table
logic is shown in below:
Present State (D,) Next State (Da+1)
6

b) transition table using D

flip-flops:

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DIGITAL ELECTRONICS

c) Simplify and circuit realization:

0 Qx+-) 1
Qr+)
0
1
5 0 1 1
1
1 1 0
1

Circuit diagram:
00 01 1|

0 2 3
1
4 5 7 6

T Qo

Clock

T Q
CIlk

CIk

d) An additional circuit is require to ensure that lock out does not occur. The counter
should be designed using the next state to be initial state from the unused state. Here, in
these problem, there is no lock out problem occurred.

e) The lockout condition occurs when by some glitch or any other reason output goes to
unused state and it is not defined when it should go next. The lockout can be avoided by
designing its state from all of its unused state to initial state. This is said to be lock free
arrangement.
17. A4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of
each FF is 50ns, Find the maximum clock frequency that can be used in this
Counter. [WBUT 2023]

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Answer: propagates through every

the proopagation
In Ripple

counter.
counters.delavs ripples through, or
fip-lop. ig.
of all the flip-flops are added to get the overall delay in the
the carry

must arrive when all

clock pulse
For the counter to work properly, the next
flip-slops and the output is stable
the carrys
generated are propagated through all the This can be
mathematically stated as:
For the ripple counter to count properly:

foIk: i.e.,
lx =Clock Interval and is the inverse of

For 4-bit modulo l6 ripple counter has 4JK flip-flops. The total propagation
be:
delay wil
T=4x50 =200 nsec
.. The maximum clock frequency will be:
f=200n-=5MHz

18. A3-bit gray counter is used to control the output of the multiplexer as shown in
the Figure (A; is MSB and A, is LSB). The initialstate of the counter is 000,. The
output is pulled high. Find the sequence of the output of the circuit. WBUT 20231
A;

3-bit gray A,
counter

A +5V
S S,

4x|
CLK
MUX
Output
3

Answer:
1,,1.1, 1,,1,, 1, 1. 1,
In the given circuit, the 3-bit gray
code. counter converts the given decimal number intogra
The output of gray code is
connected
The output of the multiplexer 1o the selection
is pulled lines ofthe
high. Therefore. the multiplcxer.
output 1s One whenthe
multiplexer is not enabled i.e.. when E=1

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When multiplexer is enablcd i.c.. E-0,the multiplexcr gives the output according to the
selcction lines (S,S,).
Decimal
Gray code Output
Binary of MUX
(4,44,)
0
1
1 0 1 1
3 1 0 1 1
4 1
1 1
1 11
1 1 0 0
7 1 1

17. Write short notes on the following:

a) Data lock-out in acounter WBUT 2006, 2009, 2011]
[WBUT 2011, 2014, 2015]
b) Ring Counter WBUT 2012, 2014]
c) Serial input parallel output shift register WBUT 2017]
d) Parallel input serial output shift register [WBUT 2017]
e) Asynchronous ripple counter
Answer:
a) Datalock-out in a counter:
taking the counter from one unused state to
Acondition that may exist in a counter
counter. It does not allow any of the
another unused state is called Lockout state of the
used state to come in between one. to on
the counter is in its initial sate or it comes
To makes sure that at the starting point provided. This is
clock cycles, external logic circuitry is to be
initial state with in a few
the additional requirements existing counter.

b) Ring Counter: circulating shift register connected so

shift register counter is essentially a
The simplest some way connected back to the first flip-flop.
that last flip-flop in the shift register is in
are ring counter and JohnsonCounter.
Most widely used shift register counters

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Block diagram
D D

dk cik dk

Timing diagram
c) Serial input - Parallel output Shift
Registers
For this kind of register, data bits are entered
the last section. The difference is the way inserially the same manner as discussed in
in
which the
register. Once the data are stored, each bit appears on its data bits are taken out of the
bits are available simultaneously. A respective output line, and all
register is shown below. construction of a four-bit serial in - parallel out

Block diagram
Qo
FFO FF1
Input data GET SET FF2 FF3
D D
D

CLK

CLEAR

d) Parallel input serial output shift

A four-bit parallel in - serial out shiftregister:
flops and NAND gates for entering data register is shown in fig. The circuit uses D
(i.e., writing) to the register. flip
DO. DI, D2 and D3 are the parallel
the least inputs, where D0 is the most significant bit and D3 IS
significant
bit. To write data in, the mode
control line is taken to LOW and the
data is clocked in.

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The data can be shifted when the mode control line is HIGH as SHIFT is active high.
The register performs right shift operation on the application ofa clock pulse. as shown
in the animation below,

Block diagram
D
|Dn D |D:

WRITE/
SHIFT

DSET O 4D SET O DSET OH -D SET Q

CLK. Output
data
CLR Q CLR Q CLR Q CUR

CLEAR

e) Asynchronous ripple counter:

Refer to Question No. 2of ShortAnswer Type Questions.

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PROGRAM LOGIC DEVICES

Chapter at a Glance
Can k
A Programmable logic device is a general purpose chip by which logic circuits
mplemented. Basically it contains a collection of logic elements that can be customizcd i
different ways. PLD can thought to be a black box that contains logic gates and
programmable switches.

Logic gates

and
Inputs Outputs
(Logic variables ) (Logic
functions
Programmable
Switches

Programmable logic array: PLA is the first developed commercially available

Programmable Logic Design. PLA consists of a collection of AND gates which are being fed
to a set of OR gates. As depicted in figure the PLA's inputs Y, Y,Y, pass
buffers into a circuit block, called an AND plane. through a set of
Vn

Input buffer
and
inve rter

P
AND Pane
OR Plane

f f
Programmable array logic: In PLA both AND and OR planes are
some problem in fabricating these programmable which hàs
in which only the AND plane is devices. This drawback is being overcomte in a new device
array logic (PAL) device. programmable but the OR plane is fixed as Programmablc

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Very Short Type Questions

1. A PLA is (WBUT 2010]
a) Mask programmable b) Field programmable
c) Can be programmed by a user
d) Can be erased and programmed
Answer: (c)

Short Answer Type Questions

1. Distinguish between ROM, PLA and PLD's as elements realizing Boolean
Functions. [WBUT 2006, 2009, 2010]
Answer:
ROM
Read-only-memory is meant only for reading the information from it. It is mainly used
for storing information which is fixed.
PLA(Pragrammable logic array)
It is a programmable AND array where product term outputs feed a programmable OR
array.
APLA is to be programmed for the desired input-output relationship similar to ROM.
It can be used to implement combinational and sequential logic circuit.
PLD(Programmable logic device)
It is a logic device which is programmed for designing digital circuit.
It is subdivided two parts e.g. SPLD (Simple Programmable Logic Device) and Complex
Programmable Logic Device. (CPLD).
Long Answer Type Questions
1. Implement the following functions using a 3 x4 x2 PLA: [WBUT 2007]
F, (4, B, C) =) (3, 5, 6, 7)
F,(4, B, C)=X(0, 2, 4, 7)
Answer:
Implement the following function using a 3x4x2 PLA
F(A.B,C)=X(3,5,6,7)
,(A.B,C) =Z(0,2,4,7)
BC
00 10
A

00

01

E =BC +AC +AB

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BC
00 0 10

00 -

F, = BC+AC +ABC
B

BC
D
AC
-D AB

F F
2. Write short note on PLD.
Answer: WBUT 2007,2008]
PLD (Programmable Logic Device)
AProgrammable logic device is a general
purpose chip by which logic circuits can be
implemented. Basically it contains a collection of logic elements that can be
in different ways. PLD can
thought to be a black box that contains logiccustomized
gates and
programmable switches.
It is a logic device in which the
logic function is programmed by the user and can
reprogrammed many times. Types of PLD's are SPLD, be
CPLD and FPG.
Numerous chips are available in the
used. These chips are called Standardmarket
in which commonly used logic
circuits are
Chips. Up to 1980, these types of
were used in different PCBs. The
drawback of this kind of chips is that thestandard
of each chip is fixed and cannot be changed.
chips
functionality
To overcome the above difficulty, the use of
picture. These chips have a very generalprogrammable logic devices come into the
programmable switches that allow the internal strücture
circuitry in
and include a collection of
the chip to be configured in
many different ways. Such chips are known as
programmable logic devices (PLDs).
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PLDs are available in a wide range of sizes. One of the sophisticated types of PLD S
known as Field Programmable Gate Array (FPGA).
Block diagram

Logic gates
and
Inputs Outputs
(Logic variables) Program1nable I (Logic functions)
Switches

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MEMORY DEVICE

Chapter at a Glance
Types of semiconductor memory:
RAM (Random Access Memory)
Static RAM
Dynamic RAM
Integratcd RAM
ROM (Rcad Only Memory)
PROM
EPROM
EEPROM
Static RAM: A memory capable of storing data indefinitely provided there no loss of
power is called Static Memory. SRAM cell consist ofa latch therefore the cell data is kent
long as the power is turned ON and re-fresh operation is not required. SRAM is mainly usek
for the cache memory in microprocessors, mainframe computer and memory in hand hell
devices due to high specd and low power conjunction.
The data storage cell ie. 1bit memory cell in static RAM arrays consists of a simple latch
circuit with two stable operating points (states).
Dynamic RAM: Dynamic RAMs are noted for high capacity, moderate access time and low
power consumption. Normally their memory cells are basiçally charge storage capacitor with
driver transistor. Dynamic RAMs require periodic charge refreshing to maintain storage of
data. Organization of DRAM is also similar to the static RAM.
ROM (Read only memory): ROM is essentially a memory (or storage) device in which:
fixed set of binary infomation is stored. Once a pattern is established for a ROM, it remains
fixed even when power is turned off and turmed on again i.e. this is a non-volatile memory
The concept of an ROM is extremely simple, user supplies address and ROM provides data
output of the word prewritten at the address.
ROMS are internally implemented using diodes, bipolar transistors of MOSFETs betwen
input and output lines.
PROMS: When ordered, PROM units contain all 0's (or all 1's) in every bit of the stored
words. Once it is programmed no change is possible.
EPROMs: In this, program can be erased and reprogrammed. Abit 0 or I is identified by
absence or presence of a charged gate.Charges on the gate are removed by UVlight.

Long Answer Type guestions

1. Design a combinational circuit using an 8x4 ROM that accepts a 3-bit number
and generates an output binary number equalto the square of the input number:
WBUT 2006, 2008, 2009]

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Answer:
B, B Bo Input output S SA S. S) S S,
) 0
0
1 4
1 9
16
1 25
36 1
49

Here output is square of the input.

i.e. if input = 0 output = 0
input = 1 output = 1
input = 2 Output = 4
input = 3 output = 9
SO on.
From table we sèe that
So Bo & S, =0
. ROM Programmable table can be written as
B, BË Bo Ss S S
0
1
1
1 1
1 0 ) 0
1 1 1
1 0
0

.:.8x 4 ROM is required for implementation.

S

B S
8x4
input B ROM S:
output
Bo

converter using PROM

Z. Design a BCD to 7-segment common anode display code WBUT 2007]
type PLD.
Answer: inputs. Figure I
Ihe decimal number 0 to 9 can be displayed by the binary coded decimal
Shows the display of decimal numbers 0to9 seven segment displays.

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5 7
I 2 3 4

a bcd e fg Fig. 1:7 Segment display of decimal numbers

be bright for decimal number 0
For example, the segments a, b, c, d, e, and f willshows
Similarly other numbers will be displayed. Table the different segments will be
bright for decimal number 0 to 9.

Table 1 Truth table for seven segment display

Decimal Inputs Outputs
f
B C b C
Number A 1 1
0 1 1
1 0 1 0 0
1
1 0 1
2 0
1 0
3 1
1 1
4 1
0 1
0
1 1 0
7 1
1 1 1 1 1 1

1 1
X
X
10 1: X X
1 X
11 1
X X
X
12 1
X X
13 1 1
X X X
14 1 1
X X X
15 1 1

3. Implement the BCD to Excess-3 code conversion using ROM. [WBUT 2010]
OR,
WBUT 2019]
Design a BCD to excess-3 code converter.

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Answer:

00 01 10 00

00
00

01
01
BCD Excess 3
b,b,hbo
10 (
0000 001|
0001 0100
0010 0101
0011 0110 bgb,
00 01 10 00
0100 011|
0101 1000 00 00
0110 1001 0
01 -

0 0
0111 1010
0
1000 1011 1

1001 1100 10 0
10

e = bbo t bbo
BCD
0 1: 2 3 4 5 6 7 8 9 10 1I 12 13 14 15
Code
b
o
b

bo
Excess 3
Code

De

4. a) Design a binary to BCD converter. WBUT 2019]

b) Design a binary to gray code converter.
Answer:
a) BCD is binary coded decimal number, where each digit of a decimal nmber is
respected by its equivalent binary number. That means, LSB of a decimal number is
represented by its equivalent binary number and similarly other higher significant bits of
decimal number are also represented by their equivalent binary numbers.

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Binary Code Decimal BCD Code

A B Number B, BÊ B B B
0 0
0 1 0 0
0 1 2
1 3
4 0
5 0
0 0
7
1 0
1 9 0
10 0
0 1 1
1 12 0 0
1 1 13 1
1 1 1 14 0 0
1 1 1 15 0 1 0
Fig: 4bit binary to bcd converter

b) The input to the 4-bit binary-to-Gray code converter circuit is a 4-bit binary and the
output is a 4-bit Gray code. There are 16possible combinations of 4-bit binary input an:
all of them are valid. Hence no don't cares. The 4-bit binary and the corresponding Gra,
code are shown in the conversion table (Figure la). Form the conversion table. We
observe that the expressions for the outputs G,,G,, G, and G, are as follows:
G, =Xm(8, 9, 10, 11, 12, 13, 14, 15)
G,=m(4, 5, 6, 7, 8,9, 10, 11)
G, =m(2. 3, 4, 5,10,11, 12, 13)
G=m(1,2, 5, 6,9, 10, 13, 14)
The K- maps for G,G,, G, , and G and their minimization are shown in Figure l.b. IN
minimal expressions for the output obtained from the K-map are:
G, = B,
G, = B,B, + B,B, = B, B,
G, = B,B, +B,B, = B, ®B,
G, = B,B, + B,B, = B, B,
So, the conversion can be achieved by using three X- OR gates as shown in the :
diagram below.

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4-bit binary 4-bit Gray

B B3 B, BË G4 G3 G2 G

0 0 0 1 0 1 B G

0 0 1 0 0 0 1 1
1 1 0 0 1 G
B
0 0 1 1
1 1 G
B;
0 1 0 1 1
1 1 1 1 0 G
B
1 0 1 1
1 0 1 1 1 0 1
Logic diagram
1 0 1 1 1 1
1 0 11 11 1
1 0 0 1 0 1I
1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1
1 1 1 1 0 0

Conversion table

4-bit binary-to-Gray code converter

B,B
B,B 10 00 01 11 10
00 01 11 B4B;
B,B; 0 1 3 2
1 3 2 00
00
7 6
4 5 01 1
01
12 3 15 14
5 14 11
12| 1
11
10
8
10 10
1

G= B,O B,
G, = B4 K-map for G
K-map for G4

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B,B B,B,
B,B; 00 01 11 10 B,B; 00 01
3
00 00
4 5 7 6 4 5
01 01 1

12 13 15 14| 12 13
11 11 15

10
10 10

G,=B, B, G, =B, B,
K-map for G K-map for G
(b) K-maps
Fig: 4-bit binary-to-Gray code converter
4.Write short notes on the following:
a) EPROM
b) EEPROM WBUT 2007, 2008]
Answer: WBUT 2009)
a) EPROM:
An EPROM is erasable and can be reprogrammed if an existing
is erased first. It uses an N-channel MOSFET with an isolated gateprogram in the memory
structure. The isolated
transistor gate has no electrical connections and can store an electrical connections and
can store an electrical charge for indefinite periods. The data bits are
presence or absence of stored gate charge. Types of EPROM are UVPROM and
represented by
EEPROM.

b) EEPROM:
EEPROMs are electrically erasable PROM. Change in contents of this memory unit is
made in milliseconds, which is much less than erasing of an EROM.
Erasing and
programming of E PROM is much easier as compared to EPROM. As the name suggests
in the memories, data can be written any number of times i.e.
they are
Reprogramming of ROM is possible only in MOS technology for erasingreprogrammable.
the contents of
the memory.
A major advantage offered by EEPROMs over EPROMs is the ability to
erase and reprogram individual words in the memory array.
electrically
Another advantage is that a complete EEPROM can be erased instant 10 ms about 30
minutes for an EPROM in external of ultraviolet light. An EEPROM can also be
programmed more rapidly it required only 10 ms programming pulse for each data word
as compared with 50 ms for an EPROM.

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A/D & D/A CONVERTER

T Chapter at a Glance
Analog to digital conversion: An analog to digital converter produces a digital output code
from
below
an analog input voltage after a certain amount of time. The block of ADC is shown
Block Diagram
+
Start Command
OpAmp Control
unit
Clock

+End of Conversion

DIA Register
Converter

Types of A/D Converter: There are several types of ADCnamely

1. Successive approximation ADC.
2. Flash type ADC
3. Up/Down Digital-ramp ADC.
4. Dual slope ADC.
5. Digital Ramp ADC.
6. Tracking ADC
Digital to analog converter: D/A conversion is the process of taking a value represented in
digital code and converting it to a voltage or constant which is proportional to the digital
value.
The analog output voltage Vo of an Nbit straight binary D/A converter is related to the digital
input by the equation
V, =K[2N='bN- +2bN-2 t...2.b, +2b,+b,]
K= proportionality factor.
b, =1ifn -th bit of digital input is I
=0 ifn - th bit of digital input is 0
Types of D/A Converter
1. Weighted -resistor D/A Converter
2. R-2R ladder DIA Converter.
3. The R/2nR DAC
4. 6-bit binary weighted DAC

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Very Short Type guestions

1. The fastest ADC is
a) dual siope
wBUT 2006, 20081
b)successive approximation
c) parallel comparator d) none of these
Answer: (b)
2. The resolution of an 8 bit A/D converter is
a) 0.62%
WBUTd) 1.25%
2007, 2008]
b)0.38% c) 0.39%
Answer: (c)
3. Which type of ADC (analog-to-digital converter) is slowest of all? [WBUT 20221
Answer:
Integrating type ADCis the slowest.
4. Which A/D converters are used for High speed operation?
Answer:
[WBUT 20221
High IF ADCs (10 MSPS to 125 MSPS), low IF ADCs (125 MSPS to 1 GSPS)
integrated receivers, and wideband ADCs (>1GSPS).
5. Which A/D converter is used for Hum rejection?
Answer:
WBUT 2023]
Voltage-to-frequency converter.
Short Answer Type Questions
1. Find the conversion time of a successive approximation A/D converter which
uses a 2 MHz clock and a 5-bit binary ladder containing 8V reference. What is the
conversion rate?
Answer:
[WBUT 2008, 2010]
Assume the A/D converter is 5-bit successive approximation type. The clock frequency =
2 MHz and clock time period T, =0.5Lus. The conversion time of 5-bit
successive
approximation A/D converter =5xT, =5x0.5us =2.5us
2. Define the following parameters of DACs: WBUT 2010]
a) Resolution b) Offset error
c) Monotonicity d) Settling error e) Percentage resolution
Answer:
a) Resolution -Normally given in bits.
Resolution indicates the smallest increment of its output corresponding to a l LSB
input code change. For example for 10 bit DAC, 2^10 =1024 codes, so the resolution
is 1/1024 of the output range.
b) Offset error - difference between the ideal and actual DAC output when zero digital
code applied to the input.
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c) Monotonicity - This refers to the abilitv of a DAC's analog output to move only in
the direction that the digital input moves (i.. if the input increases. the output
docsn't dip betore asserting the correct output. ) This characteristic is very important
for DACs used as a low frequency signal source or as a digitally programmable trim
element.
d) Scttling error - ldeally a DAC would instantaneously change its output value when
the digital input would change. However. in a real DAC it takes time for the DAC to
reach the actual expected output value.
e) Percentage resolution - Percentage resolution = resolution x 100%.

Long Answer Type Questions

1. Explain the principle of successive approximation A/D converter.
[WBUT 2005, 2011]
OR,
Explain the working of a successive approximation register (SAR) type ADC.
[WBUT 2012, 2014]
Answer:
The successive-approximation converter is one of the most widely used types of Analog
to Digital converter. It has a shorter conversion time than the other ADCs, with the
exception of the flash type. It has a fixed conversion time which is not dependent on the
value of the analog input.
Figure shows a block diagram of a 4-bit successive-approximation type ADC. It consists
of a DAC, an output register, a comparator, and control circuitry or logic. The basic
operation is as follows:
Analog VA Control ’CLK
input logic START
Comparator EOC

Output
register
MSB LSB

Binary output
DAC

Vax

Fig: The successive- approximation type ADC

The bits of the DAC are enabled one at a time, starting with the MSB. As each bit is
enabled, the comparator produces an output that indicates whether the analog input
voltage is greater or less than the output of the DAC. If the D/A output is greater than the
analog input, the comparator output is LOW, causing the bit in the control register to
reset. If the D/A output is greater than the analog input, the comparator output is HIGH,
and the bit is retained in the control register.

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The system enables the MSB first, then the next significant bit, and SO on.
bits of the DAC have been tried, the conversion cycle is complete. The After all the
each bit takes one clock cycle; so, the total conversion time for an jV-bit
willbe Nclock cycles.That is, t, for SAC = (N x l) clock cycles SA-protcessi
ype ngADC
of
The conversion time will be the same regardless of the value of K4. This is
control logic has to process cach bit to see whetheral is needed or not. because he
The method is best explained by an example. Let us assume that the output of the Da
ranges from 0 V to 15 V as its binary input ranges from 0000 to lI||, with
producing 0 V, and 0001 producing 1 V, and so on. Suppose that the unknown
input voltage. analog
V, is 10.3 V. On the first clock pulse, the output register is loaded with 1000, which:
converted by the DACto 8 V. The voltage comparator determines that 8 V is less tho
the analog input (10.3 V); so, the control logic retains that bit. On the next clock n
the control circuitry causes the output register to be loaded with 1100. The output of t
DAC is now 12 V, which the comparator determines as greater than the analog in
Therefore, the comparator output goes LOW. The control logic clears that bit; s0 th
output goes back to 1000. On the next clock pulse, the control circuitry causes the outs
register to be loaded with 1010. The output of the DAC is now 10 V, which th
comparator determines as less than the analog input. Thus, on the next clock pulse. the
control logic causes the output register to be loaded with 101 1. The output of the DACi:
now 11 V, which the comparator determines as greater than the analog input; so. the
control logic clears that bit. Now the output of the ADC is 1010, which is the nearest
integer value to the input (10.3 V). At this point, all of the register bits have been
processed, the conversion is complete and the control logic activates its HOC output to
signal that the digitalequivalent of K is now in the output register.
The advantages of the Successive approximation type ADC are
i) It is faster compared to other counter type ADC.
) The conversion time is fixed and short.
The constant conversion time allows the output to be synchronized so that it can be read
at known intervals.

2. Draw and explain the R/2R DA converter. [WBUT 2005)

OR,
Draw a neat diagram for a R-2R ladder type DAC. What is linearity error an offset
error in a DAC? [WBUT 2006, 2009]
OR,
Write short note on R-2R ladder DAC [WBUT 2011]
OR,
Explain the working of a R-2R Ladder type DAC with aneat circuit diagram.
[WBUT 2012, 2014)
OR,
What is advantage of R-2R type D/A converter over other type of D/A converter
[WBUT2016]

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 ANALOG& DIGITAL ELECTRONICS
Answer:
An R- 2R ladder DIA converter is shown in Fig, The inputs to the
resistor network are
applied through digitally controlled switches.
W
R

R
R R
2R 2R 2R 2R 2R2R

The output voltage,

R +

VRbot
|3R 23 3R 22

4b, +2b, +1b;l

For an Nbit D/A converter, output voltage can be determined and is given by,
Vo=(2b- +2N bN-2 t..12? b, +2' b, +2°bo)
where,
R, =3R and V, =2"V
Because of the widespread in the resistance values for N, the weighted resistor D/A
Converter is not suitable.
Linearity Error:
A linearity error is said to occur in the DAC if any deviation from the linearity is
observed from the ideal curve.
Offset error - It is the sdifference between the ideal and actual DAC output when zero
digital code applied to the input.
3. Describethe operation of successive approximation type AtoD converter. How
many clock pulses are required in worst case for conversion for an 8-bit SAR.
Define quantizing error for an ADC. [WBUT 2006, 2009, 2010]
Answer:
1" Part: Refer toQuestion No. lofLong Answer Type Questions.
2nd Part:
Conversion time of A/D converter is ( =2T, +2T,
V
where number of bits N=8
Analog input voltage V=5V
Reference voltage V, =10V

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Clock fiequeney f, =50kz

Then coson time N x2x -7.68ms
S0x 1000 10 S0 x 1000
lodetemine the maximun samnling trequency, considerl, =

Comeesion tine t=T, , -2T, +27,-2"T,

Jp S0x 1000
The maxinmum sampling frequency f<-= = 97.65Hz
I 27, 2 2'

3 Part:
Quantizing error:
The cror involved in quantization problem is called quatization error. Quantization
error due to the finiteresolution of ADCand is an unavoidable imperfection in alltypeof
ADC. The magniude of quantization error at the sampling instant is between zero and
halfof one LSB.

4. With the help of necessary circuit diagram explain the operation dual slope ADC.
[WBUT 2007)
Answer:
The block diagramof a dual - slope AWDConverter is shown in Fig. It has four major
blocks viz.
) an lntegrator
2) aComparator
3) a Binary Counter
4) a Switch driver

S:

R
Vo

EI N bit
Ck
Binary Counter
Clock pulses

BN By! B, B
-Nbit bin arv output
Dual slope A/D Converter
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 ANALOG &DIGITAL ELECTRONICS

The conversion process begins at t =0 with switch S,in position 0thereof connecting he
analog voltage V, to the input of the integrator. The integrator output,

This results in High Ve, thus enabling AND gate and clock pulses reach the clock
terminal of the Counter which was initially clear. counter counts from 00.....00 to
111... 11 when 2-1 clock pulses are applied. At the next clock pulse 2, counter is
cleared and becomes 1. This controls the state S, which moves to position I at lË thereoy
connecting -VR to the input of integrator. The output of integrator now starts to move in
positive direction. The counter continues to count until Vo <0. As soon as Vo goes
positive at T2, Ve goes low disabling AND gate. The counter will stop counting in
absence of clock pulses. Waveforms are shown in Fig.
Vo

,Rj(t -T)
Ve

T;

Waveforms of dual slope converter

The time T = 2^ Te, where Te= time period of clock pulses.

When switch S,is in position 1,output voltage,

T T
Vo =0 att=T,
:(T, -T)==NTc
VR
Let the count recorded in the counter be n at T,.

:.(T, -T) =nTç

VR
which gives
n=aN

Sooutput of counter is proportional to analog voltage V.a

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5. A4-bit
i)
binary ladder DIA converter with R= 10KN uses a reference of 5V. Find
the ideal scale factor in Vistep
i) the analog olp corresponding to the binary i/p 0110
ii) resolution in %
iv) full scale olp
v) the maximum deviation in volts from the best straight line in order to
meet
standard linearity. WBUT 2007]
Answer:
Assume Va =5V, and R, = R=10KQ
Scale factor K = Vp: R, 5 102y
2 3R 2 3x10 48
The output of a4-bit R-2R ladder circuit is
RE R,
2 -8,
3R +4b, +26, +l6,)
If 6, =0,b, =1,, =1,b, =0,
The output voltage V 5 10
38
3x10 8x0+4x1+2x1+lx0)=-v
48
Resolution
2-1 -x100 =6.67%(asn =4)
The full scale output voltage V 10

as b, =1,b, =1,b, =1
2
X
3x10 (8xl+4xl+2x]+lxi)=Py
48
The maximum deviation in
voltage from the best straight line in
order to meet standard
linearity =LSB = 48 21 5 5
96
6. Explain the
Answer: operation of a DIA converter.
[WBUT 2016]
Refer to Question No. 7(6) of
Long Answer Type Questions.
7. Write short
notes on the following:
a) A/D converter
b) DIA converter
c) A/D WBUT 20071]
Answer:
converter using successive approximation WBUT 2009]
a) A/D converter: WBUT 2017]
An analog to digital converter
voltage after a certain produces
amount of time. a digital
output code from an analog
The block of ADC is shown in
block diagram. input

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 ANALOG &DIGITALELECTRONICS
Block Diagram

OpAmp Control Start Command

unit
Clock

End of Conversion

DIA
Converter Register

Operations of Analog to Digital Converter

a) Atfirst, the operation is initiated by START
COMMAND pulse.
b) Clock control the rate and control unit modified certainly the binary
stored in register. number,
c) Binary number, stored in register is converted into analog voltage by DAC.
d) The comparator in the circuit compares the analog input of D/A converter with
analog input.
e) The control logic activates end of conversion signal, EOC when conversion is
complete.

Types of AD Converter
There are several types of ADC namely
1) Successive approximation ADC
2) Flash type ADC
3) Up/Down Digital-ramp ADC
4) Dual slope ADC
Dual-Slope ADC
The advantage of Dual-Slope ADC is in relatively low cost but it has one of the slowest
conversion times (typically 10 to 100 ms).
Basic operation involves linear charging and discharging of acapacitor using constant
current.
Major advantage of Dual Slope ADC is in low sensitivity to noise.
Flash typeADC
It is the highest speed ADC but it is much more circuiting then other type.
Normally a Flash type ADC remaining (2-1)comparator, 2 resistors and encoder logic.

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Successive
This type of Approximation ADC
ADC has more complex circuiting but it has a much shorter conversion ime.
in
Moreover it has a fixed value of conversion time that is not dependent on analop
value.

b) D/A converter:
Basically, D/A conversion is the process of taking a value represented in digital code ana
the digital value.
converting it to a voltage or constant which is proportional to is related to th
converter
The analog output voltage V, of an N bit straight binary D/A
digital input by the equation
Vo = K[2NbN- t 2NbN-2t....2b, + 2b, + bo
K = proportionality factor.
b, =l ifn - th bit of digital input is 1
= 0ifn - th bit of digital input is 0

Types of D/A Converter

1) Weighted - resistor D/A Converter
2) R - 2R ladder D/A Converter.

c) Successive approximation ADC:

The successive-approximation (SA) converter is one of the most widely used types of
Analog to Digital converter. It has a shorter conversion time than the other ADCs, with
the exception of the flash type. It also has a fixed conversion time which is not dependent
on the value of the analog input.
Figure below shows a block diagram of a 4-bit successive-approximation type ADC. It
consists of a DAC, an output register, a comparator, and control circuitry or logic. The
basic operation is as follows:
The bits of the DAC are enabled one at a time, starting with the MSB. As each bit is
enabled, the comparator produces an output that indicates whether the analog input
voltage is greater or less than the output of the DAC VM. If the D/A output is greater than
the analog input, the comparator output is LOW, causing the bit in the control register to
reset. If the D/A output is greater than the analog input, the comparator output is HIGH.
and the bit is retained in the control register.

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Analog
input
VA
Control ’CLK
logic + STARI
Comparator EOC

Output
register
MSB LSB

Binary output
DAC

VAX

Fig: The successive - approximation type ADC

The system enables the MSB first, then the next significant bit, and so on. After all the
bits of the DAC have been tried, the conversion cycle is complete.
The processing of each bit takes one clock cycle; so, the total conversion time for an jV
bit SA-type ADC will be Nclock cycles.That is, t, for SAC =(N x I) clock cycles
The conversion time will be the same regardless of the value of KA. This is because the
control logic has to process each bit to see whether a l is needed or not.
The method is best explained by an example. Let us assume that the output of the DAC
ranges from 0 V to 15 V as its binary input ranges from 0000 to 1111, with 0000
producing 0 V, and 0001 producing 1V, and so on. Suppose that the unknown analog
input voltage Va is 10.3 V. On the first clock pulse, the output register is loaded with
1000, which is converted by the DAC to 8 V. The voltage comparator determines that 8
Vis less than the analog input (10.3 V); so, the control logic retains that bit. On the next
1100. The
clock pulse, the control circuitry causes the output register to be loaded with
greater than the
output of the DAC is now 12 V, which the comparator determines as
logic clears that
analog input. Therefore, the comparator output goes LOW. The control
the control circuitry causes
bit; so, the output goes back to 1000. On the next clock pulse,
of the DAC is now 10V, which the
the output register to be loaded with 1010. The output
on the next clock pulse, the
comparator determines as less than the analog input. Thus, The output of the DAC is
with 101 1.
control logic causes the output register to be loaded
greater than the analog input; so, the
now 11 V, which the comparator determines as ADCis 1010, which is the nearest
control logic clears that bit. Now the output of the
value to the input (10.3V). At this point, all of the register bits have been
integer control logic activates its HOC output to
processed, the conversion is complete and the
output register.
signal that the digital equivalent of KA is now in the
approximation type ADC are
The advantages of theSuccessive
type ADC.
1) It is faster compared to other counter
short.
I1) The conversion time is fixed and so that it can be
constant conversion time allows the output to be synchronized
1) The
read at known intervals.
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LOGIC FAMILIES

T Chapter at a Glance
Allthese logic circuits are available in 1C modules and are divided into many families', Fack
family is classified by abbreviations that indicate the type of logic circuit used. They are of
the following
Resistance - Transistor Logic (RTL),
Diode Transistor Logic (DTL),
Transistor - Transistor Logic (TTL),
Emitter Coupled Logic (ECL),
Integrated - Injection Logic (I'c),
Complementary metal oxide semiconductor (CMOS) etc.
Bipolar Families: In Bipolar families there are three basic families.
DTL Diode-transistor logic
TTL Transistor-transistor logic
ECL Emitter-coupled logic
In DTL, diodes as well as transistors are used but now a days it is obsolete. In TTL, transistors
are used and it is the most popular family of SSI and MSI chips.
ECL, the emitter coupled logic is the fastest logic family which is used in high-speed
applications.
Characteristics of logic family:
Logic flexibility: Logic flexibility of a digital IC is a measure of its utility in meeting the
various system needs. The following factors are usualy included in the comparison of logic
flexibility of different digital ICs.
Wired logic Capability: Connection of gate output terminals together are using them directly
toperform additional logic function without any extra hardware.
Availability of complement output: This avoids the need for additional inverters.
Capability todrive non-standard loads such as long lines, lamps etc.
Inputvoutput facilities.
Ability to drive other logic family circuits.
Ability to have many types of gates in the same family.

Very Short Type Questions

1. The fastest logic family is WBUT 2006, 2009, 2013, 2017]
a) TTL b) CMOS c) RTL d) ECL
Answer: (d)

2. The fast logic family is WBUT 2009]

a) TTL b) ECL c) TRL d) DRL
Answer: (a)

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 ANALOG& DIGITAL ELECTRONICS
1 The digital logic family which has minimum power
dissipation is
a) TTL b) RTL WBUT 2012, 2015]
c) DTL d) CMOS
Answer: (d)

Long Answer Type guestions

4 Define the following terms in relation with
a) propagation delay b) fan-in
logic families: WBUT 2007]
c) fan-out
d) power dissipation e) floating inputs.
Answer:
a) Propagation delay: The delay in between input and output signals is called
propagation delay.
b) Fan in: Fan in is the maximum number of inputs for a logic
gate in a particular logic
family. This is limited due to delay time.
c) Fan out: The maximum number of standard logic inputs that an
output can drive
reliably is called Fan out.
d) Power Dissipation: It is the supplied power required to operate the gate. This
parameter is expressed in milliwatts (mW) and represents the actual power dissipated in
the gate.

e) Floating Inputs: Floating inputs of an IC used when a-pin is left with no connection.
Depending on the application, often inputs or outputs is not used. In such scenario, it is a
good practice and in the case of CMOS devices necesary, to tie the unused to logic high
or low using pull up or down registers. The choice of tying to high or low will be dictated
by the application and the 1C's datasheet will offer guidance.
2. Define the following terms related to digital ICs: WBUT 2008]
i) Noise Margin ii) Propagation delay - t pLH, t PHL
ii) Set up time iv) Hold time.
Answer:
i) A measure of noise which can be tolerated by a logic circuit. without impairing its
normal operation.
i) Delay measured to the transition from low to high and high to low respectively
known as PLH and t PHL
ii) It is the minimum time required to maintain a constant voltage levels (data) at the
excitation inputs of the fIf device prior to the triggering edge of the clock pulse in
order for the levels to be reliably clocked into the f/f.
iv) It is the minimum time for which the voltage level (data) at the excitation inputs
must remain constant of the triggering edge of the clock pulse in order for the
levels to be reliable clocked into the flip flop.
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3. Write short notes on the following: WBUT 2008, 20151

a) CMOS Logic
b) CMOS Logic family
c) TTL family
WBUTwBUT
2012, 2011)
2017
Answer:
a) CMOS Logic: faster than any
PMOS and NMOS devices in the same circuit. It is other
It uses both
advantages are offset somewhat by inore
logic, consumes lesspower than these
fabrication and lower packing density. It can be operated at hiok
complexity of IC
voltages resulting inimproved noise immunity. CMOS technology is used to Construct
small medium and large scale.

b)CMOS logic family: channel MOSFETs in the same circuit

logic family uses both P and N
The CMOS family i
several advantages over the PMOS and NMOS families. The CMOS
realize MOS families. These advantages are offset
faster andconsumes less power than the other fabrication process and a lower packing
somewhat by the increased complexity of the IC
voltages resulting in improved nojse
density. The CMOS can be operated at higher
immunity. It is widely used for general-purpose logic circuitry. The CMOS technologyof
large scale ICs for a wide variety
has been used to construct small, medium and
applications ranging from general-purpose logic to microprocessors. Because of its
for applications in watches and
extremely small power consumption, it is useful MOS in applications
calculators. The CMOS, however, cannot yet compete with compete with MOS in
yet
requiring the utmost in LSI. The CMOS, however, cannot high input resistance. Thus.
applications requiring the utmost in LSI. The CMOS has very
therefore, its fan-out is.very high.
it draws almost zero current from the driving gate and of NMOS (100 kO). Hence, it is
Its output resistance is small(1 k2) compared to that load. In CMOS, there
faster than NMOS. The speed of CMOS decreases with increase in
and ground, because of the
is always a very high resistance between the Vn terminal
noise
MOSFET in the current path. Hence, its power consumption is very low. The
and it is 30% of Vn.
margin of CMOS is the same in both the LOW and HIGH states
Indicating that noise margin increases with an increase in power supply voltage. So n
noisy environments, CMOS with large Vpn is preferred. However, an increase in Vp
results in the corresponding increase in P,. The CMOS loses some of its advantages at
high frequencies.

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c) TTL family:
assland MSI devices, TTL amily members are widely used.
Oniginal TTL logic family uses NAND circuit at the building block. In the next phase
schotky transistorS were incorporated to improve its
speed and 74 series is improved 74S series but
propagation delay is being reduced by a factor 3 at R: R
the expense of doubling power dissipation. Totem
Pole
After that delay power product is improved over 74
and 74S series and the series converts into 74LS
series. Preferably Advanced Low power Schotky D
series is denoted by 74 ALS.
74ALS series is actually a derivative of 74LS series {Q:
whose design is used to minimize power R
distribution. Since propagation delay is reduced
here.This series has best delay power product of any
logic family. Power consumption is also reduced Fig: Totem Pole output
become its resistance values are increased and circuit diagram
current is reduced here. Speed of the device also
increases before the inclusion of additional active elements such as emitter followers.
Finally improved processing techniques permit fabrication of smaller devices.
Description of the cireuit
In the circuit of two outputs TTL NAND gate, transistor g sits above transistor l.
Both of the transistors are connected in totem pole fashion. Both cannot ON or OFF
simultaneously but at any one of the turn will be contracting.
If , is ON, O, must be ON because drive of O, comes from ,. V:(sat)=0.3V So,
biased.
V, = 0.7V +0.3V = |V,For , to be ON, in base emitter junction must be forward
When , is considered diode has to be ON for , to be ON simultaneously. So the base
volume of , must be V, = |+.7 =1.7V for it to be ON. Since V,B is only 1 V when O,
is ON. cannot be ON. So 0 & 0, do not conduct simultaneously.
Advantages of totem Pole:
law.
1. The inclusion of diode and ,, keeps circuit Power dissipation
2. In the output high state, acts as an emitter follows with low output impedence.
waveforms at
This action is referred as active pull up and it points very fast rise time
TTL output.
Disadvantages:
I. Transistor: transistor logic suffer from internally generated current transients of
Totem-pole condition.
output of' a,number of gates cannot be
L. Totem pole output cannot be wireANDed i.e.
tied together to obtain AND operation of those output.
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QUESTION 2017
Group-A
(Multiple Choice Type Qüestions)
1.Choose the correct alternatives for any ten of the following:
i) Parity generator is used for b) amplitude detection
a) error detection
Vd) none of these
c) noise detection

i) Synchronous cicuits change their state with d)

a) input Vb) clock pulse c) output none of these
i)The efficiency of Class Aamplifier is c) 0.25 d) 0.1
Va)0.5 b) 1
what other logic gates?
V) Exclusive-OR (XOR) logic gates can be constructed from
a) OR gates only Vb) AND gates,OR gates and NOT gates
d) none of these
c) OR gates and NOT gates

) if (s4),, =(X),.then the value of Xis

a) 123 b) 312 c) 213 d) 132

vi) A+A'B + 4'B'C'+AB'CD+......... equals.

a) A+B+C+D b) A'+B'+C'+D' Vc) 1 d) 0

vi) The minimum number of NAND gates required to implement an EX-OR gate is
a) 2 b) 3 /) 4 d) 5

vii) The net phase shift of Wien-bridge oscillator around the loop is
a) 90° b) 180° c) zero a) 360°

ix) [AB'(C+ BD) + AB'}C is

a) AB' b) BC Vc) B'C d) AB

x) If the Q of a single stage single turned amplifier is doubled, then bandwidth will
Va) remain the same b) become half
c) become double d) become four imes

xi) Fastest logic gate family is

a) CMOS Vb) ECL c) TTL d) RTL

xii) The number of flip-flops required to design a Mod 10 counter is

a) 3 Vb) 4 c) 5 d) 6

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Group- B
(Short Answer Type
Implement the function of Dflip-flop using J-K flip-flop.Questions)
Soe Topic: FLIP-FLOP, Short Answer Type Question No. 7.

3. Simplify the following functions using K-map

a) F(4, B, C,D)=(7,9,10,11, 12,13, 14, 15)
b) F(4, B, C,D)=z,(0,2, 3, 6,7) +n, (8,10, 11,15)
See Topic: KARNAUGH MAP, Short Answer Type Ouestion No. 7.

A Design a 5:32 decoder using 2:4 and 3:8 decoders.

See Topic: COMBINATIONAL CIRCUITS, Short Answer Type Question No. 5
5. Draw and explain the operation of monostable multivitbrator using 555 timer.
See Topic: AMPLIFIERS, Short Answer Type Question No. 3.

6. Describe the working of S-R flipflop using truth table, logic diagram and excitation
See Topic: FLIP-FLOP, Short Answer Type Question No. 8.
table.

Group-C
(Long Answer Type Questions)
7.a) Design a MOD 4 synchronous counter using J-K flip-flops and implement it.
b) Implement a full subtractor using demultiplexer.
c) Design a full adder using two half,adders.
a) See Topic: REGISTER & COUNTER, Long Answer Type Question No. 14.
b) See Topic: ARITHMETIC CIRCUITS, LongAnswer Type Question No. 7.
c) See Topic: ARITHMETIC CIRCUITS, Short Answer Type Question No. 4.

8. a) Design asynchronous 3-bit up-down counter using J-K flip-flop which counts up when external
signal M =1 and cOunts down when M =0.
b)With a neat circuit diagram, explain the operation of a 4-it Johnson counter implemented using
Dflip-flop.
a) See Topic: REGISTER & COUNTER, Long Answer Type Question No. 7.
b) See Topic: REGISTER &COUNTER, Long Answer Type Question No. 10.
9. a) Dravw and explain the master-slave J-K flip-flop using NAND gate.
b) Write down the excitation table and convert SR to JK flip-flop.
c) Describe the operation of abi-directional universal shift register (with parallel load) with a neat
diagram.
a) See Topic: FLIP-FLOP,Short Answer Type Question No. 1.
b) See Topic: FLIP-FLOP, Long Answer Type Question No. 3.
c) See Topic: REGISTER & COUNTER, Short Answer Type Question No. 4.

10. a) What are the conditions necessary for the generation of oscillation?
D) Explain the operation of a Wien-bridge oscillator using Op-Amp with a circuit diagram.
C) Derive an equation for its frequency of oscillation.
d) What is Barkhausen criterion?
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Question No. 2.
a), b) &c) See Topic: AMPLIFIERS, Long Answer Type No. 5(2nd part).
See Topic: AMPLIFIERS, Short Answer Type Question
d)

11. Write short notes on any three of the following:

a) Parallel input serial output shift register
b) Decimal to BCD encoder
c) A/D converter using successive approximation
d) Asynchronous ripple counter
e) TTL family.
Answer Type Question No. 17(d).
a) See Topic: REGISTER &COUNTER, Long
Long Answer Type Question No. 16(h).
b) See Topic: COMBINATIONAL CIRCUITS,
c) See Topic: A/D &D/A Converter, Long Answer Type Question No. 7(c).
Answer Type Question No. 17(e).
d) See Topic: REGISTER & COUNTER, Long
Question No. 3(c).
e) See Topic: LOGIC FAMILIES, Long Answer Type

QUESTION 2018
Group-A
(Multiple Choice Type Questions)
following:
1. Choose the correct alternatives for any ten of the
i) Cross-over distortion ocCurs in
c) Class Camplifier d) Push pull amplifier
a) ClassA amplifier Vb) Class AB amplifier

as an amplifier?
ii) Which of the following mode of BJT can be used d) None of these
a) CB b) CC Vc) CE

i) Simplify A'B + A+ BC
a) A+ BC b)A+ B c) A' + BC d) None of these

iv) Anexample of weighted code is d) Allof these

a) 2421 b)GRAY c) XS3
Answer: NONE OF THESE

v) HoW many 1's are present in the binary representation of decimal number
(3×512+7x64+5x8+3)=?
a) 8 b) 9 c) 10 d) 11

vi) Master-slave configuration is used in flip-flop to

a) increase its clocking rate b) reduce power dissipation
Vc) eliminate race around condition d) improve its reliability

vii) A pure sine wave output is possible with

a) Hartley oscillators b) Wien-bridge oscillators
c) RCphase shift oscillators d) Colpitt oscillators

vii) To avoid the thermal runaway, q point should be such that it satisfied
a) Vo = Ve2 b) V < V2 Vc) Vee >= VJ2 d) Voe < V4

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ix) The output pulse wath for a monostable multivibrator using IC 555 where external res1stance
andcapacitance are 20 kO and 0.1fIF is
a) 2.1s b) 2 ms c) 2.5 ms /d) 22 us
x) Multivibrators
Va) generate square wave b) Convert sine to square wave
c) convert triangular to sine wave d) convert triangular to square wave
xi) A32:1 MUX can be designed using
Va) two 16:1 MUXs and one two input OR gate
b) two 16:1 MUXs and one two input AND gate
c) two 16:1 MUXs and 2 two input OR gate
d) two 16:1 MUXs only
Group-B
(Short Answer Type Questions)
2. What do you mean by race around condition? How this problem is solved by using master-slave
flip-flop?
See Topic: FLIP - FLOP, Short Ansiwer Type Question No. 6.

3. a) Difference between sequentialcircuits and combinational circuits.

b) What is triggering? How many types of triggering are there in sequential circuits?
See Topic: FLIP - FLOP, Short Answer Type Question No. 9.
4.Design NAND and NOR logic gate using COMS technology.
See Topic: COMBINATIONAL CIRCUITs, Short Answer Type Question No. 6.

5. Obtain the minimal POS expression of the following function and implement the same usingonly
NOR gates.
F(A, B, C, D) =Zm(1, 4, 7, 8, 9, 11) +Zd(0,3,5)
See Topic: KARNAUGH MAP, Short Answer Type Question No. 8.

6.Draw and explain Schmitt trigger circuit using 555 timer.

See Topic: AMPLIFIERS, Short Answer Type Question No. 8.
Group-C
(Long Answer Type Questions).
7. a) Design a logic diagram, using logic gates, for addition/subtraction circuit, using a control
variable Psuch that this operates as fulladder when P =0, and fullsubtractor for P =1.
b) Implement the following function using 4:1 MUX only. F=m(0,2,3,6,8,9, 12, 14).
a)See Topic: ARITHMETIC CIRCUITS, Long Answer Type Question No. 4.
b) See Topic: COMBINATIONAL CIRCUITS, Long Answer Type Question No. 1.
8. a) What are the possible classification of power amplifiers depending on the position of their
Operating point?
b) For a Transformer coupled class A amplifiers draw the AC load line. Hence calculate the
maximum value of efficiency.
©) For class B push-pull amplifier calculate the maximum value of efficiency.

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See Tepie: AMPLIFIERS, Long Answer Type Question No. 8(a), (b) &(¢).
9. a) Draw and explain the 4-bit bi-directional Shift Register using mode
logic zero then left shift an right shift for Mis logic one.
control (), when t
b) What are the facilities available in universal shift register? How a
4-bít universal shift register.
be realized using multiplexers and flip-flops?
See Topic: REGISTER &COUNTER, Long Answer Type Question No. 15(a) &
(b).
10. For a synchronous counter with
sequence:
a) 26531’0’2
Give present state/next state table.
b) Wite state transition table using D
c) Simpify and realize the circuit. Drawflip-flops.
the state diagram.
d) Justify where the design cOunter will go in lockout condition or not.
e) What should be the corrective
design process to avoid the lockout
See Topic: REGISTER &
COUNTER, Long Answer Type Question No. 16.Ccondition?
11.Write short notes on any three of
the following:
a) Grey code
b) Johnson counter
c) Even parity generator and
d) Phase shift oscillator
checker
e) Current shunt
a) See Topic: feedback
b)See Topic: CODES, Long Answer Type Question No. 1.
c) See Topic: REGISTER &COUNTER, Long
Answer Type Question No. 1.
d) See Topic:COMBINATIONAL CIRCUITS, Long Answer Type Question No.
e) See Topic: AMPLIFIERS, Long Answer Type Question No. 12(d). 16(b).
AMPLIFIERS, Answer Type Question No. 12(e).
Long

QUESTION 2019
Group- A
1. Choose the
correct (Multiple Choice
for any ten of theType Questions)
i) The alternatives
number XOR gates required
of following:
for the
a) 2
b) 3 conversion of 11011 to is equivalent Gray Code is
c) 5
i) An example of Yd) 4
a) Excess-3 weighted code is
b) ASCI
üi) The output of a c) Hamming code
a) NAND or logic gate is '1' when all its /p Vd) 8421
c) AND or XOR gate are at logic '0'. The
XNOR gate b) NOR or XORgate is either
iv) How is a d) NOR Oor gate
conducting diode biased?
Va) Forward
XNOR gate
b) Inverse
c) Poorly
d) Reverse

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 ANALOG& DIGITAL ELECIRONICS
v) The current gain of a p-n-p transistor is
a) the negative of the n-p-n current gain
b) the collector current divided by the emitter current
c) near zero
Vd) none of these

v) The control terminal in a BJT transistor is

Va) The collector b) The base c) The emitter d) none of these
vii) For the operation as an amplifier the base of an n-p-n
transistor must be
Va) +ve with respective to emitter b) -ve with respect to the emitter
c)0V
d) +ve with respect to collector
yii) The input resistance of a common base amplifier is
Va) very low b) very high c) same as CE d) same as CC

ix) Acertain common-emitter amplifier has voltage gain 100. If the emitter bypass capacitor is
removed,
a) circuit will become unstable b) voltage gain will decrease
c) voltage gain will increase d) q-point willshift
x) AJFET differs from BJT mainly because of
a) power rate b) high frequency performance
c) higher input impedance d) higher speed

xi) BJT in CC mode can be used as

a) Amplifier b) Buffer c) Intermediate stage

Group- B
(Short Answer Type Questions)
2. Carry out the following operation in binary using 1's complement arithmetic:
8-9=-1
See Topic: NUMBER SYSTEMS, Short Answer Type Question No. 3.

3. Realize the following expression using K-map and implement the simplified expression using
NOR gates only:
F (A, B, C, D) = 2 (0, 1, 4, 6, 7, 10, 11, 12, 13, 15) + d (2, 5, 9, 14)
See Topic: KARNAUGH MAP, Long Answer Type Question No. 1.
4. Explain the working principle of 4:1 MUX with a truth table. Realize it using NAND gates only.
See Topic: COMBINATIONAL CIRCUITS, Short Answer Type Question No. 7.

5. Explain the working principle of 1:4 DEMUX with truth table. Realize it using basic gates.
See Topic: COMBINATIONAL CIRCUITS, Short Answer Type Question No. 8.

6. Implement ful-adder using 3x8 decoder with al active-low outputs and one additional logic gate
if required.
See Topic: COMBINATIONAL CIRCUITS, Long Answer Type Question No. 2,.
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Group -C
(Long Answer Type Questions)
7. a) What is the main difference between alatch and aflip-flop? Explain the working of
flop. S-R flip-
D)What is thedisadvantage of S-R flip-flop? How can it be overcome? Explain.
c) What do you mean by race around condition? How is the problem solved by using
flip-flop?
a) 1* Part: See Topic: FLIP-FLOP, Short Answer Type Question No. 3.
master-slave
Z Part: See Topic: FLIP-FLOP,Short Answer Type Question No8.
b) See Topic: FLIP-FLOP, Short Answer Type Question No. 10.
c) See Topic: FLIP-FLOP,Short Answer Type Question No. 6.

8. a) Design a binary to BCD

converter.
b) Design a binary to gray code
c) Design a BCD to excess-3 codeconverter.
converter.
a) b) See Topic: MEMORY DEVICE, Long Answer Type Question No. 4(a) & (b).
C) See Topic: MEMORY DEVICE, Long Answer Type Question No. 3.

9. a) Design an 8 to 3 line encoder.

b) Design a 2 to 4 line decoder.
c) Implement the following using 3 to 8 line decoder. Use active
low decoder outputs:
YO (A, B, C) =Em(0, 1, 2, 4).
a) & b) See Topic:
COMBINATIONAL CIRCUITS, Long Answer Type
c) See Topic: ARITHMETICCIRCUITS, Short Question No. 9(a) & (b).
Answer Type Question No. 6.
10. Using IC 555 explain the operation of
pulse. Monostable MV. Cálculate the width of the generated
1" Part: See Topic: AMPLIFIERS, Short
2nd part: See Topic: AMPLIFIERS, Short Answer Type Question No.3.
Answer Type Question No. 9.
11. Draw the circuit diagram of Schmitt
expression for Hysteresis voltage. Trigger. Calculate duty Cycle. Draw H loop and find the
1st Part: See Topic:
AMPLIFIERS, Short Answer Type Question No., 4.
2nd & 3rd Part: See Topic:
AMPLIFIERS, Long Answer Type Questiou No. 9.
QUESTION2022
Group-A
1. Answer any ten of the following: (Very Short Type Questions)
i) In the astable amplifier, up to what voltage the
See Topic: AMPLIFIERS, Very Short Type Question capacitor charyes?
No. S0.
N The state 1110 is a valid [tate in
See Topic: CODES, Very Short Type8-4-2-1 Binary Coded Decimal counter. State True / False.
Question No. 8.
iii) A4-bit mod 16 ripple
what will be the m counter uses JK flip-flop, if the
maximum clock frequency (in MHz)
that propagation flopis 100 ns.
can be useddelay
of each flip
in the
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 ANALOG& DIGITAL ELECTRONICS

ee Tonic: REGISTER & COUNTER, Very Short Type Question No. 10.

v In Asynchronous circuit Race condition always arises. State True / False.

See Topic: FLIP- FLOP,Very Short Type Question No. 10.

VWhat is the minimum number of NAND gates required to design a Fulladder circuit?
See Topic: COMMBINATIONAL CIRCUITS,Very Short Type Question No. 9.
V) Which type of ADC (analog-to-digitalconverter) is slowest of all?
See Topic: A/D&DIA CONVERTER,Very Short Type Question No. 3.

vii) Which AD converters are used for High speed operation?

See Topic: AD & DIA CONVERTER, Very Short Type Question No. 4.

vi) The input of a Schmitt Trigger is sawtooth wave, what will be shape of the output?
See Topic: AMPLIFIERS, Very Short Type Question No. 51.

ix) The output Yof the logic circuit given below is

X -

See Topic: COMBINATIONAL CIRCUITS, Very Short Type Question No. 11.

of 1
x) Five JK flip-flops are cascaded to form circuit shown in figure. Clock pulses at a frequency
MHz are applied as shown. What will be the frequency (in kHz) of the waveform atQ3?

Q3 1 J2 Q2 QI Q0
Q4
clk
>clk clk > clk
KO
14K3 K2

clock

See Topic: FLIP - FLOP, Very Short Type Question No. 11.

system, find X
X) If (212), -(23),. , where X is the base of the number
10.
See Topic: NUMBER SYSTEMS, Very Short Type Question No.

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xi) Amod-n counler using a synchronous bìnary up-COunter with synchronous clear input is
in the figure. What will be the value of n? shown
4-Bit Binary -Qa
Counter
Qn
CLOCK -> CLK
Q Qc

CLEAR

See Topic: REGISTER &COUNTER, Very Short Type Question No. 11.

Group- B
(Short Answer Type Question)
2. Perform conversion of Dflip-flop to J-K
flip-flop.
See Topic: FLIP - FLOP, Short Answer Type Question No. 12.
3. Perform conversion of S-R flip-flop to J-K
See Topic: FLIP - FLOP, Short Answer Type
flip-flop.
Question No. 13.
4. Design a 5 to 32 decoder using 3 to 8
See Topic:
decoder and 2 to 4decoder.
COMBINATIONAL CIRCUITS, Short Answer Type Question No. 9.
5. Figure shows a 4 to 1 MUX to be
used to implement the sum. S of a 1-bit full
P and Qand the carry input Cin. adder with input bits
Find the combinations of inputs to I,
which will realize the sum S. I,,I, and I, of the MUX

4:1
MUX

S. S.

P O
See Topic:
COMBINATIONAL CIRCUITS, Short Answer Type Question No. 10.
 ANALOG& DIGITAL ELECTRONICS

e Eind the oscillation frequency of the phase shift oscillator whenR=10k0 and C =6.5 nf.

C
R R RR

H
See Topic: AMPLIFIERS, Short Answer Type Question No. 10.

Group-C
(Long Answer Type Question)
7.a) In the given MUX theoutput is F= AXOR B.What will be the inputs I,,,,I,, I,?

I, 4x1
MUX

1,

A B
See Topic: COMBINATIONAL CIRCUITS, Long Answer Type Question No. 10.

b)Check the following digital circuit. What will be the equivalent logic gate of the whole circuit?

SeeTopic: LOGIC GATES, Long Answer Type Question No. 1.a).

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c) What will be minimised output F of the circuit.

See Topic: LOGIC GATES, Long Answer Type Qucstion No. 1.b).

8. a) Define voltage, cürrent and power amplifier.

b)Write the different classes of power
amplifier.
c) Draw the circuit diagram of a class B push pull transistor amplifier. Explain the operation.
d) Derive the maximum efficiency of a class B
See Topic: amplifier.
AMPLIFIERS, Long Answer Type Question No. 10.
9. a) To realize the given truth table from the
of A and B. circuit shown in the figure, find the input to Jin terme

Combinational
logic circuit
B
K

clk

B
0
2,
0 1 1

See Topic:
COMBINATIONAL CIRCUITS, Long Answer Type Question No. 11.

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 ANALOG& DIGIIAL ELECTRONICS
b) What is the equivalent flip-flop of the digital circuit given below, explain with reason

CLK

See Topic: FLIP - FLOP, Long Answer Type Question No. 9.a).

c) The clock frequency applied to the digital circuit shown in the figure below is 1kHz. If the initial
state of the output of the flip-flop is 0, what will be the frequency of the output waveform Q in kHz?

clk

See Topic: FLIP - FLOP,Long Answer Type Question No. 9.b).

10. a) Find the simplified form of the Boolean expression Y,where
Y=(·BC+D)(4·D +B'C')
See Topic: BOOLEAN ALGEBRA, Long Answer Type Question No. 1.

b) The output F of decoder can be realised with best logic gates. Find out the Boolean expression.

A
(BASE)
3 to 8
B
Decoder
y
F
C

See Topic: COMBINATIONAL CIRCUITS, Long Answer Type Question No. 12.

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IC 555 timer.
11 a) Draw the circuit diagram of a Astable Multivibrator using
b) Derive the expression duty cycle and frequency of osCillatio.
c) Explain why this is called Free running oscillator.
See Topic: AMPLIFIERS, Long Answer ype Question N0. II.
QUESTION 2023
Group -A
Questions)
(V'ery Short Type
1. Answer any ten of the following: in Fig.
minimal product-of-sums function described by the K-map given
}VWhat wil be the
AB
00 01

Short Answer Type Question No. 5.

See Topic: KARNAUGH MAP, Very
high)
amplifier according to their efficiency (low to
i) Arrange the Classes of power
Class A, Class B. Class C. Class AB
Answer Type Question No. 52.
See Topic: AMPLIFIERS, V'ery Short

figure given below:

ii) What will be the output of the logic gate in

See Topic: L0GIC GATES, Very Short Answer Tvpe Question No. 10.

iv) In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays lh8
present input condition is: P=Q="0". If the input condition is changed simultaneousiy to
P=Q="]". what will be the outputs Xand Ynow?

See Topic: LOGIC GATES, V'ery Short

D
.Answer Tvpe Question No. 1I.
v) lf the input to the digital circuit (in the figure) consisting of a cascade of 20 XOR-gates is X Wha'
will be the output Y?

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 ANALOG& DIGILAL LLECIRO\ICS

See Topic: LOGIC GATES, V'ery Short Ansner Type Qucstion No. 12.

v) The circuit of following figure shows an IC 555 Timer connected as an Astable multivibrator Tne
value of the capacitor C is 10nF. Find the values of the resistors R. and R. for a frequency of
10kHz and a duty cycle of 0.75 for the output voltage.

T
R

555 Timer

Discharge

Question No. 53.

See Topic: AMPLIFIERS, Verv Short Answer Type

required to realize a 4 to 1 multiplexer?

vi) What will be the minimum number of 2 to 1multiplexers
Answer Type Question No. 12.
Sce Topic: COMBINATIONAL CIRCUTS, Very Short

race around willoccur or not

vi) Consider the given circuit. Explain whether, the
AO

Clk o

Bo

\o. 12.
See-Iopic: FLIP- FLOP, Very Short.Answ er Type Question

IX) VWhich A/D converter is used for Hum rejection?

Question No. 5.
See Topic: A/D & D/A CONVERTER, Very Short Answer Iype

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) The a c outcut pOwer of a Class B push-pull power ampl fier is 10 watt Wha: wll De
pui power drawn from power supplywhen the efficiency of the is maximun
See lopic: |\|PHL RS, erv Short.Ansuer Tpe Question \o. 54,

N)What s cctal value of2) ?

Sec bopie: \I\BRS}SIMUS. 1ery Short \nswer I'vpe Question \o. I1.
x) Statement 1 Asiable MJItivibrator can be used for gererating Square Wave
S:atement 2 Bistable Mulvibrator can be usec for storing binary informatior.
Please state whether both tne statements are true or false.
See lopic: AMPLIEERS. Verv Short .Answer T pe Question No. 55.

Group- B
(Short Answer Ivpe Question)
2 In aJK flip-flop. we have J=Q' and K=1 (see
and then clocked for 6 pulses. What will be the
figure). Assuming the fp-flop was initiaily c'egrs
seguence at the Q Output?

CLK

See Topic: FLIP - FLOP:Short

Ansmer Type Question No. 13.
3 Derive the maximum eficency of a classB
See Topic: amplifter
A\PLIFIERS. Short.Answ er Tvpe Question No. I1.
4 Explain the
operation of trarsformercoupled Class A
See lopic:
A\PLIFIERS. Short .Answer amplifier.
Tv pe Question No. 12.
5 Find out what wili be tne
modulus of this Counter?

Sce Iopic:
REEGISTER & 0UVTLR, Short \nsuer Ipe
Question \o. 5.
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 ANALOG& DIGILAL ELEC IiROVICS
ADesian a Full subtractor (X. Y and Borrow) with 4 : 1 MUX
See Topic: COMMBINATIONAL. CIRUITS, Short Ansuer Type Question No. I1.

Group- C
(l.ong Answer Type Questions)
7 2) Find the out expression for the Karnaugh Miap shown below:
CD
AB 00 01 11 10
o
00 o
01 1

11 1 1

10

See Topic: KARNAUGH MAP, Long Answer Type Question No. 5.

b) Find the out F in terms of A and B

A
B
See Topic: (OMBINATIONAL CIRCTTS, Long.Answer Type Question No. 13.

c) Find the output expression F for the following Karnaugh Map and realiseit with logic gates
AB
00 01 11 10
1 1

See T'opic: KARNA¯GH MAP, Long Answer T'ype Question No. 6.

in figure
Þa) A diçital circuit which compares two numbers AsApA-A (A) B3B,B-B (B) is shown
Finc the pair A. B to get output Y = 0

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3 A A
B. A. 3 A:

Sec Topic: COMBINATIONAL CIRCUTS, Long Answer Iype Question No. 14.a).

b) Consider the multiplexer based logic circuit shown in the figure. Find the Boolean functicns 2re
realized by the circuit
W

MUX

MUX

Sec Topi: (0\MBINATIONAL CIRCUTS, Long Answer Tvpe QuestionSjo. 14.b).

c) A 4 bit modulo-16 ripple
counter uses JK
Find the maximum clock frequency that can beflip-flops. If the propagation delay of each FF is 50ns.
used in this cOunter.
See Topic: REGISTER &
COUNTER. I.ong Answer Type Question No. 17.
9. a) Find the output Z in terms of X
and Y

4|MUX

See Topic:
(OMBINATIOVALL CIRCTTS, Long Answer Tvpe Question No. 15.a).

A&)-214
 A\ALOG &DIGIILAL ELECTRONICS

ABoolean functon ( . B.C.D) z(1.5.12.15) s to be inpiemented using an 8zi

multiplexer (A is MSB) The inputs ABC are connected to the select inputs S.SS of the
multiplexer respectively

(A. B.C D)

7
S: S S

ABC

Fnd the correct inputs to pins 0, 1, 2, 3, 4, 5, 6, 7 in order

See Topic: (OMBINATIONAL CIRCUTS, Long Answer Type Question No. 15.b).

10 a) A3-bit gray counter is used to control the output of the multiplexer as shown in the Figure
A is MSB and Ac is LSB). The initial state of the counter is 000,. The output is pulled high. Find
the sequence of the output of the circuit.

A;

3-bit gray A
counter

A +5V

S.

MUN
CLK Output

Vo. 18.
See Topic: REGISTER& COUNTER, Long Answ er Type Question
Used to implement a 3-variable Boolean
b) A 3 line to 8 line decoder, with active low outputs, is
function as shown in figure.
implemented in Product of Sum' form
Find the simplified form of Boolean function F(A. B.C)

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;Decodet

7b

Sce Topic: COMBINATIONAL CIRCITS, Long Answer Type Question No. 15.b).

11. a) Digital input signals A. B. C with A as the MSB and Cas the LSB are used to realize the
Boolean function F=n0- m2+ n3+ )5- m7. where mi denotes the ith minterm. In
addition, F h¡s a don't care for ml. Find the simplified expression for F
b) Find the prime implicants in the sum of products function
(X.).Z)=(2.3.4.5).
See Topic: BOOLEAN ALGEBRA, Long Answer Type
Question No. 2.

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