Chip Design
Professor: Sci.D., Professor
Vazgen Melikyan
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Chip Design
Lecture - 3
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Course Overview
Introduction to Chip Design Physical Data Preparation
1 lecture 3 lectures
IC Manufacturing Process Liberty Format
1 lecture 2 lectures
Phases of IC Design Liberty NCX Introduction
1 lecture 1 lecture
Cell-Level Digital Design Flow Transistor level description
2 lectures 1 lecture
Digital Design Flow Physical Design Formats
2 lectures 2 lectures
Library/IP design Functional Description
1 lecture 2 lectures
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Chip Design
Lecture - 3
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Phases of IC Design
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Phases of IC Design
Specification Design process IC design Manufacturing
IC
process
9 bit resolution
10 bit
200 MHz
conversion rate
400 MHz
200 MHz clock
frequency 400
MHz
Integral nonlinearity
1 LSB
. . . . . . . .
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Specification
One-sided Pi aj or Pi al
Limitations
Two-sided bk Pj bm
Pi is ith parameter of IC
aj is boundary value of ith parameter of IC
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Specification Example
N0 Parameter description Min Typ Max Units
1. Process 3.3V IO devices in TSMC 0.11
2. Resolution 9 10 Bits
3. Conversion Rate 200 400 MHz
4. Input Clock Frequency 200 400 MHz
5. Integral Nonlinearity 1 LSB
6. Differential Nonlinearity 0.5 LSB
7. Gain Error 5 %FSR
8. Offset error 5 %FSR
9. Signal to Noise Ratio 56 62 DBc
10. Harmonic Distortion -60 DBc
11. Temperature Drift 12 ppm/C
12. Reference Voltage 1.25 V
13. Analog Input Voltage 1.6 V
14. Power Supply Voltage1 0.8 1.1 1.22 V
15. Power Supply Voltage2 3 3.3 3.6 V
16. Power Dissipation 125 180 mW
17. Operating Temperature 0 125 °C
18. Spurious Free Dynamic Range -10 dB
19. Effective Resolution Band Width 6 MHz
20. Clock jitter 28 Ps
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IC Design
IC design is a set of files by which one can manufacture
and test the designed IC
. . . . . .
.
Circuit Layout SPICE GDSII
netlist
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Design Process
Design process is the process of getting IC
design from specification
Specification Design process IC design
9 bit resolution 10
bit
200 MHz conversion
rate 400 MHz
200 MHz clock
frequency 400 MHz
Integral nonlinearity 1
LSB
. . . . . . . .
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Classes of Problems Solved during
Design
Formalized
The algorithm of sequence of solution steps which is
known
Unformalized
The algorithm of solution which is currently unknown
though it can be solved by intuitive method.
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Types of Design
Automat
All design problems are formalized.
Automated
A part of design problems is formalized,
and some problems are unformalized.
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Design Levels
System
Add
Accumulator Register-Transfer
Input
Command Register
+1
Command Counter
1
Gate
& &
J TT
C
K
Circuit
Device
n+
p
n +
n
+
p
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Problems solved in one level of
design
Transition into less detailed circuit design
Structural Synthesis
Structural
optimization
Parametrical Synthesis
Parametrical
optimization
Simulation
no
Are the operational
conditions met?
yes
Transition into more detailed circuit design
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Design Flow Concept
Data from the
Specification previous level
Level 1
Operation
needed
Level 2
no
Meets the
spec?
yes
Level n
Next level
Completed
Design
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Verification
Verification is used to check if the design object
produced by the design step is the same as the
needed one
Design Design Design
Spec Level 1 Level 2 Level n
Is it the needed Is it the same Is it the same
design? design? design?
Verification
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Verification Methods
Formal Verification
This method mathematically proves that same design at different design levels
has fully equivalent function
Static Timing Analysis
Path delay is calculated by summing delays of elements without simulation
Simulation
The behavior of object in time and space is reproduced
Emulation
Using device, which works as the system to be verified, submits test vectors,
output signal checks
Prototyping
Building of hardware implementation of design and its testing
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Formal Verification
Formal verification checks whether two designs
are functionally equivalent or not
Formal verification
(Equivalence check)
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Static Timing Analysis (STA)
The arrival time at the input is propagated through the
gates at each level till it reaches the output
O=max[sum(B,D22),sum(C,D21)]
C D21
D22 O
A
D1
B=sum(A,D1)
0 2 4 6
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IC Simulation
Description of
circuit
Simulation
program Results
Simulation deck
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Gate Level Simulation
Simulation of timing behavior of logic design A D
Logic design description B E
Netlist, network C
Components
e.g. AND, OR, etc.
A
Component interconnections
Logic models B
Component behavior
C
Interconnect behavior
Signal values D
Timing models
Component behavior
E
Interconnect behavior
Signal delays Time
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Transistor Level Simulation
supply
Simulation of behavior of a design
consisting of transistors
Transistor level design description
Netlist, network C
Components
A
e.g. NMOS, PMOS, NFET, PFET,
Resistor, etc.
Component interconnections B
Models
ground
Component behavior
A
Interconnect behavior
Signal values
B
Timing models
Component behavior C
Interconnect behavior
Signal delays Time
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