Physical only cells

What is Physical only cells ?

 These cells are not present in the design netlist.
 If the name of a cell is not present in the current design, it will consider as physical only cells.
They do not appear on timing paths reports.
 They are typically invented for finishing the chip. 
 These cell don’t have any logic pins  and use only to meet some DRC rules and for design
protection.
 No logical function

Common physical cells in VLSI

1. Tap cells
2. Tie cells
3. Filler cells
4. Decap cells
5. Endcap cells (Boundary cells)
6. Welltap cells
 Physical only cells
Well tap cell (tap cells)
What is well tap cells ?

Well tap cells (or Tap cells) are used to prevent the latch-up issue in the CMOS design. Well tap cells connect the nwell
to VDD and p-substrate to VSS in order to prevent the latch-up issue. There is no logical function in well tap cell rather
than proving a taping to nwell and p-substrate therefore well tap cell is called a physical-only cell.

Well tap cells have no logical functions, it has only two connections:
 nwell to the power supply (VDD)
 p-substrate to the ground (VSS)
 Physical only cells
Well tap (tap cells)
Structure of well tap cells ?

Well tap cell layout is shown in the figure:

Well tap cell has no input and output pins
 Therefore it is called a physical-only cell.

Look up “latch-up prevention in CMOS” for more

related information !!!
 Physical only cells
Well tap (tap cells)
Need of well tap cells

Early days there was no concept of well tap cell, Standard cells were designed in such a way that each standard cell had nwell to
VDD and p-substrate to VSS connection within the standard cell. But such a standard cell design had consumed more area and
to save the area, later a concept of Tapless cell has evolved. In a tapless cell, there are no well taping inside the standard cell,
well taping is provided by a separate standard cell which is called a well tap cell. So well tap cell is a part of a tapless standard
cell library. Figure shows the structure of a traditional standard cell and a tapless standard cell.
 Physical only cells
Well tap (tap cells)
Placement of well tap cells
Well tap cells are placed after the macro placement and power rail creation. This stage is called the pre-placement stage.
Well tap cells are placed in a regular interval in each row of placement. The maximum distance between the well tap
cells must be as per the DRC rule of that particular technology library. A typical placement of well tap cells is shown in
figure-3.

Well tap cells are generally placed in a straight column in the alternate row as shown in figure and such a pattern is called
checkerboard pattern to provide maximum coverage for well tap. If a macro comes in the path of vertical columns, then the
placement of vertical column shifted alongside macro as shown in the figure.
 Physical only cells
End cap cell (Boundary cell)
What is End cap cell (Boundary cell)

There are high chances to get damaged the gate of standard cells placed at the boundary during the manufacturing of
chip. To prevent such damages at the boundary we have a special kind of cell in the standard cell library is called end cap
cell or boundary cell. Boundary cell not only protects the gate damage at the boundary, but it also serves many other
purposes.

Why need to place End Cap / Boundary Cell?

The end cap cells are placed in the design because of the following reasons:
 To protect the gate of a standard cell placed near the boundary from damage during manufacturing.
 To avoid the base layer DRC (Nwell and Implant layer) at the boundary.
 To make the proper alignment with the other block.
 Some standard cell library has end cap cell which serve as decap cell also.
 Physical only cells
End cap cell (Boundary cell)
Layout of end cap / boundary cell:

The boundary cell is a physical-only cell, has no logical

functions and therefore these cells are not a part of the
netlist.  Boundary cells have mainly Nwell layer, implant
layers, and dummy poly layer and metal rails as shown in
the figure
 Physical only cells
End cap cell (Boundary cell)
Where to place End Cap / Boundary Cells:

The end cap cell or boundary cell is placed at both

the ends of each placement row to terminate the
row. It has also been placed at the top and bottom
row at the block level to make integration with
other blocks. Some standard cell library has also
corner end cap cells to place the corner of the
block. Boundary cells have fixed attribute,
therefore these cells can not be moved during the
optimization. A typical placement of end cap cells
at the end of the row has shown in figure
 Physical only cells
Filler cell
Question: Is it possible that standard cell rows are fully occupied in post route stage in such a way that there are
no gaps anywhere between two standard cells?

Vss Vdd Well tap cell Standard cell

Right
Left Boundary
Boundary cell
cell
 Physical only cells
Filler cell
Question: Is it possible that standard cell rows are fully occupied in post route stage in such a way that there are
no gaps anywhere between two standard cells?

 A practical answer is: No

 There will always be some gaps between standard cells in various places
 Physical only cells
Filler cell
Question: Is there any problems if there are some gaps in standar cell row, what problem may arise due to
empty space?
1. If there are gaps in the standard cell row, the wells and standard cell rail will be discontinuous. These
discontinuities will lead nwell and pwell minimum spacing DRC violation. Metal rail minimum spacing
violations may also come
2. Some island well may miss the well taping => Well taping issue
3. WPE (Well Proximity Effect) will affect the performance of chip
 Physical only cells
Filler cell
What is Filler cell?

 Filler cell is the solution of DRC violations / Well taping issue / WPE effect caused by empty space
 We need to fill all the gaps using filler cells and we will have a continuous wells layer, implant layer and
power rails
 Generally we prefer a single well layer throughout the standard cell row
 All standard cells are designed in such a way that, when they are abutted to each other, there well layers,
implant layers, metal rail layer will get connected to each other and these layers become a single continuous
layer
 Physical only cells
Filler cell
What is Filler cell?

Filler cells are standard cells which have:

 No logic functions
 nwell, pwell, n-implant, p-implant, poly and metal rails only
 No input and output pins

Is there any logical function in filler cell?

 No
 Physical only cell
 No entry in netlist
 Physical only cells
Filler cell
Layout of Filler cell? How filler cell get inserted?
 Physical only cells
Filler cell
Placement of filler cell

Standard cell library contains multiple filler cells which having width multiple of minimum unit grid width
 Physical only cells
Filler cell
Placement of filler cell

Oder of filling: Wider cells are placed first, then smaller cells until the least width cell → example: 16w, 8w,
4w, 2w, 1w.
 Physical only cells
Decap cell
What is Decap cell ?

Decap cells are basically a charge storing device made of capacitors and used to support the instant current requirement
in the power delivery network.

Why need of Decap cell ?

There are various reasons for the instant large current requirement in the circuit and if there are no adequate measures
have taken to handle this requirement, power drop or ground bounce may occur. These power drop or ground bounce
will affect the constant power supply and ultimately the delay of standard cells may get affected. To support the power
delivery network from such sudden power requirements, decap cells are inserted throughout the design.
 Physical only cells
Decap cell
Schematic and layout of Decal Cell

There could be various ways to make capacitors out of MOS transistors but the must widely used structure is shown in
the figure-1. 

Figure-1(a) shows the various capacitances inside the MOS

transistor and it if we connect the source, drain and body
terminal together then all these capacitance will configured as a
parallel capacitance as shown in figure-1(b) and a single
equivalent capacitance as shown in figure-1(c). Figure-1(d)
shows a decap capacitor schematic using a pMOS and an nMOS
transistor. From this schematic, we can say that the capacitance
due to nMOS and pMOS will be in parallel and get added to
form a big capacitor.
 Physical only cells
Decap cell
Schematic and layout of Decal Cell

Figure-2 shows the layout of a simplest decap cell.

Source and drain of pMOS transistor shorted together and

connected to VDD and the Gate is connected to VSS. Similarly,
the source and drain of the nMOS transistor are connected to
the VSS and gate is connected to VDD.
 Physical only cells
Decap cell
Use of Decap cell

In the operation of CMOS logic, there is a region of input transition where both the nMOS and pMOS is conducting
together as shown in figure-2(a). A large short circuit current Isc will flow for that instant. If a large number of such cells
are placed together and switching together, a large current will be required as shown in figure-2(b). This large current
requirement may drop the VDD or may increase the ground voltage which is called voltage drop or groud bounce as
shown in figure-2(c).

Voltage droop or ground bounce may result in the change in the

delay of connected standard cells. As the delay is proportional
to the supply voltage. Change in delay may further affect the
timing of design and if the supply voltage drop is high, the
functionality of the standard cell may get affected. So to support
the power delivery, we add the decap cells. Decap cells work as
charge reservoirs and support the power delivery network and
make it robust as shown in the figure-2(d). 
 Physical only cells
Decap cell
Placement of Decap cell

Decap cells are placed generally after the power planning and before the standard cell placement, that is in the pre-
placement stage. These cells are placed uniformly throughout the design in this stage. Decap cells can also be placed in
the post route stage also if required. 

The only problem with decap cells is that these are leaky and increases the leakage power of design, so must be used
judiciously. 
 Physical only cells
Tie Cells
What is Tie cells

The tie cell is a standard cell, designed specially to provide the high or low signal to the input (gate terminal) of any
logic gate. The high/low signal can not be applied directly to the gate of any transistors because of some limitations
of transistors, especially in the lower node. The limitation will also be discussed along with the schematic and
operation of tie cells

Need of Tie cells

In the lower technology node → the gate oxide under the poly gate is a very thin and the most sensitive part of the
transistor. So we need to take special care of this thin gate oxide while fabrication (associated issue is antenna
effect) as well as in operation too. It has been observed that if the polysilicon gate connects directly to VDD or VSS
for a constant high/low input signal, and in case any surge/glitch arises in the supply voltage it results in damage of
sensitive gate oxide. To avoid the damages mentioned above, we avoid the direct connection from VDD or VSS to
the input of any logic gates. A tie cell is used to connect the input of any logic to the VDD or VSS.

Look up “antenna effect” for more related information !!!

 Physical only cells
Tie Cells
Need of Tie cells

Type of Tie cells

 Tie-high cell
 Tie- low cell
 Physical only cells
Tie Cells
Schematic of Tie cells

The tie cell has no input pin and only one output pin. The output of the tie-high cell is always high and the output of
the tie-low cell is always low and it is the glitch-free output that connects to the input of any logic gates.

In the tie-high cell, the drain and gate of nMOS

are shorted together and connected to the gate of
pMOS, and output is taken from the drain of
pMOS. Whereas in the tie-low cell the drain and
gate of pMOS are shorted together and connected
to the gate of nMOS and output is taken from the
drain of nMOS.
 Physical only cells
Tie Cells
Function of Tie cells

Both tie-high and tie-low cells have similar working. Here working of the tie-high cell is explained. A similar logic can
think for tie-low cell. From figure tie-high cell, the drain and gate of nMOS are shorted.

So Vg = Vd
 Vgs = Vds
Therefore, Vds > Vgs – Vt

This shows that the nMOS will always be in the saturation region. The configuration of MOS where drain and gate are
shorted is popularly known as a diode-connected transistor. And when nMOS is behaving like a diode here, the gate of
pMOS is always low and so pMOS is always in on state. When pMOS is in on state its drain which is output will
always be high.

Similarly, for the tie-low cell, the pMOS is always in saturation region so the gate of nMOS is always high and hence
the drain of nMOS will always be at the low logic.

One more important thing is here that the sudden spike in VDD or VSS will be not propagated to the output of the tie
cell.
 Physical only cells
Tie Cells
Placement of tie cells

Tie cells are not present in the synthesized netlist and not placed in the initial placement of the standard cells. Tie
cells are inserted in the placement stage and more specifically at the final stage of placement. Where ever netlist is
having any pin connected to 0 logic or 1 logic (like .A(1’b0) or .IN(1’b1), a tie cell gets inserted there.
 Physical only cells
Spare cell
What is spare cells

Once a chip is fabricated and if any functionality issue is found in the chip or some functionality enhancement is required
in the next fabrication. This might be a very challenging task without spare cells. But with the help of pre-placed spare
cells, these changes can be done very easily.

Spare cells generally consist of a group of standard cells mainly inverter, buffer, nand, nor, and, or, exor, mux, flip flops
and maybe some specially designed configurable spare cells. Ideally, spare cells do not perform any logical operation in
the design and act as a filler cell only. A group of spare cells is shown below. 

The inputs of spare cells are tied either

VDD or VSS through the tie cell and
the output is left floating. Input can not
be left floating as a floating input will
be prone to get affected by noise and
this could result in unnecessary
switching in space cells which leads to
extra power dissipation.
 Physical only cells
Spare cell
Use of Spare Cells

Spare cells enable us to modify/improve the functionality of a chip with minimal changes in the mask. We can use
already placed spare cells from the nearby location and just need to modify the metal interconnect. There is no need to
make any changes in the base layers. Using metal ECO we can modify the interconnect metal connection and make use
of spare cells. We only need to change some metal mask, not the base layer masks.

For example, suppose in the above circuit we need to replace

the last OR gate in the middle part of a circuit with an EXOR or
an AND gate, we can reconnect the spare cell placed near this
with metal ECO only.
 Physical only cells
Spare cell
Placement of Spare Cells

Spare cells can be added either by the netlist or by PnR tool command (or GUI too). In Physical design, we prefer to add
the spare cells using tool command. These cells are added before the placement of standard cells throughout the design.
 Physical only cells
Spare cell
Advantage and Disadvantage of Spare cells

Advantage
 Reusability: There is only change in some metal and via masks, so base layers mask can be reused in chip
fabrication.
 Flexibility: Small changes can be done in the design very easily.
 Cost and Time saving: We need only a few interconnect mask for a new design, which save lots of manufacturing
cost for new chip fabrication. And using metal ECO we do not need to run full design cycle and therefore save design
time.
Disadvantage
 Leakage Power: Spare cells increase the leakage power dissipation in the design.
 Area: Spare cells cost extra area overhead in the design.