ASIC Design Flow
Agenda
• ASIC Design Flow
• Types of Design Flows
• Design Trends
ASIC Design Flow
System Specification
Architectural Design
Functional Design & Verification
Synthesis
Floor Planning
Power Planning
Placement
Clock Tree Synthesis
Routing
Physical Verification
IC Fabrication
ASIC Design Flow
System Specification
Architectural Design
Functional Design & Verification
Synthesis
Floor Planning
Power Planning
Placement
Clock Tree Synthesis
Routing
Physical Verification
IC Fabrication
System Specification
• Functional Specification
• Design Goals
Speed
Power
Area
Technology
Architectural Design
Based on the functional specification and the
design goals, the top level, block level
architectures would be designed based on the
hierarchy
Functional Design and Verification
• Realizing the hardware through hardware description
languages
HDL
Verilog
VHDL
HVL
System Verilog
System C
Vera
Methodologies
UVM
VMM
OVM
Synthesis Input and Output Files
Design source
Code Reports and logs
Verilog(.v ) (text formats)
VHDL (.vhd)
Synthesis Design database
Synthesis (.db - Synopsys internal
scripts (.tcl) Process
database format)
Design
Gate level Verilog description
constraints
(.sdc)
Logic Synthesis
• Logic synthesis is the process of creating logic
circuit from circuit description.
ASIC Design Flow
System Specification
Architectural Design
Functional Design & Verification
Synthesis
Floor Planning
Power Planning
Placement
Clock Tree Synthesis
Routing
Physical Verification
IC Fabrication
Physical Design Flow
Floor planning
Power Planning
Placement
Clock Tree Synthesis
Routing
Finishing
Results (.v, .gds, .spef)
Physical Verification
• DRC Checks
• LVS Checks
ASIC Full Flow
Functional Simulation Flow
Synthesis Flow
Physical Design Flow
Gate Level Simulation Flow
Design Trends
Moore’s Law
• In 1965, Gordon Moore noted that the number of
transistors on a chip doubled every 18 to 24 months.
• He made a prediction that semiconductor technology
will double its effectiveness every 18 months
Transistor Counts
1 Billion
K
1,000,000 Transistors
100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
Courtesy, Intel
Moore’s law in Microprocessors
1000
Transistors (MT)
100 2X growth in 1.96 years!
10
P6
Pentium® proc
1 486
386
0.1 286
8085
Transistors on 8086
Lead Microprocessors double every 2 years
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
Courtesy, Intel
Die Size Growth
100
Die size (mm)
P6
10 486 Pentium ® proc
386
8080 286
8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years
1
1970 1980 1990 2000 2010
Year
Die size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
Frequency
10000
Doubles every
Frequency (MHz)
1000
2 years
100 P6
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
0.1 4004
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years
Courtesy, Intel
Power Dissipation
100
Power (Watts)
P6
Pentium ® proc
10
486
8086 286
386
8085
1 8080
8008
4004
0.1
1971 1974 1978 1985 1992 2000
Year
Lead Microprocessors power continues to increase
Courtesy, Intel
Power will be a major problem
100000
18KW
5KW
Power (Watts)
10000
1.5KW
1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive
Courtesy, Intel
Power Density
10000
Power Density (W/cm2)
Rocket
1000
Nozzle
Nuclear
100 Reactor
8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
8080 286 486
1
1970 1980 1990 2000 2010
Year
Power density too high
Courtesy, Intel
Challenges in Digital Design
DSM 1/DSM
“Microscopic Problems” “Macroscopic Issues”
• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk • High-Level Abstractions
• Reliability, Manufacturability • Reuse & IP: Portability
• Power Dissipation • Predictability
• Clock distribution. • etc.
Everything Looks a Little Different …and There’s a Lot of Them!
?
Die size
Single die
Wafer
From http://www.amd.com Going up to 12” (30cm)
Yield
No. of good chips per wafer
Y 100%
Total number of chips per wafer
Design Flow Comparison
ASIC FPGA
Review Questions
• Define ASIC
• Explain ASIC Design Flow
• Define HDL
• Define HVL
• What do you mean by specification
• What is synthesis
• What is physical design
• What is functional simulation
• What is gate level simulation
Review Questions
• What are inputs and outputs of functional
simulation
• What are inputs and outputs of gate level
simulation
• What are inputs and outputs of synthesis
• What do you mean by front end flow
• What do you mean by backend flow
• What are the steps involved in front end flow
• What are the steps involved in back end flow
Review Questions
• How is ASIC design flow different from FPGA design flow
• What do you mean by time to market
• What does Moore’s law say
• What is yield
• How does following parameters vary as per Moore’s law
Frequency
Number of transistors
Power dissipation
Die size
