Rajalakshmi Institute of Technology

(Autonomous Institution – UGC, Govt. of India)

Department of EE (VLSI Design & Tech.)

APPLICATION SPECIFIC INTEGRATED CIRCUITS

(ASIC DESIGN)
Presented by
Dr.V.M.Senthilkumar
Professor/EE(VLSI)/RIT
06/10/2025
 EV23511-ASIC DESIGN
Course Objectives & Outcomes
Prerequisite:
• Digital System Design
COURSE OBJECTIVES:
• To prepare the student to be an entry-level industrial standard ASIC or FPGA designer
• To understand the basic FPGA Architectures
• To give the students an understanding of issues and tools related to ASIC design
• To analyse the partition and placement issues
• To understand the concept of clock planning in ASIC design
COURSE OUTCOMES:
On completion of this course, the students will have:
• Understanding different FPGA Architecture and their interconnect mechanism
• Familiarize the various programmable ASICs
• Summarize the optimization algorithms in ASIC and applying the concept of partitioning
• Illustrate floor planning and clock planning
• Analyze the various routing algorithm 2
 Course Contents

Unit 1- INTRODUCTION TO ASIC

Unit 2- PROGRAMMABLE ASIC LOGIC CELLS

Unit 3- SYSTEM PARTITIONING AND FLOOR PLANNING

Unit 4- PLACEMENT AND ROUTING

Unit 5- OPTIMIZATION METHODS AND ASIC TESTING

3
 EV23511-ASIC DESIGN

UNIT – I:INTRODUCTION TO ASIC

VLSI Design Flow-Types of ASIC-Programmable ASICs design type-Antifuse-SRAM-EPROM
based ASICs-ASIC fusing based on EPROM-EEPROM based ASICs-FAMOS description Programmable
ASIC logic cells-ASIC I/O cells-Programmable interconnects – FPGA-Types of FPGA-Programmable
FPGA-ASIC I/O Cells: DC Input- AC Input- ASIC I/O Cells-DC/AC output Clock Input- Introduction to
CPLD-CPLD architecture-Types of CPLD.
UNIT – II:PROGRAMMABLE ASIC LOGIC CELLS
Actel ACT Architecture-Actel Interconnect delay analysis-Xilinx LCA -Architecture-Xilinx LCA internal
architecture-Xilinx EPLD Architecture-Xilinx EPLD Internal Architecture-Xilinx LCA Interconnect-Xilinx
EPLD Interconnect-Altera MAX 7000, - Architecture-Altera Max 9000 : Architecture-Altera Max 9000 :
interconnect mechanism-Altera Interconnect features- Altera MAX 5000 : Interconnect Delay analysis.
UNIT – III:SYSTEM PARTITIONING AND FLOOR PLANNING
System Partitioning Objectives-System partitioning Procedure-Partitioning Methods Measuring
Connectivity-Problem on Constructive Partitioning-Constructive Partitioning Iterative Partitioning
Improvement-Problem on Iterative Partitioning Improvement-The Kernighan–Lin Algorithm-The
Ratio-Cut Algorithm- ASIC floor planning-Channel Definition I/O and Power Planning -Clock Planning

06/10/2025 4
Contd..
UNIT IV PLACEMENT AND ROUTING
Placement-placement algorithms- Eigen value placement algorithm- Iterative
placement improvement-Time driven placement methods-Introduction to
Routing- single layer global routing-single layer detailed routing wire length-
Global Routing Methods-Routing between blocks-inside flexible blocks-
Detailed Routing- Algorithms-Left Edge algorithm-Area routing algorithm-
Multilevel Routing-Timing driven detailed routing-Special routing.
UNIT V OPTIMIZATION METHODS AND ASIC TESTING
Trade off issues at System Level-Solutions to the issues at system level-
Optimization with regard to speed-Optimization with regard to area-
Optimization with regard to power Optimization trade off factor Asynchronous
and low power system design- Boundary scan test – Faults – Fault simulation –
Automatic test pattern generation algorithm: D-algorithm, PODEM – Built in
self-test.
06/10/2025 5
 Text Books

1. Smith, Michael. Application-Specific Integrated Circuits. United Kingdom, Addison

Wesley Professional, 2008
2. Douglas J. Smith, Fundamentals of HDL Design: An Engineering Approach. India:
Pearson Education, 2010.
3. Taraate, Vaibbhav. ASIC Design and Synthesis: RTL Design Using Verilog.
Germany: Springer Singapore, 2021.
4. Golshan, Khosrow. Physical Design Essentials: An ASIC Design Implementation
Perspective. Ukraine: Springer US, 2007.
5. Herwani, Naveed A. Sherwani, Naveed A. Algorithms for VLSI Physical Design
Automation. United States: Springer US, 2013.

6
06/10/2025 7
06/10/2025 8
 HISTORY OF IC
• First op amps built in 1930’s-1940’s
• Used in WW-II to help how to strike
military targets
- Buffers, summers, differentiators,
inverter

9
Contd Analog
Computer

…
 Vacuum Tube Era, 1945s
 1st used in Analog Computers
 Addition
 Subtraction
 Integration
 Differentiation
 Heavy
 Prone to failure

K2-W tubes general

purpose Op-
1
Amp. 1952 0
Contd..
• In 1947 Bardeen and Brattain and Shockley succeeded in creating an amplifying
circuit utilizing a point-contact "transfer resistance" device that later became
known as a transistor.
• In 1951 Shockley developed the junction transistor, a more practical form of the
transistor.
• By 1954 the transistor was an essential component of the telephone system
and the transistor first appeared in hearing aids followed by radios.
• 1962 NPN Transistor
• 1963 RTL Logic
• 1965 - Moore’s Law, Transistors per IC doubles every 18 months
- 2300 transistors on the 4004 (‘71) -> 42 Million on the
Pentium 4 (’00), 2.3x1098 core Xenon Shrink
Transistor Size by 30% every two years!
11
Contd..
•1967 MOS Transistor
•1972 CMOS- INTEL 8008
•1995 Intel Pentium Pro
•In 2000 Jack St. Clair Kilby was an American electrical engineer
who took part (along with Robert Noyce) in the realization of the
first integrated circuit while working at Texas Instruments (TI) in
1958. He was awarded the Nobel Prize in Physics on December 10,
2000.

12
Contd..
•2010-FinFET Device

•2015-CNTFET

•2018-SoC

13
 Integrated Circuit(IC)?

-Microchip

 Why IC?
- Size, Speed, Power & Complexity

14
 Physical Design, CAD Tools.

• SiCore Systems Pvt. Ltd. 161, Greams Road, ...

• Silicon Automation Systems (India) Pvt. Ltd. ( SASI) ...
• Tata Elxsi Ltd. VLSI Design Group, ...
• Tata Infotech Ltd. Bangalore. ...
• Texas Instruments (India) Ltd. Golf View Homes, ...
• TranSwitch (India) Pvt. Ltd. ...
• Vedatech India (Software) Pvt. Ltd.

15
 Integrated Circuit
 Wafer : A circular piece of pure silicon (10-15 cm bu
in dia, wafers of 30 cm dia are expected t
 Wafer Lot: soon)
5 ~ 30 wafers, each containing
 Die: hundreds of chips(dies) depending
upon size of the die
A rectangular piece of silicon that
 Mask Layers: Each IC is manufactured with
contains one
successive
IC design
mask layers(10 – 15 layers)
 First half-dozen or so layers define transistors
 Other half-dozen define Interconnect

16
Integrated Circuit (IC) in a package

(a) A pin-grid array (PGA) package.

(b) The silicon die or chip is under the package lid.

17
 Evolution of IC
• SSI (Small-Scale Integration)-(1962)
– Tens of Transistors
– NAND, NOR

• MSI (Medium-Scale Integration)-(late 1960)

– Hundreds of Transistors
– Counters

• LSI (Large-Scale Integration)-(mid 1970)

– Tens of Thousands of Transistors
– First Microprocessor

• VLSI (Very Large-Scale Integration)-(1980)

– started Hundreds of Thousands of Transistors-several billion transistors in 2009
– 64 bit Microprocessor with cache memory and floating-point arithmetic units

• ULSI (Ultra Large-Scale Integration)-(late 1980)

– More than about one million circuit elements on a single chip.
– The Intel 486 and Pentium microprocessors, use ULSI technology
18
 IC technologies
• Bipolar
– More accuracy
• MOS
– Gate-Aluminium
– Low power consumption
– Low cost
• CMOS
– Gate-Poly-Silicon
– Low power consumption
– Low cost
• BiCMOS
19
 Types of IC
• Standard ICs
• Glue Logic-Microelectronic system design then
becomes a matter of defining the functions
that you can implement using standard ICs
and then implementing the remaining
logic functions (sometimes called glue logic )
with one or more custom ICs.
• ASIC
• ASSP (Application-Specific Standard Products)

20
What is an ASIC?
ASIC, short for application-specific integrated circuits is a specialized type of integrated circuit
meticulously designed to perform a specific function or set of functions within an electronic
system.
Unlike general-purpose microprocessors in everyday electronic devices like your microwave
or TV box, ASICs are tailor-made for a particular application, offering unparalleled efficiency
and performance.
Applications of ASICs
Consumer electronics: ASICs are omnipresent in consumer electronics, powering devices
such as smartphones, digital cameras, and smart TVs. Their ability to provide tailored
solutions enhances these gadgets’ overall performance and power efficiency.
Telecommunications: ASICs are employed in networking equipment, routers, and
communication devices. Their custom-designed nature ensures optimal functionality and
speed in processing data.
Automotive industry: ASICs contribute significantly to the automotive industry, in which they
are integrated into various systems like engine control units (ECUs),
advanced driver-assistance systems (ADAS), and infotainment systems.
Healthcare: Medical devices, diagnostic equipment, and imaging systems often incorporate
ASICs to meet the stringent requirements of precision, reliability, and power efficiency.
ASIC DESIGN FLOW
 ASIC Design Flow
1.Design entry. Enter the design into an ASIC design system, either
using a hardware description language ( HDL ) or
schematic entry .
2. Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis
tool to produce a netlist —a description of the logic
cells and their connections.
3. System partitioning. Divide a large system into ASIC-sized pieces.
4. Prelayout simulation. Check to see if the design functions correctly.
5. Floorplanning. Arrange the blocks of the netlist on the chip.
6. Placement. Decide the locations of cells in a block.
7. Routing. Make the connections between cells and
8. Extraction. blocks.
Determine the resistance and capacitance of the
9. Postlayout simulation. interconnect.
Check to see the design still works with the
added, and
Steps 1–4 are part of logical design loads
steps 5–9 are part of physical
design . of the interconnect.
• There is some overlap. For example, system partitioning might be considered as either logical
or physical design. To put it another way, when we are performing system partitioning we have to 55
consider both logical and physical
factors.
 ASIC Design Process – Cont’d
Altera FPGA Design Flow – A Self-Contained System that
does all from Design Entry, Simulation, Synthesis, and Programming of Altera
Devices

• EDIF-Electronic Design Interchange

Format
• SDF-Standard Delay Format

25
 ASIC Design Process – Cont’d
Xilinx FPGA Design Flow – Allows Third-Party Design Entry
SW, Accepts their generated netlist file as an input

• XNF-Xilinx Netlist
Format
• LCF-Library Container
File

26
FPGA Vs ASIC Design Flow

• ECO-
Engineei
rngchan
ge order
•
ASIC Design Flow Using Cadence Tool
Start

Specificatio
ns
RTL
Coding
Incisive Tool
(Using
Platform
Functional
gedit) (NCLAUNC
Verification H)
(Using
simvision)
Synthes
is
Encounter
Timing
RTL
Simulation Complier

DFT (Design
For
Testability)
Floorplanning

Power Planning

Placement

Clock Tree
Synthesis(CTS) Encounter RTL
to GDSII
Routing

DRC/LVS

GDS-- Graphical
Data Stream
XR Information
C Interchange
GDSI
 ASIC and Non ASIC
• Examples of ICs that are not ASICs include standard parts such as:
– memory chips sold as a commodity item—ROMs, DRAM, and SRAM;
microprocessors;
– TTL or TTL-equivalent ICs at SSI, MSI, and LSI levels.

• Examples of ICs that are ASICs include:

– a chip for a toy bear that talks;
– a chip for a satellite;
– a chip designed to handle the interface between memory and a
microprocessor for a workstation CPU;
– a chip containing a microprocessor as a cell together with other logic.

• ASSP (two ICs that might or might not be considered ASICs )

– controller chip for a PC and a chip for a modem.
– Both of these examples are specific to an application (shades of an ASIC)
but are sold to many different system vendors (shades of a standard part).
ASICs such as these are sometimes called application-specific standard14
products ( ASSPs ).
 Measurement of IC
• Gate Equivalent
– Number of gates or transistors
– Gate refer to two input NAND Gate
– In CMOS, each NAND gate consist of 4 transistors
– Example : 10k gate IC
– (10,000 two-input NAND gates or 40,000 transistors in
CMOS)

• Feature Size (smallest feature size =  )

– Half of smallest transistor length
– Example: 0.5µm IC
32
– Feature size,  = 0.25µm
 Types of ASICs – Cont’d

• Full-Custom ASICs: Possibly all logic cells and all mask layers customized
• Semi-Custom ASICs: all logic cells are pre-designed and some (possibly all)
mask layers customized
33
 Types of ASICs – Cont’d
 Full-Custom ASICs
 Include some (possibly all) customized logic cells

 Have all their mask layers customized

 Manufacturing lead time is typically 8 weeks (time taken to make

the IC does not include design time)

 Full-custom ASIC design makes sense only

 When no suitable existing libraries exist or

 Existing library cells are not fast enough or

The available pre-designed/pre-tested cells consume too much

power that adesign can allow or
 The available logic cells are not compact enough to fit or

 ASIC technology is new or/and so special that no cell library exits.

17
 Types of ASICs – Cont’d
 Full-Custom ASICs
 Advantages:
 Offer highest performance
 lowest cost (smallest die size)

 Disadvantages
 Increased design time
 Increased Complexity
 Higher design cost
 Higher risk.

 Some Examples:
 Microporcessor,
 High-Voltage Automobile Control Chips
 Ana-Digi Communication Chips
 Sensors and Actuators
35
 Types of ASICs – Cont’d
 Semi-Custom ASICs
 Standard-Cell based ASICs (CBIC- ―sea-bick‖)

 Use predesigned logic cells (Called standard cells) from

standard cell libraries

other mega-cells (Microcontroller or Microprocessors)

full-custom blocks

System-Level Macros(SLMs)

 Functional Standard Blocks (FSBs)

 cores etc

 Get all mask layers customized- transistors and interconnect

 Manufacturing lead time is about 8 weeks

 Custom blocks can be embedded

36
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Standard-Cell based
ASICs
(CBIC- ―sea-bick‖) – Cont’d

37
 Types of ASICs – Cont’d
 Standard Cell in Flexible block of CBIC

• Std cell in library is constructed using full-custom

design methodology-
– Same performance and flexibility but reduce time and risk.

• ASIC designer defines only placement of standard cells

– It can be placed anywhere on silicon.

 Construction of Flexible blocks in CBIC

– Standard cells are designed like bricks in a wall.
– Groups of standard cells fit horizontally to form rows.

– The rows stack vertically to form flexible blocks- reshape

during design
– Flexible blocks connected with other std cell blocks or full
custom block
38
 Types of ASICs – Cont’d
 Wiring cells in Standard Cell based ASICs
• Feedthrough cell:
• Piece of metal that is used to pass a signal through a cell or to a space in a cell
waiting to be used as a feedthrough

• Spacer cells
• The width of each row of standard cells is adjusted so that they may be
aligned using spacer cells .

• Row end cells

• The power buses, or rails, are then connected to additional vertical power
rails using row-end cells at the aligned ends of each standard-cell block.

• Power cells
• If the rows of standard cells are long, then vertical power rails can also be run
in metal2 through the cell rows using special power cells that just connect to
VDD and GND.
• Usually the designer manually controls the number and width of the
vert 2ic2al
 Types of ASICs – Cont’d
 Advantages of CBIC
– Save time, money, reduce risk

– Standard cell optimized individually for speed or area

 Disadvantages of CBIC:
– Time to design standard cell library

– Expenses of designing std cell library

– Time needed to fabricate all layers of the ASIC for new design

23
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Gate Array based ASICs
 Transistors are predefined on the silicon wafer
 Predefined pattern of transistors on a gate array is base array.
 Smallest element repeated to form base array is base cell.
 Only the top few layers of metal, which define the interconnect
between transistors, are defined by the designer using custom masks.It is
often called a masked gate array ( MGA ).
 Less turnaroundtime: fewdays or couple of weeks.

24
 Similar to CBIC –but here space is fixed
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Chanelless Gate Array ASIC

• The key difference between a channelless gate array and channeled

gate array
• there are no predefined areas set aside for routing between
cells on a channelless gate array.
• Use an area of transistors for routing in a channelless array,
we do not make any contacts to the devices lying underneath; we
simply leave the transistors unused.
• The logic density—the amount of logic that can be
implemented in a given silicon area is higher for channelless gate
array 42
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Difference between Channeled and Chanelless Gate Array ASIC

• contact mask is customized in a channelless gate

array, but is not usually customized in a channeled gate
array. This leads to denser cells in the channelless
architectures.

• Customizing the contact layer in a channelless gate

array allows us to increase the density of gate-array cells
because we can route over the top of unused contact sites.
43
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Structured Gate Array based ASICs
- Cont’d

• An embedded gate array or structured gate array (also known as masterslice or

masterimage ) combines some of the features of CBICs and MGAs.
• One of the disadvantages of the MGA is the fixed gate-array base cell. This
makes the implementation of memory, for example, difficult and inefficient.
•In an embedded gate array we set aside some of the IC area and dedicate it
to a specific function.
•This embedded area either can contain a different base cell that is
more suitable for building memory cells, or it can contain a complete circuit
block, such as a microcontroller.
44
 Channelled gate array
Adv: Specific space for interconnection
Disadv: compared to CBIC space is not adjustable
Channelless gate array
Adv :
• Logic density is higher for channelless gate array
• Contact layers are customized
Disadv:
• No specific area for routing
• Rows of transistors used for routing are not used for other purpose.
Structured Gate Array
Adv:
• Embedded gate array set in some of IC area and dedicate to
specific
function-customized.
• Increase area efficiency, performance of CBIC
•Disadv:
low cost and fast turn around of MGA
28
Embedded function is fixed
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Programmable ASICs
PLDs - PLDs are low-density
devices which contain 1k – 10 k gates and
are available both in bipolar and CMOS
technologies [PLA, PAL or GAL]
 CPLDs or FPLDs or FPGAs
-
FPGAs combine architecture of gate arrays
with programmability of PLDs.
 User Configurable
Contain Regular Structures -
circuit elements such as AND, OR,
NAND/NOR gates, FFs, Mux, RAMs,
 Allow Different
Programming Technologies
 Allow both Matrix and Row-
based Architectures

46
 Programmable Logic Devices
• Programmable logic devices ( PLDs ) are standard ICs
– Available in standard configurations
– Sold in very high volume to many different customers.
– PLDs may be configured or programmed to create a part customized to a specific
application
– PLDs use different technologies to allow programming of the device.

• The important features of PLDs:

– No customized mask layers or logic cells
– Fast design turnaround

• Structure of programmable logic device (PLD)

– A single large block of programmable interconnect
– A matrix of logic macrocells that usually consist of programmable array logic
followed by a flip-flop or latch

47
 Examples of PLD
• The simplest type of programmable IC is a read-only memory ( ROM ).

• The most common types of ROM use a metal fuse that can be
blown permanently
(a programmable ROM or PROM ).

• An eraseable programmable ROM (EPROM) , uses programmable MOS

transistors whose characteristics are altered by applying a high voltage.

• Erasable PROM
– Erase an EPROM either by using another high voltage (an electrically erasable
PROM , or EEPROM )
– Exposing the device to ultraviolet light ( UV-erasable PROM , or
UVPROM ).

• There is another type of ROM that can be placed on any ASIC—a

maskprogrammable ROM (mask-programmed ROM or masked
ROM).
– A masked ROM is a regular array of transistors permanently programmed using
custom mask patterns.
 PROM

PROM, it is not fast enough.

Occupies more space.
49
PROM

50
 Type of PLDs-PLA and PAL
• Place a logic array as a cell on a custom
ASIC. This type of logic array is called a
programmable logic array (PLA).

• A PLA has a programmable AND logic

array, or AND plane , followed by a
programmable OR logic array, or OR
plane

• A PAL has a programmable AND plane

and, in contrast to a PLA, a fixed OR
plane.

• Depending on how the PLD is

programmed, we can have an
– Erasable PLD (EPLD),
– Mask-programmed PLD (called as
masked PLD but usually just PLD).

• The first bipolar based PALs, PLAs, and

PLDs used programmable fuses or links.

• 34
CMOS PLDs usually employ floating-gate
transistors
 Programmable Logic Devices
PLA PLA Design Example

35
 PAL

• Suitable to
implement sequential 36
logic.
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Programmable ASICs
PLDs - PLDs are low-density
devices which contain 1k – 10 k gates and are
available both in bipolar and CMOS
technologies [PLA, PAL or GAL]
CPLDs or FPLDs or
FPGAs -
FPGAs combine architecture of gate arrays with
programmability of PLDs.
User Configurable
Contain Regular Structures -
circuit elements such as AND, OR,
NAND/NOR gates, FFs, Mux, RAMs,
 Allow Different
Programming Technologies
Allow both Matrix and Row-
based Architectures

54
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Programmable ASICs - Cont’d
 Structure of a CPLD / FPGA

55
 Essential characteristics of FPGA

• Core-regular array of Programmable basic logic cells implement

combinational or sequential logic
• Matrix of programmable interconnects surround the basic logic cells

• Programmable I/O cells surround the core

• A method of programming the basic logic cells and interconnect

• None of the mask layers are customized

• Design turnaround is few hours.

• Difference between PLD and FPGA:

– FPGA are larger and more complex than PLD

56
 Why FPGA-based ASIC Design?
 Choice is based on Many
Requirement FPGA/FPLD Discrete Logic Custom Logic
Factors ; Speed

 Speed Gate Density

 Gate Density Cost

 Development Time
Development Time
 Prototyping and Simulation
Time Prototyping and Sim.

 Manufacturing Lead Time Manufacturing

 Future Modifications Future Modification

 Inventory Risk Inventory

 Cost
Development Tools

Very Effective Adequate Poor

57
Different Categorizations of FPGAs
Based on Functional
Unit/Logic Cell Structure
 Transistor Pairs
 Basic Logic Gates: NAND/NOR
 MUX
 Look –up Tables (LUT)
 Wide-Fan-In AND-OR Gates
Programming Technology
 Anti-Fuse Technology
 SRAM Technology
 EPROM Technology
Gate Density
Chip Architecture (Routing Style)

58
Different Types of Logic Cells

59
 Different Types of Logic Cells – Cont’d
 Actel Act Logic Module Structure
 Use Antifuse Programming Tech.
 Based on Channeled GA Architecture
 Logic Cell is MUX which can be configured as multi-input logic gates

The Actel ACT 2 and ACT 3 Logic Modules. (a) The C-

Module for combinational logic. (b) The ACT 2 S-Module.
(c) The ACT 3 S-Module. (d) The equivalent circuit (without
buffering) of the SE (sequential element). (e) The
sequential element configured as a positive-edge–triggered D
flip-flop. (Source: Actel.)

60
Different Types of Logic Cells – Cont’d
To SUMMARIZE, FPGAs from various
vendors differ in their
 Architecture (Row Based or Matrix Based
Routing Mechanism)
 Gate Density (Cap. In Equiv. 2- Input NAND
Gates)
 Basic Cell Structure
 Programming Technology

61
 Programming Technologies
 Three Programming Technologies
 The Antifuse Technology
 Static RAM Technology
 EPROM and EEPROM Technology

62
 Antifuse
An antifuse is an electrical device that performs the opposite function to a fuse. Whereas a fuse starts with a low resistance
and is designed to permanently break or open an electrically conductive path (typically when the current through the path
exceeds a specified limit), an antifuse starts with a high resistance—an open circuit—and programming it converts it into a
permanent electrically conductive path (typically when the voltage across the antifuse exceeds a certain level).

[a [b
] ]

[c [d
] ] 63
 Programming Technologies – Cont’d
 The Antifuse Technology
 Invented at Stanford and
developed by Actel
Opposite to regular fuse Technology
 Normally an open circuit until a
programming current (about 5 mA) is
forced through it
 Two Types:
Actel’s PLICE
[[Programmable Low-Impedance Circuit Element]-
 A High-Resistance Poly-Diffusion

Antifuse [A] Actel Antifuse cross section

 ONO layer offers high resistance
 For 5mA, resistance is 500Ω b. Link in Actel Antifuse
 Programming time-5-10 c. Actel Antifuse in metal contacts
Minutes
 Disadvantages:
d. Actel Antifuse Resistance
It doesn’t allow large amount of
current
Need extra space to connect
witnh metal layer- add parasitic
capacitance.-Unwanted Long Delay.
OTP 64
 Programming Technologies – Cont’d
 QuickLogic’s Low-Resistance
metal-metal antifuse [ViaLink]
technology
 Direct metal-2-metal
connections
 Higher programming
currents reduce antifuse
resistance
For 15mA, resistance is 80 Ω
Advantage:
No parasitic capacitance- [A] QuickLogic Antifuse – two level metal
reduce delay b.QuickLogic Antifuse – three level metal
 Disadvantages of Antifuse c.QuickLogic Antifuse in metal contacts
technology:

d.QL Antifuse Resistance
Unwanted RC Delay
 OTP Technology
 Less reliable- electromigration
 Need separate programming
box- Activator.
65
 Programming Technologies – Cont’d
 Static RAM Technology
 SRAM cells are used for
As Look-Up Tables (LUT) to implement logic (as Truth
Tables)
As embedded RAM blocks (for buffer storage etc.)
Two cross coupled inverters and a standard CMOS
process
The configuration cell make or break connection
As control to routing and configuration switches

 Advantages
Allows In-System Programming (ISP)
Suitable for Reconfigurable HW

 Disadvantages
 Volatile – needs power all the time / use PROM to
download configuration data
 Larger in size than Antifuse

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Programming Technologies – Cont’d
 EPROM and EEPROM Technology-(Altera & Xilinx)

EPROM Cell is almost as small as Antifuse

Floating-Gate Avalanche MOS (FAMOS) Tech.
 Under normal voltage, transistor is on
 With Programming Voltage applied, we can turn it off
(configuration) to implement our logic
 Exposure to UV lamp (one hour) we can erase the programming
 Use EEPROM for quick reconfiguration, also, ISP possible

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 Programming Technologies – Cont’d
 Summary Sheet

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