MAHAKAVI BHARATHIYAR COLLEGE OF ENGINEERING

AND TECHNOLOGY
Thalayanai Road, Vasudevanallur- 627760
Department of Electronics and Communication Engineering
Academic Year 2024 – 2025 (Odd semester)
Course Plan

Programme : B.E Degree : B.E

Course Name : VLSI AND CHIP DESIGN Course Code : EC3552

Course Area/
Course Type : Professional core : VLSI
Domain
Corresponding Lab VLSI AND CHIP DESIGN LAB Lab Course
Course Name
:
Code
: EC3561

Year / Sem / Dept : III /IV / ECE Contact Hours : 45Hrs

COURSE OBJECTIVES:
The student should be made:
 Understand the fundamentals of IC technology components and their characteristics.
 Understand combinational logic circuits and design principles
 Understand sequential logic circuits and clocking strategies.
 Understand ASIC Design functioning and design.
 Understand Memory Architecture and building blocks

PREREQUISITE:

COURSE
COURSE NAME DESCRIPTION SEM
CODE
Understand the fundamentals of IC technology
EC3352 DIGITAL SYSTEM DESIGN III
components and their characteristics

SYLLABUS No .of credits: 3

UNIT DETAILS HOURS

MOS TRANSISTOR PRINCIPLES
I MOS logic families (NMOS and CMOS), Ideal and Non Ideal IV Characteristics, CMOS 9
devices. MOS(FET) Transistor Characteristic under Static and Dynamic Conditions,
Technology Scaling, power consumption
COMBINATIONAL LOGIC CIRCUITS
II Propagation Delays, stick diagram, Layout diagrams, Examples of combinational logic 9
design, Elmore’s constant, Static Logic Gates, Dynamic Logic Gates, Pass Transistor Logic,
Power Dissipation, Low Power Design principles.
SEQUENTIAL LOGIC CIRCUITS AND CLOCKING STRATEGIES
III Static Latches and Registers, Dynamic Latches and Registers, Pipelines, Non bistable, 9
Sequential Circuits. Timing classification of Digital Systems, Synchronous Design, Self-
Timed Circuit Design
IV INTERCONNECT , MEMORY ARCHITECTURE AND ARITHMETIC 9
CIRCUITS
Interconnect Parameters – Capacitance, Resistance, and Inductance, Electrical Wire Models,
Sequential digital circuits: adders, multipliers, comparators, shift registers. Logic
 Implementation using Programmable Devices (ROM, PLA, FPGA), Memory Architecture
and Building Blocks ,Memory Core and Memory Peripherals Circuitry
ASIC DESIGN AND TESTING
V Introduction to wafer to chip fabrication process flow. Microchip design process & issues in
test and verification of complex chips, embedded cores and SOCs, Fault models, Test coding. 9
ASIC Design Flow, Introduction to ASICs, Introduction to test benches, Writing test benches
in Verilog HDL, Automatic test pattern generation, Design for testability, Scan design: Test
interface and boundary scan.

TEXT BOOKS:
1. Jan D Rabaey, Anantha Chandrakasan, “ Digital Integrated Circuits: A Design Perspective”, PHI, 2016.
(Units II, III and IV).
2. Neil H E Weste, Kamran Eshranghian, “ Principles of CMOS VLSI Design: A System Perspective,”
Addison Wesley, 2009.( Units - I, IV).
3. Michael J Smith ,” Application Specific Integrated Circuits, Addison Wesley, (Unit - V)
4. Samir Palnitkar,” Verilog HDL:A guide to Digital Design and Synthesis”, Second Edition, Pearson
Education, 2003. (Unit - V)
5. Parag K.Lala,” Digital Circuit Testing and Testability”, Academic Press, 1997, (Unit - V)

REFERENCES:
1. D.A. Hodges and H.G. Jackson, Analysis and Design of Digital Integrated Circuits, International Student
Edition, McGraw Hill 1983
2. P. Rashinkar, Paterson and L. Singh, "System-on-a-Chip Verification-Methodology and Techniques",
Kluwer Academic Publishers,2001
3. SamihaMourad and YervantZorian, “Principles of Testing Electronic Systems”, Wiley 2000
4. M. Bushnell and V. D. Agarwal, "Essentials of Electronic Testing for Digital, Memory and Mixed-Signal
VLSI Circuits", Kluwer Academic Publishers,2000

COURSE OUTCOMES:

CO. No. Course Outcomes

On successful completion of this Course ,students will be able to
CO1 In depth knowledge of MOS technology
CO2 Understand Combinational Logic Circuits and Design Principles
CO3 Understand Sequential Logic Circuits and Clocking Strategies
CO4 Understand Memory architecture and building blocks
CO5 Understand the ASIC Design Process and Testing.

COURSE OUTCOMES MAPPING WITH PROGRAM OUTCOMES AND PROGRAM SPECIFIC OUTCOMES

CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3

1 1 1 - - - - - - - - - - 3 3 3
2 3 2 3 2 - - - - - - - 1 3 3 3
3 2 3 2 3 1 1 - - - - - 2 3 2 3
4 - - 1 1 - - - - - - - 3 3 3 2
5 - - - - - 2 - - - - 1 - 3 2 2
C 2 2 2 2 1 1.5 - - - - 1 2 3 3 3

Note:1:Low, 2:Medium, 3:High, ‘-‘: No correlation

LESSON PLAN

Text
/
S. Teaching Course
Date/ Hour Unit Topics to be covered Ref.
No Methodology Outcome
Boo
k
I MOS Transistor Principles
1 12.08.24/3 I MOS logic families (NMOS and CMOS) T1 Black Board CO1
2 13.08.24/5 I Ideal and Non Ideal IV Characteristics T1 Black Board CO1
3 16.08.24/5 I Ideal and Non Ideal IV Characteristics T1 Black Board CO1
4 19.08.24/3 I CMOS devices T1 Black Board CO1
MOS(FET) Transistor Characteristic under Static
5 20.08.24/5 I T1 Black Board CO1
and Dynamic Conditions
MOS(FET) Transistor Characteristic under Static T1,
6 22.08.24/5 I Black Board CO1
and Dynamic Conditions R4
7 23.08.24/5 I Technology Scaling T1 Seminar CO1
8 26.08.24/3 I power consumption T1 Black Board CO1
II Combinational Logic Circuits
9 27.08.24/5 II Introduction T1 Black Board CO2
10 29.08.24/5 II Propagation Delays, stick diagram T1 Black Board CO2
11 30.08.24/5 II Layout diagrams T1 Black Board CO2
12 31.08.24/3 II Examples of combinational logic design T1 Black Board CO2
13 02.09.24/3 II Elmore’s constant T1 Black Board CO2
0309.24/5
14 II Static Logic Gates T1 Black Board CO2
05.09.24/5
15 II Dynamic Logic Gates T1 Seminar CO2
06.09.24/5
16 II Pass Transistor Logic T1 Black Board CO2
17 09.09.24/3 II Power Dissipation T1 Black Board CO2
18 10.09.24/5 II Low Power Design principles T1 Black Board CO2
Sequential Logic Circuits And Clocking
III
Strategies
19 12.09.24/5 III Introduction
20 16.09.24/3 III Static Latches R1 Black Board CO3
21 19.09.24/5 III Registers R1 Black Board CO3
22 21.09.24/5 III Dynamic Latches and Registers T1 Black Board CO3
23 23.09.24/3 III Pipelines R1 Black Board CO3
24 24.09.24/5 III Non bistable Sequential Circuits T1 Seminar CO3
25 26.09.24/5 III Timing classification of Digital Systems T1 Black Board CO3
26 30.09.24/3 III Synchronous Design R1 Black Board CO3
27 01.10.24/5 III Self-Timed Circuit Design T1 Black Board CO3
Interconnect, Memory Architecture And
IV
Arithmetic Circuits

28 03.10.24/5 IV Introduction T1 Black Board CO4

Interconnect Parameters – Capacitance,
29 05.10.24/5 IV T1 Black Board CO4
Resistance, and Inductance
30 07.10.24/3 IV Electrical Wire Models T1 Black Board CO4
31 08.10.24/5 IV Sequential digital circuits: adders, multipliers T1 Black Board CO4
32 10.10.24/5 IV comparators, shift registers T1 Black Board CO4
33 14.10.24/3 IV shift registers T1 Black Board CO4
Logic Implementation using Programmable Black Board
34 15.10.24/5 IV T1 CO4
Devices (ROM, PLA, FPGA)
35 17.10.24/5 IV Memory Architecture T1 Black Board CO4
36 19.10.24/5 IV Building Blocks T1 Seminar CO4
37 21.10.24/3 IV Memory Core and Memory Peripherals Circuitry T1 Black Board CO4
Introduction to Wafer to Chip Fabrication
V
Process Flow

38 22.10.24/5 V Introduction T1 Black Board CO5

Microchip design process & issues in test and T1 Black Board

39 24.10.24/5 V CO5
verification of complex chips
40 28.10.24/3 V embedded cores and SOCs T1 Black Board CO5
41 29.10.24/5 V Fault models, Test coding T1 Black Board CO5
42 04.11.24/3 V ASIC Design Flow, Introduction to ASICs T1 Black Board CO5
Introduction to test benches, Writing test T1 Black Board
43 05.11.24/5 V CO5
benches in Verilog HDL
44 07.11.24/5 V Automatic test pattern generation T1 Seminar CO5
45 09.11.24/5 V Design for testability, Scan design T1 Black Board CO5
46 11.11.24/3 V Test interface and boundary scan. T1 Black Board CO5

CONTENT BEYOND THE SYLLABUS

1 Emerging transistor technologies

2 Analog and Mixed signal circuit design
3 Physical design and verification
4 Low power and energy efficient design
5 Quantum circuits
Website / URL References
1 https:// nptel.ac.in/courses/117106092/

APPLICATION ORIENTED SYLLABUS

1 Developing electronic devices

2 Design hardware
3 Optimizing user interaction

ASSESSMENT METHODS

DIRECT ASSESSMENT INDIRECT ASSESSMENT

 Internal Assessment Test (IAT) / Model Test  Periodical Feedback
 Formative Assessment  Course Exit Survey
 Seminars
 University Examination

Prepared by Approved by
SIGNATURE:
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DESIGINATION:
HOD/