Short Syllabus

BECE303L VLSI System Design (3-0-0-3)

VLSI Design Overview and MOSFET Theory - Concepts of Regularity, Modularity and Locality;
CMOS Logic gates - CMOS Sequential Logic Design, Latches and Flip Flops; CMOS
Fabrication and Layout - CMOS Process Technology, Layout Design Rule; CMOS Circuits
Performance Analysis - Logical Effort and Transistor Sizing; CMOS Logic Families -
Transmission Gates based Logic Design; Timing Analysis - Introduction to Static timing
analysis; Semiconductor Memory Design- Introduction and types.
 Item 66/22 - Annexure - 18

Course Code Course Title L T P C

BECE303L VLSI System Design 3 0 0 3
Pre-requisite BECE204L, BECE204P Syllabus version
1.0
Course Objectives :
1. To introduce the basic concepts and techniques of modern integrated circuit design.
2. Describe the fundamental principles underlying digital design using CMOS logic and
analyze the performance characteristics of these digital circuits.
3. Verify that a design meets its functionality, timing constraints, both manually and
through the use of computer-aided design tools.

Course Outcomes :
Students will be able to
1. Analyze the CMOS digital electronics circuits, including logic components and their
interconnect using mathematical methods and circuit analysis models
2. Create models of moderately sized CMOS inverters with specified noise margin and
propagation delay.
3. Apply CMOS technology-specific layout rules in the placement and routing of
transistors and interconnect.
4. Analyse the various logic families and efficient techniques at circuit level for
improving power and speed of combinational and sequential logic.
5. Implement the CMOS digital circuits with the specified timing constraints.
6. Design memories with efficient architectures to improve access times, power
consumption

Module:1 VLSI Design Overview and MOSFET Theory 8 hours

VLSI Design Flow, Design Hierarchy, Concepts of Regularity, Modularity and Locality, VLSI
Design Styles, Design Quality, MOSFET : Device Structure, Electrical behaviour of MOS
transistors, Capacitance- Voltage Characteristics and Non-ideal Effects; Effects of scaling on
MOSFETs and Interconnects.

Module:2 CMOS Logic Gates 8 hours

CMOS Inverter: DC Transfer Characteristics, Static and Dynamic Behaviour, CMOS Basic
Gates, Compound Gates, CMOS Sequential Logic Design – Latches and Flip Flops

Module:3 CMOS Fabrication and Layout 5 hours

CMOS Process Technology N-well, P-well Process, latch up in CMOS technology, Stick
Diagram for Boolean Functions using Euler Theorem, Layout Design Rule

Module:4 CMOS Circuits Performance Analysis 5 hours

Delay Estimation, Logical Effort and Transistor Sizing, Performance Estimation - Static &
Dynamic Power Dissipation.

Module:5 CMOS Logic Families 8 hours

Pass Transistor Logic, Transmission Gates based Logic Design, pseudo NMOS, Cascode
Voltage Switch Logic Dynamic and domino logic, clocked CMOS (C2MOS) logic and np –
CMOS logic.

Module:6 Timing Analysis 4 hours

Introduction to Static timing analysis, Setup Time, Hold Time, calculation of critical path,
slack, setup and hold time violations.

Module:7 Semiconductor Memory Design 5 hours

Proceedings of the 66th Academic Council (16.06.2022) 404

 Item 66/22 - Annexure - 18

Introduction, Types - Read-Only Memory (ROM) Circuits, Static Read-Write Memory

(SRAM) and Dynamic Read-Write Memory (DRAM) Circuits.

Module:8 Contemporary issues 2 hours

Total Lecture Hours: 45 hours

Text Book(s)
1. Neil H.Weste, Harris, A. Banerjee, CMOS VLSI Design, A circuits and System
Perspective, 2015, 4th Edition, Pearson Education, Noida, India.
Reference Book
1. Jan M. Rabaey, Anantha Chadrakasan, Borivoje Nikolic, Digital Integrated Circuits: A
Design Perspective Paperback, 2016, 2rd Edition, Pearson Education, India.
2. Sung-Mo Kang, Yusuf Liblebici, Chulwoo Kim, CMOS Digital Integrated Circuits:
Analysis and Design, 2019, Revised 4th Edition, Tata Mc Graw Hill, New Delhi, India.

Mode of Evaluation: Continuous Assessment Test, Digital Assignment, Quiz and Final
Assessment Test
Recommended by Board of Studies 14-05-2022
Approved by Academic Council No. 66 Date 16-06-2022

Proceedings of the 66th Academic Council (16.06.2022) 405

 BECE303L
VLSI System Design
Module 1

Introduction
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

1
© Digital
EE141 Integrated Circuits2nd Introduction
 What is this course all about?
 Introduction to digital integrated circuits.
 CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay,
noise margins, and power dissipation.
Combinatorial Circuits and Sequential circuits.
Computer-Aided Design.
 What will you learn?
 Understanding, designing, and optimizing digital
circuits with respect to different quality metrics:
speed, power dissipation, cost, and reliability

2
© Digital
EE141 Integrated Circuits2nd Introduction
 Overview of the Course
 Introduction: Issues in digital integrated circuit (IC)
design
 Device: MOS Transistors
 Wire: R, L and C
 Fabrication process
 CMOS inverter
 Combinational logic structures
 Sequential logic gates
 Design methodologies
 VLSI Computer-Aided Design
 Timing/power optimizations on gate and interconnect

3
© Digital
EE141 Integrated Circuits2nd Introduction
 Introduction
 Why is designing
digital ICs different
today than it was
before?
 What is the
challenge?

4
© Digital
EE141 Integrated Circuits2nd Introduction
 The Transistor Revolution

First transistor
Bell Labs, 1948

© Digital
EE141 Integrated Circuits2nd Introduction
 The First Integrated Circuit

First IC
Jack Kilby
Texas Instruments
1958

© Digital
EE141 Integrated Circuits2nd Introduction
 Intel 4004 Micro-Processor

1971
1000 transistors
1 MHz operation

7
© Digital
EE141 Integrated Circuits2nd Introduction
 Intel 8080 Micro-Processor
1974
4500 transistors

© Digital
EE141 Integrated Circuits2nd Introduction
 Intel Pentium (IV) microprocessor

2000
42 million transistors
1.5 GHz

9
© Digital
EE141 Integrated Circuits2nd Introduction
Modern Chip

© Digital
EE141 Integrated Circuits2nd Introduction
 Moore’s Law
In1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.

11
© Digital
EE141 Integrated Circuits2nd Introduction
 Moore’s law
Twice the
number of
transistors,
approximately
every two
years

© Digital
EE141 Integrated Circuits2nd Introduction
© Digital
EE141 Integrated
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Circuits2nd
1959
1960
Moore’s Law

1961

Electronics, April 19, 1965.

1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
13
Introduction
 Transistor Counts
1 Billion
K Transistors
1,000,000

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
14
© Digital
EE141 Integrated Circuits2nd Courtesy, Intel Introduction
 ITRS Prediction

15
© Digital
EE141 Integrated Circuits2nd Introduction
 Moore’s law in Microprocessors
1000

100 2X growth in 1.96 years!

Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
Transistors
0.01 on Lead Microprocessors double every 2 years
8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

16
© Digital
EE141 Integrated Circuits2nd Courtesy, Intel Introduction
 Not true
Frequency any more!
10000
Doubles every
1000
2 years
Frequency (Mhz)

100 P6
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years

17
© Digital
EE141 Integrated Circuits2nd Courtesy, Intel Introduction
 Interconnects Dominate

300
250
Delay (psec)

200 Interconnect delay

150
100
50 Transistor/Gate delay

0
0.8 0.5 0.35 0.25
Technology generation (m)

Source: Gordon Moore, Chairman Emeritus, Intel Corp.

18
© Digital
EE141 Integrated Circuits2nd Introduction
 Power Dissipation
100
P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Lead Microprocessors power continues to increase

19
© Digital
EE141 Integrated Circuits2nd Courtesy, Intel Introduction
 Power is a major problem
100000
18KW
10000 5KW
1.5KW
Power (Watts)

1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year

Power delivery and dissipation will be prohibitive

20
© Digital
EE141 Integrated Circuits2nd Courtesy, Intel Introduction
 Power density
10000
Rocket
Power Density (W/cm2)

Nozzle
1000
Nuclear
Reactor
100

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

Power density too high to keep junctions at low temp

21
© Digital
EE141 Integrated Circuits2nd Courtesy, Intel Introduction
 Not Only Microprocessors
Cell
Phone

Small Power
Signal RF RF

Digital Cellular Market

(Phones Shipped) Power
Management

1996 1997 1998 1999 2000

Analog
Units 48M 86M 162M 260M 435M Baseband

Digital Baseband
(DSP + MCU)

(data from Texas Instruments)

22
© Digital
EE141 Integrated Circuits2nd Introduction
 Many Chips

23
© Digital
EE141 Integrated Circuits2nd Introduction
 Challenges in Digital Design

• Ultra-high speed design

• Interconnect delay
• Reliability, Manufacturability
• Power Dissipation
• Time to market

24
© Digital
EE141 Integrated Circuits2nd Introduction
 Productivity Trends
Logic Transistor per Chip (M)
10,000
10,000,000 100,000
100,000,000
1,000 Logic Tr./Chip 10,000
1,000,000 10,000,000

(K) Trans./Staff - Mo.

Tr./Staff Month.
100 1,000
Complexity

100,000 1,000,000

Productivity
10 58%/Yr. compounded 100
10,000 Complexity growth rate 100,000

1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
xx Productivity growth rate
x
0.01
10 0.1
100

0.001
1 0.01
10
1983

1993
1995

2005
1981

1985
1987
1989
1991

1997
1999
2001
2003

2007
2009
Source: Sematech

Complexity outpaces design productivity

25
© Digital
EE141 Integrated Circuits2nd Courtesy, ITRS Roadmap Introduction
 Computer-Aided Design
 Every new generation can integrate 2x more
functions per chip
 Chip price does not increase significantly
 Cost of a function decreases by 2x
 However,
 Design engineering population does not double every
two years.
 How to design much more complex chips (with more
and more functions)?
 Great need for ultra-fast design methods
 Design Automation (Computer-Aided Design)

26
© Digital
EE141 Integrated Circuits2nd Introduction
 Design Abstraction Enables CAD
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

27
© Digital
EE141 Integrated Circuits2nd Introduction
 Design Metrics
 How to evaluate performance of a
digital circuit (gate, block, …)?
 Speed (delay, operating frequency)
 Power dissipation
 Cost
– Design time
– Design effort
 Reliability
– Process, voltage and temperature variations

28
© Digital
EE141 Integrated Circuits2nd Introduction
 Cost of Integrated Circuits
 NRE (non-recurrent engineering) costs
 design time and effort to design layout and
mask
 one-time cost factor
 Recurrent costs
 silicon processing, packaging, test
 proportional to volume
 proportional to chip area

29
© Digital
EE141 Integrated Circuits2nd Introduction
 NRE Cost is Increasing

30
© Digital
EE141 Integrated Circuits2nd Introduction
 Die Cost

Single die

Wafer

Going up to 12” (30cm)

From http://www.amd.com 31
© Digital
EE141 Integrated Circuits2nd Introduction
 Yield
No. of good chips per wafer
Yield  100%
Total number of chips per wafer

Wafer cost
Die cost 
Dies per wafer  Die yield

32
© Digital
EE141 Integrated Circuits2nd Introduction
 Defects


 defects per unit area  die area 
Yield  1  
  

 is approximately 3 in the current fabrication process

About 0.5-1 defect per cm2.

33
© Digital
EE141 Integrated Circuits2nd Introduction
 Some Examples (1994)
Chip Metal Line Wafer Def./ Area Dies/ Yield Die
layers width cost cm2 mm2 wafer cost
386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC 4 0.80 $1700 1.3 121 115 28% $53

601
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

34
© Digital
EE141 Integrated Circuits2nd Introduction
 Summary
 Digital integrated circuit design faces huge
challenges for the coming decades
 High speed
 Low power
 Short design time for highly complex circuit having
1 billion transistors
 Reliable under noise and variations
 Purpose of the course
 Understand the basics of VLSI design
 Getting a clear perspective on the challenges and
potential solutions

35
© Digital
EE141 Integrated Circuits2nd Introduction
Complexity and Design
Creating a design team provides
a realistic approach to
approaching a VLSI project, as it
allows each person to study small
sections of the system
Needing hundreds of engineers,
scientists, and technicians
Needing hierarchy design and
many different “LevelViews”
Everyone of each level depends
upon the Computer-Aided
Design (CAD) tools
Design Hierarchy
System specifications: is defined in both
general and specific terms, such as functions,
speed,size, etc.
Abstract high-level model: contains
information on the behavior of each block and
the interaction among the blocks in the system
Logic synthesis: To provide the logic design of
the network by specifying the primitive gates
and units needed to build each unit
Circuit design: where transistors are used as
switches and Boolean variables are treated as
vary voltage signals
Physical design: the network is built on a tiny
area on a slice of silicon
Manufacturing: a completed design process is
moved on tothe manufacturing line
Design Hierarchy
Hierarchical design
Top-down design

The initial work is quite abstract and theoretical and there is no

direct connection to silicon until many steps have been
completed
Acceptable in modern digital system design
Co-design with combining HW/SW is critical
Similar to Cell-based DesignFlow

Bottom-up design

starts at the silicon or circuit level and builds primitive units

such as logic gates, adders, and registers as the first steps
Acceptable for smallprojects
Similar to Full-custom DesignFlow
 Design Hierarchy
System Specifications

Abstract high-level model

Logic Synthesis

Circuit Design

Physical Design

Manufacturing

Finished VLSI Chip

Design Hierarchy (Example)
Based on “divide andconquer”
Dividing a module into sub- modules and then
repeating this operation on the sub-modules until the
complexity of the smaller parts becomes manageable.
In fig.,CMOS four-bit adder into its components.
The adder can be decomposed progressively into one-
bit adders, separate carry and sum circuits, and finally,
into individual logic gates. At this lower level of the
hierarchy, the design of a simple circuit realizing a
well-defined Boolean function is much more easier to
handle than at the higher levels of the hierarchy.
VLSI ChipTypes
At the engineering level, digital VLSI chips are classified by the
approach used to implement and build the circuit
Full-custom Design: where every circuit is custom designed for the
project
Extremely tedious
Time-consuming process
Application-Specific Integrated Circuits (ASICs): using an
extensive suite of CAD tools that portray the system design in terms
of standard digital logic constructs
Including state diagrams, functions tables, and logic diagram
Designer does not need any knowledge of the underlying electronics or
the physic of the silicon chip
Major drawback is that all characteristics are set by the architectural
design
Semi-custom Design: between that of a full-custom and ASICs
Using a group of primitive predefined cells as building blocks, called cell
library
Regularity, Modularity and Locality
The hierarchical design approach reduces the design complexity
by dividing the large system into several sub-modules. Usually,
other design concepts and design approaches are also needed to
simplify the process.

1) Regularity:
Decomposition of a large system in simple and similar blocks as
much aspossible.

Example:
Design of array structures consisting of identical
cells - such as a parallel multiplicationarray.
2) Modularity:

Modularity in design means that the various functional blocks

which make up the larger system must have well-defined
functions and interfaces.
Modularity allows that each block or module can be designed
relatively independently fromeach other.
All of the blocks can be combined with ease at the end of the
design process, to form the large system.
The concept of modularity enables the parallelisation of the
design process.

3) Locality:

The concept of locality also ensures that connections are mostly

between neighboring modules, avoiding long-distance
connections as much aspossible.
 BECE303L VLSI System Design

MOS Transistor Device Characteristics

 Outline
■ Introduction
■ MOS Capacitor
■ NMOS I-V Characteristics
■ PMOS I-V Characteristics
■ Gate and Diffusion Capacitance
■ Nonideal Transistor Behavior
■ Process and Environmental Variations
 Introduction
■ So far, we have treated transistors as ideal switches
■ An ON transistor passes a finite amount of current
► Depends on terminal voltages
► Derive current-voltage (I-V) relationships
■ Transistor gate, source, drain all have capacitance
► I = C (DV/Dt) -> Dt = (C/I) DV
► Capacitance and current determine speed
■ Also explore what a “degraded level” really means
 MOS Capacitor
■ Gate and body form MOS capacitor
■ Operating modes
polysilicon gate
► Accumulation Vg < 0
silicon dioxide insulator
+
p-type body
► Depletion -

► Inversion
(a)

0 < V g < Vt
depletion region
+
-

(b)

V g > Vt
inversion region
+
- depletion region

(c)
 Terminal Voltages
■ Mode of operation depends on Vg, Vd, Vs
► Vgs = Vg – Vs
► Vgd = Vg – Vd
► Vds = Vd – Vs = Vgs - Vgd
■ Source and drain are symmetric diffusion terminals
► By convention, source is terminal at lower voltage
► Hence Vds  0
■ NMOS body is grounded. First assume source is 0 too.
■ Three regions of operation
► Cutoff Vg
► Linear
+ +
► Saturation Vgs Vgd
- -
Vs Vd
-
Vds +
 NMOS Cutoff
■ No channel
■ Ids = 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b
 NMOS Linear
Vgs > Vt
Vgd = Vgs
+ g +
- -
s d
■ Channel forms n+ n+ Vds = 0

■ Current flows from d to s p-type body

► e- from s to d
b
■ Ids increases with Vds
■ Similar to linear resistor Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b
 NMOS Saturation
■ Channel pinches off
■ Ids independent of Vds
■ We say current saturates
■ Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b
 I-V Characteristics
■ In Linear region, Ids depends on
► How much charge is in the channel?
► How fast is the charge moving?
 Channel Charge
■ MOS structure looks like parallel plate capacitor while
operating in inversion
► Gate – oxide – channel
■ Qchannel = CV
■ C = Cg = eoxWL/tox = CoxWL
■ V = Vgc – Vt = (Vgs – Vds/2) – Vt

polysilicon
gate
W gate
tox Vg
L SiO2 gate oxide
+ +
n+ n+

p-type body
(good insulator, eox = 3.9)
source Vgs Cg Vgd drain
Vs - channe - Vd
n+ - l + n+
Vds
p-type body
 Carrier velocity
■ Charge is carried by e-
■ Carrier velocity v proportional to lateral E-field
between source and drain
■ v = mE (m is called mobility)
■ E = Vds/L
■ Time for carrier to cross channel:
►t=L/v
 NMOS Linear I-V
■ Now we know
► How much charge Qchannel is in the channel
► How much time t each carrier takes to cross

Qchannel
I ds 
t
 mCox
WV  V  Vds V
 gs t  ds

L 2 

  Vgs  Vt 
Vds  W
 Vds  = mCox
 2 L
 NMOS Saturation I-V
■ If Vgd < Vt, channel pinches off near drain
► When Vds > Vdsat = Vgs – Vt
■ Now drain voltage no longer increases current

I ds   Vgs  Vt  dsat V
V
 dsat
 2 

  Vt 
2
 V gs
2
 NMOS I-V Summary
■ Shockley 1st order transistor models (long-channel)


 0 Vgs  Vt cutoff

  V V V  V
I ds    Vgs  Vt  ds  ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2
 Example
■ We consider a 0.6 mm process
► From AMI Semiconductor
► tox = 100 Å 2.5
Vgs = 5

► m = 350 cm2/V*s 2

► Vt = 0.7 V 1.5 Vgs = 4

Ids (mA)
■ Plot Ids vs. Vds 1
Vgs = 3
► Vgs = 0, 1, 2, 3, 4, 5
0.5
► Use W/L = 4/2 l
Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
Vds

W  3.9  8.85  1014   W  W

  mCox   350  8  L   120 m A / V 2

L  100  10   L
 PMOS I-V
■ All dopings and voltages are inverted for PMOS
■ Mobility mp is determined by holes
► Typically 2-3x lower than that of electrons mn
► 120 cm 2/V*s in AMI 0.6 mm process
■ Thus PMOS must be wider to provide same current
► In this class, assume mn / mp = 2
► *** plot I-V here
 PMOS I-V Summary

 first order transistor models


 0 Vgs  Vt cutoff

  V V V  V
I ds    Vgs  Vt  ds  ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2
I-V characteristics of pMOS
Transistor
 Capacitance
■ Any two conductors separated by an insulator have
capacitance
■ Gate to channel capacitor is very important
► Creates channel charge necessary for operation
■ Source and drain have capacitance to body
► Across reverse-biased diodes
► Called diffusion capacitance because it is associated with
source/drain diffusion

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, eox = 3.9e0)
p-type body
 Gate Capacitance
■ Approximate channel as connected to source
■ Cgs = eoxWL/tox = CoxWL = CpermicronW (minimum L)
■ Cpermicron is typically about 2 fF/mm
 Let’s call CoxWL = C0
 When the transistor is on, the channel extends from the source
to the drain (if the transistor is unsaturated, or to the pinchoff
point otherwise)
Cg = Cgb + Cgs + Cgd
Gate Capacitance

In reality the gate overlaps source and

drain. Thus, the gate capacitance should
include not only the intrinsic capacitance
but also parasitic overlap capacitances:
Cgs(overlap) = Cox W LD
Cgs(overlap) = Cox W LD
 Detailed Gate Capacitance
Capacitance Cutoff Linear Saturation
Cgb (total) C0 0 0
Cgd (total) CoxWLD C0/2 + CoxWLD CoxWLD
Cgs (total) CoxWLD C0/2 + CoxWLD 2/3 C0+ CoxWLD

Source: M-S Kang, Y. Leblebici,

CMOS Digital ICs, 3/e,
2003, McGraw-Hill
 Diffusion Capacitance
■ Csb, Cdb
■ Undesirable, called parasitic capacitance
■ Capacitance depends on area and perimeter
► Use small diffusion nodes
► Comparable to Cg
for contacted diff
► ½ Cg for uncontacted
► Varies with process
Lumped representation of the
MOSFET capacitances
ΦF is the difference between intrinsic Fermi
level (Ei) and Fermi level (EF).
ΦS- work fuction of semiconductors
 Ideal vs. Simulated nMOS I-V Plot
■ 65 nm IBM process, VDD = 1.0 V

Ids (mA)

Simulated
Vgs = 1.0
Ideal
1200
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

1000
Ion = 747 mA @
Channel length modulation: V = V = V
gs ds DD
Saturation current increases
800 with Vds Vgs = 1.0

Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Vgs = 0.8
Saturation current increases less than
400 quadratically with Vgs

Vgs = 0.6
200 Vgs = 0.6
Vgs = 0.4
0 Vds
0 0.2 0.4 0.6 0.8 1
 ON and OFF Current
Ids (mA)
■ Ion = Ids @ Vgs = Vds = VDD 1000
Ion = 747 mA @
Vgs = Vds = VDD
► Saturation 800 Vgs = 1.0

600

Vgs = 0.8

400

■ Ioff = Ids @ Vgs = 0, Vds = VDD Vgs = 0.6

200
► Cutoff Vgs = 0.4

0 Vds
0 0.2 0.4 0.6 0.8 1
 Electric Fields Effects
■ Vertical electric field: Evert = Vgs / tox
► Attracts carriers into channel
► Long channel: Qchannel  Evert
■ Lateral electric field: Elat = Vds / L
► Accelerates carriers from drain to source
► Long channel: v = mElat
 Mobility Degradation
■ High Evert effectively reduces mobility
► Collisions with oxide interface
 Velocity Saturation
■ At high Elat, carrier velocity rolls off
► Carriers scatter off atoms in silicon lattice
► Velocity reaches vsat
▼ Electrons: 107 cm/s
▼ Holes: 8 x 106 cm/s
► Better model
 Velocity Sat I-V Effects
■ Ideal transistor ON current increases with VDD2
W Vgs  Vt 
2

 Vgs  Vt 
2
I ds  mCox
L 2 2
■ Velocity-saturated ON current increases with VDD
I ds  CoxW Vgs  Vt  vmax

■ Real transistors are partially velocity saturated

► Approximate with a-power law model
► Ids  VDDa
► 1 < a < 2 determined empirically (≈ 1.3 for 65 nm)
 a-Power Model
 0 Vgs  Vt cutoff

  Vt 
a
 I dsat  Pc V
 Vds gs
I ds   I dsat Vds  Vdsat linear 2
 Vdsat
Vdsat  Pv Vgs  Vt 
a /2

 I dsat Vds  Vdsat saturation
 Channel Length Modulation
■ Reverse-biased p-n junctions form a depletion region
► Region between n and p with no carriers
► Width of depletion Ld region grows with reverse bias
► Leff = L – Ld
■ Shorter Leff gives more current
► Ids increases with Vds
► Even in saturation
GND VDD VDD
Source Gate Drain
Depletion Region
Width: Ld

n L n
+ Leff +
p GND bulk Si
 Channel Length Modulation

  Vt  1  lVds 
2
I ds  V gs
2
■ l = channel length modulation coefficient
► not feature size
► Empirically fit to I-V characteristics
 Threshold Voltage Effects
■ Vt is Vgs for which the channel starts to invert
■ Ideal models assumed Vt is constant
■ Really depends (weakly) on almost everything
else:
► Body voltage: Body Effect
► Drain voltage: Drain-Induced Barrier Lowering
► Channel length: Short Channel Effect
 Body Effect
■ Body is a fourth transistor terminal
■ Vsb affects the charge required to invert the channel
► Increasing Vs or decreasing Vb increases Vt
Vt  Vt 0  g  fs  Vsb  fs 
■ fs = surface potential at threshold
NA
fs  2vT ln
ni
► Depends on doping level NA
► And intrinsic carrier concentration ni
■ g = body effect coefficient

tox 2qe si N A
g 2qe si N A 
e ox Cox
 Short Channel Effect
■ In small transistors, source/drain depletion
regions extend into the channel
► Impacts the amount of charge required to invert the channel
► And thus makes Vt a function of channel length
■ Short channel effect: Vt increases with L
► Some processes exhibit a reverse short channel effect in
which Vt decreases with L

Drain-Induced Barrier Lowering or DIBL:

In a short-channel device, the drain junction is now quite close to the source
junction. As a consequence, the potential at the source-channel region is
determined not only by the gate voltage, but also the drain voltage. The drain
voltage can cause a lowering of the barrier at the source end of the channel,
causing current to flow for a lower vale of gate voltage. This effect is called
Drain-Induced Barrier Lowering or DIBL (pronounced “dibble”)
 Leakage
■ What about current in cutoff?
■ Simulated results
■ What differs?
► Current doesn’t
go to 0 in cutoff
 Leakage Sources
■ Subthreshold conduction
► Transistors can’t abruptly turn ON or OFF
► Dominant source in contemporary transistors
■ Gate leakage
► Tunneling through ultrathin gate dielectric
■ Junction leakage
► Reverse-biased PN junction diode current
 Subthreshold Leakage
■ Subthreshold leakage exponential with Vgs
Vgs Vt 0 Vds  kg Vsb
 Vds

I ds  I ds 0e nvT
1  e vT

 
 
■ n is process dependent
► typically 1.3-1.7
■ Rewrite relative to Ioff on log scale

■ S ≈ 100 mV/decade @ room temperature

 Gate Leakage
■ Carriers tunnel thorough very thin gate oxides
■ Exponentially sensitive to tox and VDD

► A and B are tech constants

► Greater for electrons
▼ So nMOS gates leak more

From
■ Negligible for older processes (tox > 20 Å) [Song01]

■ Critically important at 65 nm and below (tox ≈

10.5 Å)
 Junction Leakage
■ Reverse-biased p-n junctions have some leakage
► Ordinary diode leakage
 VvD 
► Band-to-band tunneling (BTBT) I D  I S  e T  1
 
► Gate-induced drain leakage (GIDL)  
■ Is depends on doping levels
► And area and perimeter of diffusion regions
► Typically < 1 fA/mm2 (negligible)

p+ n+ n+ p+ p+ n+

n well
p substrate
 Temperature Sensitivity
■ Increasing temperature
► Reduces mobility
► Reduces Vt
■ ION decreases with temperature
■ IOFF increases with temperature

I ds

increasing
temperature

Vgs
 So What?
■ So what if transistors are not ideal?
► They still behave like switches.
■ But these effects matter for…
► Supply voltage choice
► Logical effort
► Quiescent power consumption
► Pass transistors
► Temperature of operation
 Parameter Variation
■ Transistors have uncertainty in parameters
► Process: Leff, Vt, tox of nMOS and pMOS
► Vary around typical (T) values
■ Fast (F)
► Leff: short

fast
► Vt: low FF
SF
► tox: thin
■ Slow (S): opposite

pMOS
TT

■ Not all parameters are independent

for nMOS and pMOS FS
SS

slow
slow fast
nMOS
 Environmental Variation
■ VDD and T also vary in time and space
■ Fast:
► VDD: high
► T: low

Corner Voltage Temperature

F 1.98 0C
T 1.8 70 C
S 1.62 125 C
 Process Corners
■ Process corners describe worst case variations
► If a design works in all corners, it will probably work for any
variation.
■ Describe corner with four letters (T, F, S)
► nMOS speed
► pMOS speed
► Voltage
► Temperature
 Important Corners
■ Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthreshold F F F S
leakage