=~. Se 2 Crpress SSF Semicon Features * Advanced second generation PAL architecture ‘+ Low power 55 mA max “L" 90 mA max standard — 120 mA max military © CMOS EPROM technology for reprogrammability © Variable product terms = 2% G thru 16) product, terms '* User programmable macro cell = Output polarity control — Individually selectable for registered or combinatorial operation — “15” commercial & industrial 10 ns to. 10 ns ts, 15 ns tpp, 50 MHz PAL C 22V10B/PAL C 22V10 IDUCTOR — 20" military 15 ns tco Insts 20 ns tep 31 MHz ‘© Up to 22 input terms and 10 ‘outputs ‘© Enhanced test features — Phantom array = Top Test — Bottom Test = Preload © High reliability — Proven EPROM technology = 100% programming and functional testing ‘* Windowed DIP, windowed LOC, DIP, LCC, PLCC available Reprogrammable CMOS PAL® Device Functional Description ‘The Cypress PAL C 22V10 is a CMOS second generation Programmable Log- ic Array device. Its implemented with the familiar sum-of-products (AND- OR) logic structure and a new concept, the “Programmable Macro Cell” ‘The PAL C22V10 is executed in a 24 pin 300 mil molded DIP, a 300 mil windowed Cerdip, a 28 lead square ce- ramic leadless chip carrier, a 28 lead square plastic leaded chip carrier and provides up to 22 inputs and 10 out- puts. When the windowed CERDIP is exposed to UV light, the 22V 10 is erased and then can be reprogrammed. The Programmable Macro Cell pro- Vides the capability of defining the ar chitecture of each output individually. Each of the 10 potential outputs may be specified to be “REGISTERED" or “COMBINATORIAL”. Polarity of PALS i repateedtrademar: of Monolithic Memorss Inc Logic Symbol and Pinout fom oa he oo ao 4 KH yO i ¥_¥ ORY EY EYEUBY LCC and PLCC Pinout 453Functional Description (Continued) ‘each output may also be individually selected allowing. ‘complete lexibility of output configuration, Further con- figurability is provided through “ARRAY” configurable “OUTPUT ENABLE" for cach potential output. This fea~ ture allows the 10 outputs to be reconfigured as inputs on. ‘an individual basis or alternately used as a combination 1/0 controlled by the programmable array. The PAL C 22V10 features a “VARIABLE PRODUCT TERM" architecture, There are 5 pairs of product terms beginning at 8 product terms per output and incrementing by 2to 16 product terms per output. By providing this variable structure the PAL C 22V10 is optimized to the configurations found in a majority of applications without treating devices that burden the product term structures. With unuseable product terms and lower performance. Additional features of the Cypress PAL C 22V 10 include a synchronous PRESET and an asynchronous RESET prod- Lt term. These product terms are common to all MACRO CELLS eliminating the need to dedicate standard product terms for initialization functions. The device automatically resets on power-up. ‘The PAL € 22V10 featuring programmable macro cells and variable product terms provides a device with the flexi bility to implement logic functions in the 500 to 800 gate array complexity. Since each of the 10 output pins may be individually configured as inputs on a temporary or perma- nent basis, functions requiring up to 21 inputs and only a Single output down to 12 inputs and 10 outputs are possi- ble. The 10 potential outputs are enabled through the use of product terms. Any output pin may be permanently se- lected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. Each of these outputs is achieved through an individual programmable macro cell These macro cells are programmable to provide a combina- torial or registered inverting or non-inverting output, In a Macrocell PAL C 22V10B/PAL C 22V10 registered mode of operation, the output of the register is, fed back into the array providing current status informa: tion to the array. This information is available for estab lishing the next result in applications such as control-state~ ‘machines, In @ combinatorial configuration, the combina- torial output of if the output is disabled, the signal present ‘on the I/O pin is made available 1o the array. The Nexibili- ty provided by both programmable macro cell product term control ofthe outputs and variable product terms allows a significant gain in functional density through the use of programmable logic. ‘Along with this increase in functional density, the Cypress PAL C 22V10 provides lower power operation thru the use of CMOS technology, increased testability with a register preload feature and guaranteed AC performance through the use of a phantom array. This phantom array (Po~P3) and the “TOP TEST" and “BOTTOM TEST™ features al- Tow the 22V10 to be programmed with a test pattern and tested prior to shipment for full AC specifications without using any of the functionality of the device specified for the product application, In addition, this same phantom array ‘may be used to test the PAL C 22V10 at incoming inspec- tion before committing the device to a specific function through programming. PRELOAD facilitates testing pro- grammed devices by loading initial values into the regis- ters. Configuration Table 1 Registered/Combinatorial Cc &o Configuration Registered /Active Low ‘Combinatorial/ Active Low ‘Combinatorial/Active High 0 1 Registered/Active High 0 1 nourras PAL C 22V10B/PAL C 22V10 BABS oucree Selection Guide Generic loc mA tp ns, tgs to ns ] PartNamber_[st* [Com/ing [Mit [~Com/toa [Mit_| Com/tnd_[ Mil | Coming | Mi nvion-1s 30 = 5 = 10 = 10 22V108-20 = 100 = 20 = 7 = 8 z2v10-20 9% = 20 = 2 = 2 = mvi02s Ea 30 i 25 35 5 ie 15 i 22V10-30 = 100) = 30 20 = 20 2210.35, 3 | 3% = E = 35 = 22V10-40, = 100 = 0 = xo | 25 ‘Maximum Ratings (Above which the useful life may be impaired, For user guidelines, not tested.) Storage Temperature 68°C 10 + 150°C DC Programming Voltage PALCIIVI0B. ov Ambient Temperature with Power Applied -ssctotnsc — PALC2VI0 Mov Supply Voltage to Ground Potential Latchup Current >200mA Gin toPn 2) =05Vt0+70V Operating Range DC Voltage Applied o Outputs aan in igh ZStaters -05V 10 +70¥ Range amie Vee DC Input Voltage «.... -30Vi0+70V Soap Ourpat Current into Outputs (Low) Gan fae esc are asc Vis on UV Exposure 7258 Wsee/em Tnawtrad | aC vane [sv +108 Electrical Characteristics Over Operating Rangel [Parameters] Deseroton “est Conditions Min, [Max [Cai on Joutpursttatt vonage [¥oo= Min, "lon = —32maCOMIL/IND | : Mi = YiterVi_ [oy = —2ma HIGH Laaicwos — |¥oc = Min, — = Nonz _[ourper Votiget Vig = VinorVn_HOH = ~100 na Receuee| ; Tiéma [conven SSS eo o Vin = Vinor¥in_ [lon = 12ma [MIL ost Nur [tnpat HIGH Level [Guaranteed Top Logical HIGH Vollage for All Input’ [70 v i. input LOW Level [Guaranteed Input Logical LOW Valge for All input os fv Ix [Input Leakage Current 5s = Vin © Vou Voc = Max =i0 | 10 baa ltoz Output Leakage Current [Veo = Max. Vos = Vour = Voc 40 [40 [wa sc | Outpa Shore Creuit Current] Voc = Max, Vour = 05Vi23) “0 | =99] ma c 35 [ma cor [Standby Power ce = Mas, Vin = GND Outputs Open [COMLAND 90 | ma Supply Current or Unprogrammed Device MIL 100 [ma _ MIL20 100 ma Ih Operating Power Fae a [COM'LAND 5 30 [ma 1oct | sappy Current vice Programmed with Worst Case : i [emus Patter, Outputs Testated a 100 [ ma Som 1 "Te arbre ves with pect ode ground and allover, Figur Jo et ond ed ol rants ce te. and shoots ue to system o® tse none are eluded Not more than one ouput shouldbe fest ata tine Duration ofthe short teu should not be more than one texans. Vou = O5V has ‘been chosen osvoi text problem cauned by tester ground degrada Tested initially and after any desi o proces changes that may affet these parameters 455 fpxe. Piture Tb test load sed for teas tom re aan, 5 See the lst page ofthis specfestion for Group A subg testing 6. Taste “instanton