Preparatory Guidebook for Comprehensive Examination
QUESTION BANK
Digital Logic
The minimum time for which the input data signal of the flip-flop should not change after passing of the
clock edge is called ________ of the flip-flop.
A. Set-up time
B. Hold time
C. Pulse interval time
D. Pulse stability time
Which of the following circuits has the longest propagation delay?
A. 4-bit ripple carry adder
B. 4-bit carry look-ahead adder
C. 2:1 Multiplexer
D. 1:2 Decoder
______ selects one of the many input signals and forwards the selected input to the single output. The
binary address of the input selected appears at its select lines.
A. Decoder
B. MUX
C. De-MUX
D. Encoder
LUT is an acronym for
A. Look Up Table
B. Local User Terminal
C. Least Upper Timer
D. None of the above
Any given Boolean expression can be implemented by using
A. Only OR gate
B. Only NOR gate
C. Only XOR gate
D. Only AND gate
The binary equivalent of decimal number 0.4375 is
A. 0.0111
B. 0.1011
C. 0.1100
D. 0.1010
The decimal equivalent of binary number 101.101 is
A. 5.6249
B. 5.625
C. 5.5
D. 5.25
If negative numbers are stored in 2's complement form, the range of numbers that can be stored in 8
bits is
A. -128 to +128
B. -128 to +127
C. -127 to +128
D. -127 to +127
Which of the following 4-bit number equals its 2’s complement?
A. 1010
B. 0101
C. 1000
D. No such number exists
FFFF will be the last memory location in a memory of size
A. 16K
B. 32K
C. 64K
D. 128K
How many minimum number of selection bits (control bits) are required to control a 34:1 multiplexer?
i.e. The multiplexer has 34 inputs and 1 output.
A. 5
B. 6
C. 7
D. 8
Any multiplexer of N:1 can be constructed using a 2:1 multiplexer. How many minimum numbers of 2:1
multiplexers are required to construct a 32:1 multiplexer?
A. 8
B. 15
C. 16
D. 31
To expand a 4-bit parallel adder to an 8-bit parallel adder, you must use
A. Four 4-bit adders with no interconnection
B. Two 4-bit adders and connect the sum output of one to the bit inputs of the other.
C. Eight 4-bit adders with no interconnection
D. Two 4-bit adders with carry out of one to be connected to carry out of another.
A memory block consists of total 512 bytes. If the address bus of this memory block is only 7-bit wide,
how much wide should be the data bus to access the entire memory?
A. 8-bit wide
B. 16-bit wide
C. 24-bit wide
D. 32-bit wide
The Boolean expression
AB + AB’ + A’C + AC
Is unaffected by the value of which Boolean variable
A. A
B. B
C. C
D. None of the above
Which gate is built using the least number of transistors?
A. Buffer
B. NAND gate
C. Inverter
D. AND gate
A memory block consists of total 2048 bytes. If the data bus of this memory block is 64-bit wide, how
much wide should be the address bus to access the entire memory?
A. 7-bit wide
B. 8-bit wide
C. 9-bit wide
D. 10-bit wide
Which gate is built using the least number of transistors?
A. XOR gate
B. XNOR gate
C. OR gate
D. NOR gate
2’s complement of any binary number can be calculated by
A. Adding 1’s complement twice
B. Adding 1 to 1’s complement
C. Subtracting 1 from 1’s complement
D. Calculating 1’s complement and inverting most significant bit.
The decimal “17” in BCD will be represented as
A. 11101
B. 11011
C. 10111
D. 11110
