Indian Institute of Technology, Kharagpur -721302
End-Semester
Date: April 2016 ; Time: 3 hours; Full Marks: 50~ Number of Students 245
Spring Semester, 2015-2016; Department: E & ECE; II year B. Tech.
Subject no. EC 21008 Subject name: Analog Electronic Circuits
lnstructionj Answer ALL questions and in the same order of the questions. Wherever it is necessary, you may
use assumption(s) with reasonable justification.
Common Information: Unless otherwise it is specified in question, use the following values of different device
parameters:
For n-p-n transistor, VBE(on):::0.6
V, VCE(sat):::
0.3 V, ~F =100, VA= 100 V
For p-n-p transistor, VEB(on):::0.6
V, VEC(sat):::
0.3 V, ~F =100, VA= 100 V
For n-MOS and p-MOS enhancement transistors, the trans-conductance factor, K = 1mA/V2,I Vth I=1 V, A=O.Ol V·l
0.1. For the circuit given in Fig.La, Vdd
(i) Find d.c. operating point of the transistor.
(ii)Find the values of trans-impedance and input impedance of 10 ~F
(---0
the amplifier in mid-frequency range when the switch SW is
closed. ~
(iii)Find the values of transconductance and voltage gain
amplifier in mid-frequency range when the switch is open 10 ~lF
[2 +4+4]
-- --
Fig. La
OR
For the circuit given in Fig.Lb,
(i) Find the d.c. operating point of all the transistors, (ii)Find the
small signal voltage gain, input impedance and output impedance in
mid-frequency range,
(iii) Find the output voltage Vout in terms of the input voltage v..
[Given: RGI= 10 kG, RG2= 20 kG, Ro= 10 kG, RL= 1 kG, Rs= 1 kG, Cl =
C2= C3 = lllF, Iref = 0.15mA, Vdd = 10V, For d.c. condition, you may
approximate {1 +AIVosl)::: 1]
[2 +6+2]
Fig.1.b
0.2. Circuit diagram of a feedback system is shown in Fig. 2.a. The input signal Vs = 0.2 Sin{wt) Volts.
(i) Find the output voltage Vo when the switch SWl is closed but the switch SW2 is open.
(ii) Find the feedback voltage Vf and the output voltage Vo when both the switched SWl and SW2 are open.
(iii) Find the output voltage Vo when the switch SWl is open but the switch SW2 is closed. [4+4+2]
p.T. 0 .
(i)
?R.I9/)/P MAN VAL
MRIG;, fiN I<., SHIi P,.t1..b
L
r-------------------------l ,,
,
1- ~
Fig.2.a
OR
Q.2. The circuit in fig.2.b acts like a trans-impedance amplifier. The first stage has the input device MI, which is
biased with a DC current of IOO~A. The input terminal faces a relatively large capacitor Cin. The input source
provides a pulsed current waveform with ION = 25~A and IOFF = O. MI has been sized up to minimize the
input resistance of the first stage and to keep the pole corresponding to node A at sufficiently high frequency.
A Common-Source amplifier with M6 as the input device, constitutes the 2nd stage. The W/l ratio of all the
transistors are marked in the figure (l= Ium for all devices). For transistors use uncox = ~pCox = 5 mA/V2, A =0,
Vtn = [Vtp] = 2V, Cgs = 5pF/~m2, Cgd = 2pF/ urnz, Cdb= Csb ~ O. Vdd = lOV.
(i) Ignoring small signal swing at nodes A and B, for a DC bias current of IOO~A in MI, find the minimum gate
voltages VgI and Vg2, to keep MI, M2 in saturation. Hence, determine the ratio RgI:Rg2:Rg3.
(ii) Considering the case of lin = ION, find the VSG drop for M3. Using this information, and for the values of VgI
and Vg2 determined above, find the minimum Vdd needed to keep all transistors in the first stage in saturation.
(iii) Find the high frequency poles at nodes A, Band C.
(iv) Find the value of Rd such that the pole a node D is equal to the lowest of the three poles calculated in part
(c).
[3+2+3+2]
Fig.l.b
0.3. The circuit given in fig. 3.a depicts a differential amplifier with resistive load followed by a differential
2
amplifier with current mirror load. For transistors llse I1nCOX = 5 mA/V , IVAI=50Y, Ytn = [Vtp] = 2Y. The W/L
ratio of all the transistors are marked in the figure (L= Iurn for all devices). Bias current in both stages has been
set to ImA. Rd 1= Rd2 = 10kQ.
Find the expressions for Vo+, Vo- and Vout when
(2 )
51 nd
, (i) Vin+ = Vin - = 5+0.01 Sin(wt) V, hence, report the common mode gain of the 1 and the 2 stage and hence
for the overall circuit.
Fig.3.a
(ii) Vin+ = Vin - = 5+0.01 Sin(wt) V , Rd 1 = 10.05 kn, Rd2 = 10.0 kn, report the overall common-mode gain.
Justify any approximation. [3+7]
ORofQ.3 +5V
2.6 k!2
A fully differential amplifier circuit is shown in Fig. 3.b.
IN1
(i) Find the values of differential mode gain and common mode gain of
the amplifier for OV input quiescent voltage (i.e. V1N1Q =V1NZQ = 0 V).
(ii) For input signals Vinl = -2.2 V and Vin2 = -2.2 + 0.02 Sin(2000nt) V,
find the output voltages of the amplifier.
(4+6)
-5V
Fig 3.b
Q4. For the differential amplifier in Fig. 4, assume that the devices
in the two branches are well matched.
(i) Find the value of Ro so that in d.c. condition (with suitable
input common mode level) 1501 = 2mA. Use this value of Ro for the
subsequent parts.
(ii) Calculate the input common mode range over which all the
transistors remain in saturation region of operation. v.;
M~~
(iii) Draw small signal equivalent circuits of the amplifier for
VOUl
differential mode of operation, derive the expression of
differential mode gain and find its value.
(iv) Draw small signal equivalent circuits of the amplifier for M5JlIS~
common mode of operation derive the expression of common
mode gain and find its value.
Fig.4
[Given: Voo = lOV] [2+2+3+3)
(3)
Q.5 In a negative feedback system, transfer function of the forward amplifier and that of the feedback network
are,
Neatly Sketch the Bode' plots of the loop gain and the feedback system gain. Using asymptotic approximation,
calculate the phase margin and gain margin of the feedback system. Draw the Nyquist diagram of the
feedback system. [5 x 2)
OR
Fig. 5 depicts a feedback amplifier. For transistors use uncox = I1PCOX= O.5E-5 A/V2, I VA I =150V, Cgs =
1pF/l1m2, Cgd = O.5pF/ 11m2,Cdb= Csb ~ O. Vg is a 5V DC source. The W/L ratio of all the transistors are marked
in the figure (L= 111mfor all devices). Vb has been chosen to obtain a bias current of O.2mA in MS. Rf = 10kO.
CI is an external load capacitance of value 20pF. In part (a) to (d), assume Rz and Cc to be absent.
Vdd = 10V
Fig.S
(i) Identify the feedback topology and find the feedback factor B.
(ii) Find the open loop gain, input resistance and output resistance of the open-loop amplifier, considering the
loading effect of the feedback network.
(iii) For the open-loop amplifier (considering the loading effect of the feedback network), find the values of the
dominant and the first non-dominant high frequency poles.
(iv) Assuming only the dominant and first non-dominant pole to be significant, (assuming 2-pole system), find
the phase margin for the loop transfer function A~.
(1+3+3+3)
