EEC110A Win 2010 Final Exam

Prof. Stephen ODriscoll odriscoll@ucdavis.edu March 16th 2010 Duration: 2 hours

Name:

ID #:

Q1 Q2 Q3 Q4 Total

Q1 [60 points: each part, (a) through (f), is worth 10 points] (a)
VCC RC vO + va + 1.7V Q1 RE1 CE1 + vb + 1.7V Q2 RE2 CE2

Figure 1: Circuit for Q1(a).

10 VCC = 15V ; RC = 2.6k; VT = 26mV ; RE1 = RE1 = 101 ; and CE1 and CE2 are BFCs. Transistor Q1 has: = 100, VA = , VBE(ON ) = 0.7V . Transistor Q2 has: = 200, VA = , VBE(ON ) = 0.7V . Note the s are not the same. va (t) = 7V Sin(10t) vb (t) = 3V Sin(10t)
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(i) What is the DC voltage at vO ? (ii) What is the time varying-component of the voltage at vO ?

Q1 (b)
+ VCC R1 Q2 Q1 + VBIAS1 iS BFL VEE + R2 Q3 + VBIAS2 Q4 Q5 R3 R4 vO

Figure 2: Circuit for Q1(b). Assume = , VA = and all transistors are biased to the forward active mode. The BFL looks like a short at DC and an open at mid-band frequencies.
o Find an expression for the midband small-signal transconductance vs in terms of R1 , R2 , i R3 , R4 , gm1 ,gm2 , gm3 , gm4 and gm5 (you may not need to use all of these terms). Simplify your expression as much possible.

Q1 (c)
Amplifier ro + vs + vi + avi + vo L

ri

Figure 3: RC loaded amplier + circuit from part (a). The amplier in Fig. 3 has voltage gain A, innite input resistance and zero output resistance. Suppose a = 111.11, ri = 100k, ro = 1.1111k, R = 10k, C = 10pF and L = 1nH. 1 (i) Find the required value of A such that vo = 100 at f = 2 GHz. Hint: vo = 100 is purely vs vs real, has no imaginary part. For that value of A: (ii) What is the value of vo at f = 0Hz, i.e. DC? vs (iii) What is the value of vo as f ? vs (For part (c) give magnitude not dB.)

Q1 (d)
Forward Amplifier ie io

ii

Ri

aie

Ro

RL

Feedback Network

bio

Figure 4: Ideal shunt-series feedback topology. Assume RL = 0. Find (i) the input resistance, RiCL (ii) output resistance, RoCL (iii) current gain ACL = iio i You will not receive credit for giving the answer only. Derivation is required.

Q1 (e)
VCC

R1 CIN + vi -

RC2

RC2 Q3

RC4 Q5

RC5 Q6 vO

Q1 R2

Q2 RE3 RE2

Q4 RE4

RE1

RF

RE6

Figure 5: Circuit for Q1(e). (i) Identify the feedback topology and explain your answer. (ii) At midband is the feedback positive or negative? Explain your answer.

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Q1 (f)

VDD

Cin

Cin

Cin

VDD

A S A

Cin

Cin

Cin

VDD

Cout

A B Cin

Cout

Figure 6: Subcircuit for Q1(f). The circuit shown inside the dashed box in Fig. 6 is abstracted as a block with three inputs: A; B; Cin ; and two outputs: Cout ; S. 12

Q1 (f)
B0 A0 B1 A1 B2 A2

A B Cin

Cout S

A B Cin

Cout S

A B Cin

Cout S

S0

S1

S2

S3

Figure 7: Circuit for Q1(f). Three of these subcircuits are connected as shown in Fig. 7. (i) All of the signals are represented as Boolean logic levels, i.e. 0 or 1. If A0 = 1, A1 = 1, A2 = 1 and B0 = 1, B1 = 0, B2 = 1 and what are the values of S0 , S1 , S2 and S3 ? (ii) Can you tell what function is implemented by this circuit? Describe as succinctly as possible (no more than one sentence).

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Q2 [30 points] Recall that an ideal opamp has innite input resistance, zero output resistance and innite voltage gain. Therefore an inverting opamp circuit, as shown in Fig. 8, has voltage gain vo = Z2 . vi Z1
Z2 Z1 + vi -

+ Ideal Opamp + vo -

Figure 8: Inverting Opamp Circuit (a) For the circuit in Fig. 9 all components are ideal. The ideal voltage buer has innite input resistance, zero output resistance and its output voltage equals the voltage at the + input terminal minus the voltage at the - input terminal.
C2 R2 + vi + R1 Ideal Voltage Buffer L1 C4 R4 R3 Ideal Opamp

+ Ideal Opamp + vo -

R5

R6

Figure 9: Q2(a) Find A(j) and b in terms of the component values in Fig. 9 such that the model in Fig. 10 has equivalent input-output relationship to the circuit in Fig. 9. Note: If the either the numerator or denominator of A(j) is function of express it as a product of rst order polynomials in j and a constant factor, if necessary, not as a single 2 higher-order polynomial in j e.g. K(1 + j )(1 + j ) not K + j K(+) K 15

Q2

+ vi -

A(j)

+ vo -

Figure 10: Equivalent Model for Q2(a) circuit.

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Q2 (b) Given R1 = R3 = 10, R2 = R4 = 100k, R5 = 999k, R6 = 1k, L1 = 1mH and C2 = C4 = 10pF . (i)Draw a Bode plot showing the magnitude of loop gain, in dB, versus angluar frequency and another showing the phase of of loop gain, in degrees, versus angluar frequency on the box-ruled sheet provided. On both plots clearly label the axes, and mark with values all slopes and all frequencies at which the slope changes. (ii)What is the low frequency loop gain? (iii)What is the unity gain angular frequency, u ? (iv)What is the Gain Margin? (v)What is the Phase Margin? (vi)Is the system stable?

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Q2

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Q2 (c) You can change the value of inductor L1 but you cannot change the value of any other component. (i) What value of L1 would you choose such that the phase margin equals +45 ? (ii) What is the low frequency closed loop gain?

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Q3 [30 points]

VCC

R1 CIN + vS -

RC

CIN vO

Q1 R2 RE CE

RL

Figure 11: Circuit for Q3. CIN , COU T and CE are BFCs. R1 = 40k, R2 = 10k, RE = 222 k,RL = 100, = 100, 101 VBE(ON ) = 0.7V , VCE,sat = 0.2V , VA = , VT = 26mV , rb = 0, VCC = 15V . C = 1pF , C = 0.1pF . (a) (i) Calculate the collector current, IC . (ii) Calculate RC to meet our design rule for maximum unclipped output swing.

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Q3 (b) (i) Draw the high-frequency small signal equivalent circuit. (ii) Estimate cH , the 3dB bandwidth, using the method of open circuit time constants.

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Q3 (c) We want to set cH = 107 by adding one capacitor of as small a value as possible. (i) Between which two nodes would you place that capacitor? (ii) What is the minimum value of capacitance you should use?

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Q4 [30 points] (a) Draw a gate-level schematic using two 2-input N AN D gates and one N OT gate to realize the Boolean expression below: Y = AB + C

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Q4(b) (i) Complete Table 1 for the circuit in Fig. 12

VDD

C P

A C B

Figure 12: Circuit for Q4(b)(i)

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Table 1: Truth table for Q4(b)(i)

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(ii) Complete Table 2 for the circuit in Fig. 13

VDD

Q A

Figure 13: Circuit for Q4(b)(ii)

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Table 2: Truth table for Q4(b)(ii)

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Q4(c)
VDD

Vi

VO
CL

Figure 14: Circuit for Q4(c) Given N = P = 0; N = 2.5p = 0.025m2 V 1 s1 ; CoxN = CoxP = 5 103 F m2 ; LN = LP = 0.1m; WN = 0.3m; WP = 0.75m; VDD = 4V ; VTN = VTP = 1V ; CL = 1pF ; and 0t<0 VDD Vi = at t = 0 2 VDD t > 0 (i) Find the time at which Vo = VDD , i.e. nd tP HL . 2 (ii) Assume the conditions above except now WN = 0.9m. What is the new tP HL ?

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EEC110A Win 2011 Final Exam

Prof. Stephen ODriscoll odriscoll@ucdavis.edu Friday March 18th 2011 Duration: 2 hours
Note: You can apply formulae from the formula sheet or class so long as you write the formulae down. You do not need to derive formulae we have previously derived unless explicitly asked to do so.

Name:

ID #:

Q1 (a) Q1 (b) Q1 (c) Q1 (d) Q2 Q3 Total

/ 10 / 10 / 10 / 10 / 30 / 30 / 100

Q1 [40 points: each part, (a) through (d), is worth 10 points] (a)
VCC RC vO + va + 1.7V Q1 RE1 CE1 + 1.7V ix Q2 LE2 RE2

Figure 1: Circuit for Q1(a).

10 VCC = 10V ; RC = 1k; VT = 25mV ; RE1 = 101 ; RE2 = 1k; CE1 is a BFC; and LE2 is a BFL i.e. a short at DC and an open in small-signal. Transistor Q1 has: 1 = 100, VA = , VBE(ON ) = 0.7V . Transistor Q2 has: 2 = 999, VA = , VBE(ON ) = 0.7V . Note the s are not the same. va (t) = 25V Sin(10t) 1 ix (t) = 999 mA Sin(10t)
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(i) What is the DC voltage at vO ? (ii) What is the time varying-component of the voltage at vO ?

Q1 (b)
VCC RC5

R1 CIN

RC1

RC2 Q3

RC6 vO Q6

Q1 is R2

Q2 RE3

Q5 Q4

RE1

RF

RE6

Figure 2: Circuit for Q1(b). Assume R1 and R2 are much, much larger than all other impedances. (i) Identify the feedback topology and explain your answer. (ii) Assuming that all transistors operate in the forward active region. At midband small signal is the feedback positive or negative? Please explain your answer.

Q1 (c) Draw a gate-level schematic using two 2-input N AN D gates and one N OT gate to realize the Boolean expression below: Y = AB + C

Q1 (d)
VDD

B VO
CL

Figure 3: Circuit for Q1(d). Assuming B is held constant at 0V , that A was held at 0 for a long time prior to t = 0 and that A is instantaneously switched from 0 to VDD at time t = 0: (i) What is the value of VO at time t = 0?

(ii) What is the nal value of VO i.e. at t = ? (iii) Derive an estimate for the time at which VO = 1 VDD in terms of VDD , CL , Kn , Kp , 2 VT p , VT n using similar approximations as we used when estimating the propagation delay of a CMOS inverter.

Q2 [30 points] Contains parts (a) through (c).

VCC

R1 RS + vS CIN

RC

COUT vO RL

Q1 R2 RE CE

Figure 4: Circuit for Q2.

130 CIN , COU T and CE are BFCs. RS = 100, R1 = 8k, R2 = 2k, RE = 101 k, RL = 50, = 100, VBE(ON ) = 0.7V , VCE,sat = 0.2V , VA = , VT = 25mV , rb = 0, VCC = 10V . C = 0.7pF , C = 0.1pF .

(a) Feel free to make any approximations you deem appropriate but be sure to justify them. (i) Calculate the DC collector current, IC , assuming the transistor operates in forward active mode. (ii) Calculate RC to meet our design rule for maximum unclipped output swing. (iii) Is the assumption of forward active mode valid? Explain why or why not.

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Q2 (b) (i) Draw the high-frequency small signal equivalent circuit. (ii) Estimate cH , the 3dB bandwidth, using the Miller approximation and check whether the Miller approximation is valid.

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Q2 (c) We want to set cH = 107 by adding one capacitor of as small a value as possible. (i) Between which two nodes would you place that capacitor? (ii) Continuing to estimate cH using the Miller approximation, what is the value of capacitance you should add?

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Q3 [30 points] Contains parts (a) through (d).

RS + vs + vi -

Feedforward Amplifier

R2 + a1vi + vint R3 C3

R4 + a2vint CL + vo -

R1

C1

RL

Feedback Amplifier

+ bvo -

Figure 5: Circuit for Q3. Consider the circuit in Fig. 5. All components are ideal. (a) What type of feedback topology is this? (i.e. Series-Series, Series-Shunt, Shunt-Series, or Shunt-Shunt)

in (b) Express the open loop voltage gain with respect to vi (not vs ) i.e. AOLi = vo vi b=0 terms of the variables shown in Fig. 5. Note: If the either the numerator or denominator of A(j) is function of express it as a product of rst order polynomials in j and a constant factor, if necessary, not as a single 2 higher-order polynomial in j e.g. K(1 + j )(1 + j ) not K + j K(+) K .

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Q3 (c) RS = 50, R1 = 50, R2 = 100, R3 = 100k, R4 = 20, RL = 20, C1 = 100F , b0 where b0 = 102 , C3 = 1F , CL = 10nF , a1 = 2 109 , a2 = 1, and b =
1+j

b = 10 rad/s. (i) Draw Bode plots showing the magnitude of loop gain Li = AOLi b, in dB, versus angluar frequency and another showing the phase of loop gain, in degrees, versus angluar frequency on the box-ruled sheet provided. On both plots clearly label the axes, and mark with values all slopes and all frequencies at which the slope changes. (ii) What is the low frequency loop gain?

(iii) What is the unity gain angular frequency, u ?

(vi) What is the Phase Margin?

(v) Is the system stable?

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Q3

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Q3 (d) We would like a phase margin of +45 . You can change the value of any one capacitor. (i) Which capacitor would you choose to change and why?

(ii) What new value would you choose for that capacitor?

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Name______________________________ Student ID__________________________ 1. Modeling with Verilog

Page 1

Write the Verilog description for a round-robin bus arbiter, which regulates the access of four modules to a shared bus. Each module will have to issue its own request signal to indicate the need to access the bus. The arbiter will issue a grant signal in response to a request, ensuring that exactly one of the requester is granted access to the bus. The grantee will have to deactivate its request signal at the end of the bus access period after which, the arbiter disables the corresponding grant signal.

Name______________________________ Student ID__________________________ 2. Design with FPGAs Consider an accumulator system that includes an adder and a register as shown in the figure to the right. The function of the accumulator is S <= S + A, where S and A are 2-bit vectors. Note that the carry-in of the adder is assumed to be zero and the carryout is ignored.

Page 2

Can the above circuit be implemented using one Xilinx 4000 logic cell (CLB). If yes, indicate the connections required on the CLB (shown below) and give the equations for F and G. If no, do the same for as many logic cell as needed. Label the cell inputs and draw heavy lines for all internal connections used.

Name______________________________ Student ID__________________________ 3. Resource-Latency Tradeoff

Page 3

The objective is to design a system for adding a list of 13 numbers using two-input adder modules. Assume that the numbers are already stored in 13 distinct registers, and the overhead of multiplexers and glue logic are negligible. a) What is the minimum number of adders to accomplish the task in at most 6 cycles? b) If you have only three adders available, what is the minimum number of cycles necessary to carry out the computation?