Chapter 7
Behavioral Modeling
VHDL
VHDL - Flaxer Eli Ch 7 - 1
Behavioral Modeling
Outline
z Process Statement
z Signal Assignment Statement
z Variable Assignment Statement
z Wait Statement
z If-Then-Else Statement
z Case Statement
z Null Statement
z Loop Statement
z Exit & Next Statement
z Assertion Statement
z Report Statement
VHDL - Flaxer Eli Ch 7 - 2
Behavioral Modeling
Behavioral Modeling
z In the behavioral modeling style, the behavior of the entity is expressed
using sequentially executed, procedural code, which is very similar in
syntax and semantics to that of a high-level programming language like
C or Pascal. A process statement is the primary mechanism used to
model the behavior of an entity. This chapter describes the process
statement and the various kinds of sequential statements that can be used
within a process statement to model such behavior.
z There is meaning to the order of the statements in the process.
VHDL - Flaxer Eli Ch 7 - 3
Behavioral Modeling
Process Statement
z The syntax of the process is:
[P-Label:] PROCESS [(sensitivity-list)][IS]
[process-item-declarations]
BEGIN
sequential-statement1;
sequential-statement2;
END PROCESS [P-Label];
z A set of signals to which the process is sensitive is defined by the
sensitivity list. In other words, each time an event occurs on any of the
signals in the sensitivity list, the sequential statements within the process
are executed in a sequential order, that is, in the order in which they
appear (similar to statements in a high-level programming language like
C or Pascal). The process then suspends after executing the last
sequential statement and waits for another event to occur.
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Behavioral Modeling
Sequential Signal Assignment
z The syntax is:
target-signal <= waveform;
– Examples:
MyTest: PROCESS (a, b)
BEGIN
z <= a;
Y <= a AFTER 10 ns;
X <= (a AND b) AFTER 20 ns;
W <= a AFTER 10 ns, ‘1’ AFTER 20 ns, ‘0’ AFTER 30 ns;
END PROCESS MyTest;
VHDL - Flaxer Eli Ch 7 - 5
Behavioral Modeling
Variable Assignment
z The syntax is:
target-variable := expression;
– Examples:
MyTest: PROCESS (a)
VARIABLE inx: integer := -1; -- only initialize
BEGIN
inx := inx + 1;
END PROCESS MyTest;
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Behavioral Modeling
IF-THEN-ELSE Statement
z Logically equivalent to concurrent conditional signal assignment
(WHEN-ELSE), but more versatile.
z Syntax:
label: -- optional
IF condition1 THEN
statements1;
ELSIF condition2 THEN -- optional section
statements2;
ELSE -- optional section
statements3;
END IF;
z Executes the first block of statements following a TRUE condition
z No other statement blocks are executed
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Behavioral Modeling
IF-THEN-ELSE (example)
z Series of conditions forms a priority encoder structure:
PROCESS (x,y,z,a,b,c,d)
BEGIN
IF x = ‘1’ THEN
foo <= a;
ELSIF y = ‘1’ THEN
foo <= b;
ELSIF z = ‘1’ THEN
foo <= c;
ELSE
foo <= d;
END IF;
END PROCESS;
z Result:
foo = x * a + /x * y * b + /x * /y * z * c + /x * /y * /z * d
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Behavioral Modeling
IF-THEN-ELSE Statement
z CAUTION - Implied memory (latch) will be created if a signal is not
always given a value each time the process runs
z Example:
PROCESS (xbus)
BEGIN
IF xbus = X”F” THEN
doitnow <= ‘1’; -- output of a set-only latch
END IF;
END PROCESS;
z If a latch is NOT desired
– include a default value assignment
– or be sure some branch of the IF statement always assigns a value
VHDL - Flaxer Eli Ch 7 - 9
Behavioral Modeling
IF-THEN-ELSE (latch)
ENTITY latch IS
PORT (a,b: IN std_logic; --inputs
sel: IN std_logic;
y,x: OUT std_logic); --output
END latch;
-----------------------------------------------------
ARCHITECTURE behavior OF latch IS
BEGIN
PROCESS (a,b,sel)
BEGIN
IF sel = '0' THEN
y <= a;
x <= a;
ELSE
y <= '-';
END IF;
END PROCESS;
END behavior;
x = sel * x.CMB + a * /sel
y= a
VHDL - Flaxer Eli Ch 7 - 10
Behavioral Modeling
CASE-WHEN Statement
z Logically equivalent to concurrent selected signal assignment (WITH-
SELECT-WHEN), but more versatile
z Syntax:
label: -- optional
CASE selector_expression IS
WHEN choice1 => statements1;
WHEN choice2 => statements2;
WHEN choice3 [| choice4] => statements3;
[WHEN OTHERS => statements4;] -- optional
END CASE;
z Executes the single block of statements following a valid choice, or
following OTHERS
z Choices must be mutually exclusive and all inclusive
z Forms a multiplexer-based logic structure
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Behavioral Modeling
CASE-WHEN (example)
z Example:
CASE State IS
WHEN “000” => x <= x + 1;
WHEN “001” => x <= x - 1;
WHEN “010” | “110” => y <= x;
WHEN “011” =>
IF (z = ‘1’) THEN
y <= “00”;
ELSE
y <= “11”;
END IF;
WHEN OTHERS => Temp <= (OTHERS => ‘0’);
END CASE;
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Behavioral Modeling
NULL Statement
z The NULL is a sequential statement that does not cause any action to
take place; execution continues with the next statement. One example of
this statement's use is in an if statement or in a case statement where, for
certain conditions, it may be useful or necessary to explicitly specify
that no action needs to be performed.
z For example:
CASE State IS
WHEN “00” => x <= x + 1;
WHEN “01” => x <= x - 1;
WHEN “10” => y <= x;
WHEN OTHERS => NULL;
END CASE;
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Behavioral Modeling
LOOP Statements
z Sequential statements for repetitive, iterative operations
z NOT executed iteratively in synthesized hardware!
z Simply a way of calculating new signal values in a process
z General syntax is:
[loop-label:] iteration-scheme LOOP
sequential-statement1;
sequential-statement2;
END LOOP [loop-label];
z FOR-LOOP executes specific number of iterations
z WHILE-LOOP executes as long as Boolean condition is TRUE
z LOOP executes as long as no EXIT appear.
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Behavioral Modeling
FOR LOOP
z For-Loop general format:
FOR index IN looprange LOOP
statements; -- generally using the index
END LOOP;
z Index variable automatically declared
z Index variable auto-increments or decrements at end of loop
z The loop index can not be assigned any value inside the loop
z The index name is local to the loop (if another variable with the same
name exist outside the loop)
z The range in for loop can also be a range of an enumeration type
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Behavioral Modeling
FOR LOOP (example)
z For-Loop example 1
FOR j IN 7 DOWNTO 0 LOOP
array(j) <= X”00”; -- clear a signal array
x(j) := y(j) + 5; -- integer array variable
END LOOP;
z For-Loop example 2
fact := 1;
FOR j IN 2 TO N LOOP
fact := fact * j;
END LOOP;
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Behavioral Modeling
FOR LOOP (synthesis example)
-- Example - 2 Level Full Adder
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
------------------------------------------------------
ENTITY adder4 IS
GENERIC (N: integer := 2);
PORT ( a: IN unsigned(N-1 DOWNTO 0); --inputs
cin: IN unsigned(N/2-1 DOWNTO 0); --carry in
co: OUT unsigned(N/2-1 DOWNTO 0); --carry out
y: OUT unsigned(0 DOWNTO 0)); --output
END adder4;
------------------------------------------------------
ARCHITECTURE behavior OF adder4 IS
BEGIN
PROCESS (a)
VARIABLE Temp: unsigned(N/2 DOWNTO 0);
BEGIN
Temp := '0' & cin;
FOR i IN 0 TO N-1 LOOP
Temp := Temp + (0=>a(i), OTHERS=>'0');
END LOOP;
y(0) <= Temp(0);
co <= Temp(N/2 DOWNTO 1);
END PROCESS;
END behavior;
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Behavioral Modeling
FOR LOOP (synthesis result)
co(0) =
a(1) * cin(0)
+ a(0) * cin(0)
+ a(0) * a(1)
y(0) =
a(0) * a(1) * cin(0)
+ /a(0) * /a(1) * cin(0)
+ /a(0) * a(1) * /cin(0)
+ a(0) * /a(1) * /cin(0)
VHDL - Flaxer Eli Ch 7 - 18
Behavioral Modeling
FOR LOOP (synthesis example)
-- Example - 4 Level Full Adder
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
------------------------------------------------------
ENTITY adder4 IS
GENERIC (N: integer := 4);
PORT ( a: IN unsigned(N-1 DOWNTO 0); --inputs
cin: IN unsigned(N/2-1 DOWNTO 0); --carry in
co: OUT unsigned(N/2-1 DOWNTO 0); --carry out
y: OUT unsigned(0 DOWNTO 0)); --output
END adder4;
------------------------------------------------------
ARCHITECTURE behavior OF adder4 IS
BEGIN
PROCESS (a)
VARIABLE Temp: unsigned(N/2 DOWNTO 0);
BEGIN
Temp := '0' & cin;
FOR i IN 0 TO N-1 LOOP
Temp := Temp + (0=>a(i), OTHERS=>'0');
END LOOP;
y(0) <= Temp(0);
co <= Temp(N/2 DOWNTO 1);
END PROCESS;
END behavior;
VHDL - Flaxer Eli Ch 7 - 19
Behavioral Modeling
FOR LOOP (synthesis result)
S_1 =
/a(0) * /a(1) * /a(3) * /cin(0) * cin(1)
+ /a(0) * a(1) * a(2) * /cin(0) * /cin(1)
+ a(0) * /a(1) * a(3) * /cin(0) * /cin(1)
+ a(1) * /a(2) * a(3) * /cin(0) * /cin(1)
S_2 =
a(1) * a(2) * a(3) * cin(0) * cin(1)
+ a(0) * a(2) * a(3) * cin(0) * cin(1)
+ a(0) * a(1) * a(3) * cin(0) * cin(1)
+ a(0) * a(1) * a(2) * cin(0) * cin(1)
+ a(0) * a(1) * a(2) * a(3) * cin(1)
+ /a(0) * /a(1) * /a(2) * /a(3) * cin(1)
+ /a(0) * /a(1) * /a(2) * /cin(0) * cin(1)
+ /a(0) * /a(2) * /a(3) * /cin(0) * cin(1)
+ /a(1) * /a(2) * /a(3) * /cin(0) * cin(1)
+ /a(0) * /a(1) * a(2) * a(3) * /cin(1)
+ /a(0) * a(1) * /a(2) * cin(0) * /cin(1)
+ /a(1) * /a(2) * a(3) * cin(0) * /cin(1)
+ /a(0) * a(2) * /a(3) * cin(0) * /cin(1)
+ a(0) * /a(1) * /a(3) * cin(0) * /cin(1)
+ a(0) * a(1) * /a(2) * /a(3) * /cin(1)
+ a(0) * a(2) * /a(3) * /cin(0) * /cin(1)
VHDL - Flaxer Eli Ch 7 - 20
Behavioral Modeling
FOR LOOP (synthesis result)
\MODULE_1:g1:a0:g0:u0:ga:g1:ua0\ =
a(0) * cin(0) * cin(1)
\MODULE_2:g1:a0:g0:u0:ga:g1:ua0\ =
/a(0) * a(1) * cin(0) * cin(1)
+ a(0) * a(1) * /cin(0) * cin(1)
\MODULE_3:g1:a0:g0:u0:ga:g1:ua0\ =
/a(0) * /a(1) * a(2) * cin(0) * cin(1)
+ /a(0) * a(1) * a(2) * /cin(0) * cin(1)
+ a(0) * /a(1) * a(2) * /cin(0) * cin(1)
+ a(0) * a(1) * a(2) * cin(0) * /cin(1)
\MODULE_4:g1:a0:g0:u0:ga:g1:ua0\ =
/a(0) * /a(1) * /a(2) * a(3) * cin(0) * cin(1)
+ /a(0) * /a(1) * a(2) * a(3) * /cin(0) * cin(1)
+ /a(0) * a(1) * /a(2) * a(3) * /cin(0) * cin(1)
+ a(0) * /a(1) * /a(2) * a(3) * /cin(0) * cin(1)
+ /a(0) * a(1) * a(2) * a(3) * cin(0) * /cin(1)
+ a(0) * /a(1) * a(2) * a(3) * cin(0) * /cin(1)
+ a(0) * a(1) * /a(2) * a(3) * cin(0) * /cin(1)
+ a(0) * a(1) * a(2) * a(3) * /cin(0) * /cin(1)
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Behavioral Modeling
FOR LOOP (synthesis result)
/co(0) =
/S_1.CMB * /S_2.CMB
co(1) =
/\MODULE_1:g1:a0:g0:u0:ga:g1:ua0\.CMB * \MODULE_2:g1:a0:g0:u0:ga:g1:ua0\.CMB *
\MODULE_3:g1:a0:g0:u0:ga:g1:ua0\.CMB * \MODULE_4:g1:a0:g0:u0:ga:g1:ua0\.CMB
+ \MODULE_1:g1:a0:g0:u0:ga:g1:ua0\.CMB * /\MODULE_2:g1:a0:g0:u0:ga:g1:ua0\.CMB *
\MODULE_3:g1:a0:g0:u0:ga:g1:ua0\.CMB * \MODULE_4:g1:a0:g0:u0:ga:g1:ua0\.CMB
+ \MODULE_1:g1:a0:g0:u0:ga:g1:ua0\.CMB * \MODULE_2:g1:a0:g0:u0:ga:g1:ua0\.CMB *
/\MODULE_3:g1:a0:g0:u0:ga:g1:ua0\.CMB * \MODULE_4:g1:a0:g0:u0:ga:g1:ua0\.CMB
+ /\MODULE_1:g1:a0:g0:u0:ga:g1:ua0\.CMB * /\MODULE_2:g1:a0:g0:u0:ga:g1:ua0\.CMB *
/\MODULE_3:g1:a0:g0:u0:ga:g1:ua0\.CMB * \MODULE_4:g1:a0:g0:u0:ga:g1:ua0\.CMB
+ \MODULE_1:g1:a0:g0:u0:ga:g1:ua0\.CMB * \MODULE_2:g1:a0:g0:u0:ga:g1:ua0\.CMB *
\MODULE_3:g1:a0:g0:u0:ga:g1:ua0\.CMB * /\MODULE_4:g1:a0:g0:u0:ga:g1:ua0\.CMB
+ /\MODULE_1:g1:a0:g0:u0:ga:g1:ua0\.CMB * /\MODULE_2:g1:a0:g0:u0:ga:g1:ua0\.CMB *
\MODULE_3:g1:a0:g0:u0:ga:g1:ua0\.CMB * /\MODULE_4:g1:a0:g0:u0:ga:g1:ua0\.CMB
+ /\MODULE_1:g1:a0:g0:u0:ga:g1:ua0\.CMB * \MODULE_2:g1:a0:g0:u0:ga:g1:ua0\.CMB *
/\MODULE_3:g1:a0:g0:u0:ga:g1:ua0\.CMB * /\MODULE_4:g1:a0:g0:u0:ga:g1:ua0\.CMB
+ \MODULE_1:g1:a0:g0:u0:ga:g1:ua0\.CMB * /\MODULE_2:g1:a0:g0:u0:ga:g1:ua0\.CMB *
/\MODULE_3:g1:a0:g0:u0:ga:g1:ua0\.CMB * /\MODULE_4:g1:a0:g0:u0:ga:g1:ua0\.CMB
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Behavioral Modeling
FOR LOOP (synthesis result)
y(0) =
a(0) * a(1) * a(2) * a(3) * cin(0)
+ /a(0) * /a(1) * a(2) * a(3) * cin(0)
+ /a(0) * a(1) * /a(2) * a(3) * cin(0)
+ a(0) * /a(1) * /a(2) * a(3) * cin(0)
+ /a(0) * a(1) * a(2) * /a(3) * cin(0)
+ a(0) * /a(1) * a(2) * /a(3) * cin(0)
+ a(0) * a(1) * /a(2) * /a(3) * cin(0)
+ /a(0) * /a(1) * /a(2) * /a(3) * cin(0)
+ /a(0) * a(1) * a(2) * a(3) * /cin(0)
+ a(0) * /a(1) * a(2) * a(3) * /cin(0)
+ a(0) * a(1) * /a(2) * a(3) * /cin(0)
+ /a(0) * /a(1) * /a(2) * a(3) * /cin(0)
+ a(0) * a(1) * a(2) * /a(3) * /cin(0)
+ /a(0) * /a(1) * a(2) * /a(3) * /cin(0)
+ /a(0) * a(1) * /a(2) * /a(3) * /cin(0)
+ a(0) * /a(1) * /a(2) * /a(3) * /cin(0)
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Behavioral Modeling
WHILE LOOP
z While-Loop general format:
WHILE boolean-expression LOOP
statements;
END LOOP;
z No automatic index declaration or modification
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Behavioral Modeling
WHILE LOOP (example)
z While-Loop example 1
j := 1; x:= 0;
WHILE j < 5 LOOP
x := x + array(j);
j := j + 1;
END LOOP;
z While-Loop example 2
j := 2; fact:= 1;
WHILE j <= N LOOP
fact := fact * j;
j := j + 1;
END LOOP;
VHDL - Flaxer Eli Ch 7 - 25
Behavioral Modeling
LOOP
z Loop general format:
LOOP
statements;
END LOOP;
z No automatic index declaration or modification
z The loop is infinite (if no exit, next or return)
z Actually it is equivalent to WHILE TRUE LOOP
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Behavioral Modeling
EXIT Statements
z The exit statement is a sequential statement that can be used only inside
a loop. It causes execution to jump out of the innermost loop or the loop
whose label is specified. The syntax for an exit statement is:
EXIT [loop-label] [WHEN condition];
z If no loop label is specified, the innermost loop is exited. If the when
clause ("when condition") is used, the specified loop is exited only if the
given condition is true; otherwise, execution continues with the next
statement.
VHDL - Flaxer Eli Ch 7 - 27
Behavioral Modeling
EXIT (example)
z Exit example 1
FOR j IN 1 TO 10 LOOP
array(j) <= X”00”;
IF j+i > 4 THEN
EXIT; -- stop loop if j+i > 4
END IF;
END LOOP;
z Exit example 2
Lp1: FOR j IN 1 TO 10 LOOP
array(j) <= X”00”;
EXIT Lp1 WHEN j+i > 4;
END LOOP Lp1;
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Behavioral Modeling
NEXT Statements
z The next statement is also a sequential statement that can be used only
inside a loop. The syntax is the same as that for the exit statement except
that the keyword next replaces the keyword exit. Its syntax is:
NEXT [loop-label] [WHEN condition];
z The next statement results in skipping the remaining statements in the
current iteration of the specified loop; execution resumes with the first
statement in the next iteration of this loop, if one exists. If no loop label
is specified, the innermost loop is assumed. In contrast to the exit
statement, which causes the loop to be terminated, the next statement
causes the current loop iteration of the specified loop to be prematurely
terminated; execution resumes with the next iteration.
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Behavioral Modeling
Next (example)
z Next example 1
FOR opcode IN nop TO jmp LOOP -- enumerated
Inx := Inx + 1;
IF opcode = jmp THEN
NEXT; -- skip next line if jump
ELSE
pc := pc + 1;
END IF;
END LOOP;
z Next example 2
Lp1: FOR i IN 1 TO 10 LOOP
Lp2: LOOP
NEXT Lp1 WHEN Done = ‘1’;
Jnx = Jnx + 1; -- This line is skip
END LOOP Lp2
Inx = Inx + 1; -- This line is skip
END LOOP Lp1;
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Behavioral Modeling
