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Department of Electronics and Communication Engineering: B E Degree Examination - Internal Assessment-II

This document contains questions related to advanced computer architecture for an internal assessment exam. It covers topics like instruction level parallelism, pipelining, dynamic scheduling, data level parallelism, vector processors, multiple issue processors, and control hazards. It contains 3 parts with a total of 16 questions assessing different cognitive levels ranging from remembering to applying and analyzing.

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38 views1 page

Department of Electronics and Communication Engineering: B E Degree Examination - Internal Assessment-II

This document contains questions related to advanced computer architecture for an internal assessment exam. It covers topics like instruction level parallelism, pipelining, dynamic scheduling, data level parallelism, vector processors, multiple issue processors, and control hazards. It contains 3 parts with a total of 16 questions assessing different cognitive levels ranging from remembering to applying and analyzing.

Uploaded by

vaniprabha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Reg No 13. 2 K3 a) Define Multithreading.

Explain how ILP is


achieved using Multithreading with an example.
Sri Shanmugha College of Engineering and Technology
(8) (N/D-’16)
Department of Electronics and Communication 3 K4 b) How do you determine the execution time of a
Engineering sequence of vector operations? Explain with
example.(5) (N/D’17)
B E Degree Examination – Internal Assessment- II 14. 3 K3 Discuss the salient features of vector
Year / Sem.: IV / VII Date &Time: 22.09.’19 & 9.50-12.50 processor(13) (N/D’17)
Subject code / Title:EC6009 / Advanced Computer Architecture Max.Marks:100 15. 3 K2 a) Write short notes on the different types of
Part – A 10 x 2 = 20 multiple issue processors(5) (N/D ’17)
K3 b) Discuss the various hardware techniques used
Q.No CO BT QUESTION for handling control hazards (8) (A/M-’17)
1. 2 K2 What is Instruction Level Parallelism? (N/D ‘11)
(M/J ‘12) Part – C 1x 15 =15
2. 2 K2 List the advantages of dynamic scheduling. (N/D Q.No CO BT QUESTION
‘12) (M/J ‘12) 16. 2 K4 Consider the following code:
3. 2 K2 What is recorder buffer? (N/D ‘17).
4. 2 K2 Define pipelining. (N/D ‘17) LOOP: L.D F2,0(R1)
5. 2 K3 Outline the limitations of Instruction Level MUL,D F4,F2,F0
Parallelism. (A/M-’18) L.D F6,0(R2)
6. 2 K3 Explain the idea behind dynamic scheduling. ADD.D F6,F4,F6
(N/D ‘16) S.D 0(R2).F6
7. 2 K2 Give an example for data dependence.(N/D ‘16). DADDIU R1,R1,#8
8. 3 K2 Define data level parallelism. (A/M ’18) DADDIU R2,R2,#8
9. 3 K3 How did single core architectures exploit data CMPI R3,R1,#800
level parallelism?(N/D’17) BEQZ R3,LOOP
10. 3 K3 Differentiate GPU and CPU. (N/D ’16) Assume that there are separate functional units
for effective address calculations, for ALU
Part – B 5x 13 =65 operations and for branch conditions evaluation.
Assume latencies for add and 5 for multiply,
Q.No CO BT QUESTION assume that loads and stores access memory one
11. 2 K2 a) Explain the types of dependencies in ILP clock cycle after the effective address
(6) (N/D ’16 ) calculations. Show the working of this code for
K2 b)Explain the compilation techniques that can be two iterations of the loop when executed on a
used to express instruction level parallelism (7) single issue Tomasulo processor that supports
(N/D ’16) speculation.(10) ({N/D-’17)
12. 2 K2 Explain the static and dynamic branch prediction
schemes in detail (13) (N/D’11,M/J ‘12, N/D
‘12,M/J ‘14)
Prepared by Verified by

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