POSSESION OF MOBILE IN EXAM IN UFM PRACTICE
Name…………………… Enrolment No……………………
Jaypee Institute of Information Technology, Noida
End Term Examination, ODD Sem-2021
B.Tech Semester-V
Course Name: Computer Organization and Architecture Max. Time: 1Hr
Course Code: 15B11CI313 Max. Marks: 100
1. [CO5, 2 Marks] Write assembly instructions in 8085 for the following C code conversion.
If(a<=b)C=0;
Else c=1;
MOV A, 05H
MOV B, 04H
CMP B 0.5 M
JNC AGTB 0.5 M
MOV C, 00H 0.5 M
JMP NEXT
AGTB: MOV C, 01H 0.5 M
NEXT: HLT
2. [CO2, 5 Marks] Write addressing mode of following instructions. Also calculate physical address
used by the instruction.CS=0700H, DS=0610H, ES=0510H, SS=0910H, IP=2000H, SI = 100H, BX=200H,
DI = 400H, SP= 300H, DX= 500H
a) MOV ES: [1234h], 5678h d) ADC CX, 1234H[SI][BX]
b) JMP [-4] e) PUSH DX
c) JMP[BX]
a) MOV ES: [1234h], 5678h
EA= ES (0)+1234H=05100+1234H=06334H 0.5 M
Direct Addressing mode 0.5 M
b) JMP [-4]
CS(0)+IP=07000+2000=09000H (Address of jump instruction)
Current IP=09001h
JMP[-4]= 08FFDH (JUMP address) 0.5 M
Relative Program Memory Addressing 0.5 M
c) JMP [BX]
IP =CS:[BX] = CS(0)+[0200]= 07000+Content of 0200 =EA memory location content
[0.5M]
Indirect Program Memory Address [0.5M]
d) ADC CX, 1234H[SI][BX]
EA=DS(0)+SI+BX+1234=07634h [0.5M]
Based - Indexed addressing Mode [0.5M]
e) PUSH DX
EA=SS(0)+SP=09100+0300=09400H [0.5M]
Stack Memory Addressing Modes [0.5M]
3. [CO6, 3+3+2 Marks]Assume that the code below is run on a machine with a 3 GHz clock that
requires the following number of cycles for each instruction: add, addi, slltake 4cc each, lwand
1
swtake 5cc, bne takes 3cc each. Assuming all registers except $6 is having zero value. The initial
value of registers $6 is 0x4.
a) How many seconds will it take to execute this code on non-pipeline based processor.
b) How many seconds it will take to execute it on single cycle pipeline based processor (having five
stages IF, ID, EX, MEM, WB) without data forwarding and instruction rearranging?
c) Also, calculate the speedup of pipeline to non-pipeline based processor.
[1]sll $6, $6, 1 [6]addi $8, $8, 4
[2]add $8, $0, $0 [7]sw $13, 0($13)
[3]Loop: add $14, $4, $9 [8]addi $9, $9, 4
[4]lw $11, 0($15) [9]bne $8, $6, Loop
[5]addi $12, $12, 20
Solution:
Initial value of $6= 0x4= 0000 0000 0000 0100
Value after sll $6, $6, 1= 0000 0000 0000 1000; 0x8
The loop will run 2 times
On Non pipelined based processor
sll $6, $6, 1 R TYPE 4CC
add $8, $0, $0 RTYPE 4CC
Loop: add $14, $4, $9 RTYPE 4CC
lw $11, 0($15) I TYPE 5CC
addi $12, $12, 20 I TYPE 4CC
addi $8, $8, 4 I TYPE 4CC
sw $13, 0($13) I TYPE 5CC
addi $9, $9, 4 I TYPE 4CC
bne $8, $6, Loop I TYPE 3CC
Number of CC before Loop = 4cc+4cc
Number of CC of Loop =(4cc+ 5cc+4cc+4cc+5cc+4cc+3cc)*2 Times
= 29cc*2
=58cc
Total Time on Non Pipeline based processor= 66cc/3*109= 22ns [3M]
On Pipeline based Processor
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
sll $6, $6, 1 IF ID EX M WB
add $8,$0, $0 IF ID EX M WB
L:add $14, $4, $9 IF ID EX M WB
lw $11, 0($15) IF ID EX M WB
addi $12,$12, 20 IF ID EX M WB
addi $8, $8, 4 IF ID EX M WB
sw $13, 0($13) IF ID EX M WB
addi $9, $9, 4 IF ID EX M WB
bne $8, $6, L IF ID EX M WB
2
L:add $14, $4, $9 IF ID EX M WB
lw $11, 0($15) IF ID EX M WB
addi $12,$12, 20 IF ID EX M WB
addi $8, $8, 4 IF ID EX M WB
sw $13, 0($13) IF ID EX M WB
addi $9, $9, 4 IF ID EX M WB
bne $8, $6, L IF ID EX M WB
Total cc on Pipeline based processor= 22cc [3M]
Total Time on Pipeline based processor= 22cc/3*109= 7.33ns
Speedup of pipeline to non-pipeline based processor= PerformancePipeline/ PerformanceNonpipeline
= TimeNonpipeline/ Timepipeline
= 22/7.33= 3 [2M]
4. [CO4, 5 Marks] Design memory interface of 256KB with 8086 processor using 3 to 8 line decoder.
For this design
a) what will be size of the individual memory chips that are connected to output of the decoder
and address line from the processor [2M]
b) What will be input address(A,B,C) line for low bank and high bank decoder [1.5M]
c) If the processor address ranges starts from 40000H, what will be input to the 3rd decoder?
[1.5M]
Solution:
2M
1.5M
1.5M
P.T.O
3
5. [CO6, 5 Marks] Consider a computer with the following characteristics: total of 1Mbyte of main
memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes.
a) Give any two main memory addresses with different tags that map to the last cache line for a
direct-mapped cache.[1.5M]
b) For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset
values for a fully-associative cache.[1.5M]
c) For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set,
and offset values for a two-way set-associative cache.[2M]
Solution:
a) We need to pick any address where the line is the same, but the tag (and optionally, the
word offset) is different.[1.5 M]
b) The word-offset must be 4 bits to address each individual word in the 16-word block. This
leaves 16 bits leftover for the tag. [1.5 M]
F0010: Word offset = 0h, Tag = F001h
CABBE: Word offset = Eh, Tag = CABBh
c) The 20-bit address is broken up as follows: Bits 0-3 indicate the word offset, Bits 4-14 indicate
the cache set.[2 M]
F0010 = 1111 0000 0000 0001 0000
4
Word offset = 0000 = 0
Cache Set = 000 0000 0001 = 001
Tag = 11110 = 1 1110 = 1E
CABBE = 1100 1010 1011 1011 1110
Word offset = 1110 = E
Cache Set = 010 1011 1011 = 2BB
Tag = 11001 = 1 1001 = 19
6. [CO2, 5 Marks] We have the following high-level code sequence:
C=A+B
D=C+A
a) Write the assembly code sequence for the above code sequence for the Accumulator, Stack,
and Load-store ISAs. The assembly code you write must use minimum instructions. [2.5M]
b) Assume that in memory reference instruction, every access to memory for data reads/writes
is 4 bytes. How many bytes of data are transferred between memory and processor for each
of the three ISAs in the code sequence (show the data bytes transferred for each instruction
in the code)? [2.5M]
Solution:
1.5 M
1.5 M
2M
7. [CO6, 5 Marks] The read access time of main memory in 90 nanoseconds. Assume that the caches
use the referred-word-first read policy and the write-back policy. Assume that all the caches are
direct mapped caches. Assume that the dirty bit is always 0 for all the blocks in the caches. In
5
execution of a program, 60% memory reads are for instruction fetch and 40% are for memory
operand fetch. What will be the average read access time in nanoseconds (up to 2 decimal places).
Solution: {Give full marks for correct formula)
Average Instruction fetch Time = L1 access time + L1 miss rate * L2 access
time + L1 miss rate * L2 miss rate * Memory access tim
time [2 marks
s]
Average Instruction fetch Time== 2 + 0.2 * 8 + 0.2 * 0.1 * 90= 5.4 ns
Average Data fetch Time = L1 access time + L1 miss rate * L2 access time +
L1 miss rate * L2 miss rate * Memory access tim
time [2 marks]
Average Data fetch Time =2 + 0.1 * 8 + 0.1 * 0.1 * 90= 3.7 ns
So, average read (access) time
= Fraction of Instruction Fetch * Average Instruction fetch time + Fraction of
Data Fetch * Average Data Fetch Time [1 marks]
So, average read (access) time== 0.6×5.4+0.4×3.7 = 4.72ns
*********************************Good Luck****************************************
