School of Computer Science and Engineering [SCOPE]
CAT – II (Open Book Exam) KEY
Semester: WIN2223 Course Name: Computer Organization and Architecture
Course Code: BCSE205L Slot: B1+TB1 Max.Marks: 50
Program: BCE,BKT,BCI,BDS ,BCT Time: 90 minutes
Answer ALL Questions (5* 10 = 50)
Q. Questions Max
No Marks
1 Scheme of Evaluation: 10
Sl.No. Item Marks
1 Instruction Cycle state diagram 4
2 Category based on operation type 3
3 Category Based on Addressing Mode 3
a)List various states and draw a state diagram for the process of an instruction
b)
Categories the following Simple RISC Computer instructions based on Operation, and
addressing modes involved. Use prescribed tabular format to specify opcode number
Category based on operation type Category Based on Addressing Mode
Instruction type Enter opcode numbers Addressing Mode Enter the opcode numbers
1.Data Movement 18,26,27,28,29 1.Implicit 30
2.Data Processing 19,20,22,23,24 2.Immediate 18,21.23
3.Control 30 3.Displacement 26,27,28,29
Simple RISC Computer instructions:
Opcode Instruction Operand references Description
16 svi ra rb Save II and IPC in ra and rb resly
17 ri ra rb Restore II and IPC from ra and rb respectively
Sets higher order 16 bits of ra with the least
18 sethi ra c2 significant 16 bits of the c2 field
19 xor ra rb rc R[ra]←R[rb] xor R[rc]
20 and ra rb rc R[ra]←R[rb] ^ R[rc]
21 andi ra rb c2 R[ra]←R[rb] ^ C2
22 or ra rb rc R[ra]←R[rb] ν R[rc]
23 not ra rc R[ra]← ¬ R[rc]
24 shr ra rb rc Shift rb right into ra by count in rc; c3 is 0
26 shr ra rb c3 Shift rb right into ra by constant count c3
shift rb right with sign-extend into ra by count
26 shra ra rb rc in rc
shift rb right with sign-extend into ra by
27 shra ra rb c3 constant c3
27 shl ra rb rc Shift rb left into ra by count in rc; c3 is 0
28 shl ra rb c3 Shift rb left into ra by constant count c3
Shift rb left circularly into ra by count in rc;
28 shc ra rb rc c3 is 0
Shift rb left circularly into ra by constant count
29 shc ra rb c3 c3
30 rfi Return from interrupt,PC←IPC
2 Scheme of Evaluation: 10
Sl.No. Item Marks
1 merits and de-merits 4
2 Address files size 3
Mode field size
Register field size
3 Opcode Field size 3
a)Discuss merits and de-merits of 1-Bus micro architecture against 2-Bus micro architecture
in data path implementation
Solution:
1. Reduction in the number of cycles for execution.
2. Increases the speed of execution or we can say faster execution.
b)
The memory unit of a computer has 4k words of 32 bit each. The computer has an
instruction format with four fields
• an operation code field
• A mode field to specify on of seven addressing opcode
• Register address field to specify one of 128 processor registers
• And a memory address.
Specify the instruction format and the number of bits in each field if the instruction is in one
memory word of size 32 bit.
Solution:
Number of words=4k=4 x 210=22x210=212
o Address files size (To address one of words)=12 bits
Number of address modes=7
o Mode field size( To address one of modes 7=23)=3 bits
Number of registers=128
o Register field size(To address one of registers 128=2 7)= 7 bits
Instruction Length
-----------------------------32bits-------------------------------
Opcode Mode Register Address Memory Address
? 3-Bits 7-bits 12-bits
Opcode field =
Instruction Length-
(Mode field + Register Address +Memory Address filed)
=32-(3+7+12)=32-22
Opcode field =10
3 Scheme of Evaluation: 10
Sl.No. Item Marks
1 List of characteristics 4
2 Formula 2
3 Calculations 4
a)List characteristics of memories
b) Assume that a benchmark has 100 instructions; 30% instructions are loads/stores (each
take 3 cycles), 40% instructions are adds (each takes 2 cycles), and 30% instructions are
square root (each takes 50 cycles), what is the CPI for this benchmark?
• The CPI is the average number of cycles per instruction.
If for each instruction type, we know its frequency and number of cycles need to
execute it, we can compute the overall CPI as follows:
Average CPI = Σ (CPI x F)
Op F CPI CPI x F
loads/stores 30%=0.3 3 .9
adds 40%=0.4 2 0.8
square root 30%=0.3 50 15
Total 100%=1 16.7
CPI=(0.3x3+0.4x2+0.3x50)=16.7
4 Scheme of Evaluation: 10
Sl.No. Item Marks
1 Brief Explanation on FIFO, LRU 4
2 Table of FIFO 2
3 Table of LRU 2
4 Comparison and Justification 2
In cache memory management policies, explain the process of the block replacement
algorithms FIFO and LRU, and interpret the following Main Memory block addresses to the
cache for FIFO and LRU. Consider the cache has four lines. Show each step in-detail for hit
and miss through 4-line cache.
7 0 1 2 0 1 0 2 2 3 2 0 3 3 5
Summarize details in the following prescribed format:
Algorithm FIFO LRU
No. of Misses 6 6
No. of Hits 9 9
Total no. of Reference 15 15
Miss Ratio 0.4 0.4
Hit Ratio 0.6 0.6
Compare the results and write your observations
5 Scheme of Evaluation: 10
Sl.No. Item Marks
1 Significance of memory interleaving 4
2 Table-1 2
3 Table -2 4
a)Discuss significance of memory interleaving
Solution:
Main memory is relatively slower than the cache. So to improve the access time of the main
memory, interleaving is used.
It allows simultaneous access to different modules of memory.
Interleave memory is useful in the system with pipelining and vector processing.
In an interleaved memory, consecutive memory addresses are spread across different
memory modules.
Reduce the memory access time by a factor close to the number of memory banks.
b) A computer employs RAM chips of 1024 x8 and ROM chips of 512 x 8. The computer
system needs 2k bytes of RAM, 1024 x 16 of ROM, and two interface units with 128 registers
each. A memory-mapped I/O configuration is used. The two higher -order bits of the address
bus are assigned 00 for RAM, 01 for ROM, and 10 for interface registers.
a. Compute total number of decoders are needed for the above system? (2Marks)
b. Design a memory-address map for the above system (4Marks)
Solution:
S. No. No. of Memory NxW N1 x W1 p q p*q x y z Total
Memory Title NI WI N=2x p=2y T=2z =
Types N W x+y+z
(T)
3 2048 8 2x1 (1024=210) (2=21) (3=22)
1 RAM 1024 x8 2Kx8 1024 2 8
1
=2 =10 =1 =2
13
3 16 2 x2
1024 8 2 (512=29) (2=21) (3=22)
2 ROM 512x8 1024x16 512 2 =4 12
=9 =1 =2
3 -2 x 1 (128=27) (2=21) (3=22)
3 Interface 128x 2 - 10
=2 =7 =1 =2
Component Hexadecimal address Address bus (13 bits: 0-12)
Organization
[p-rows x q-columns] From To 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
RAM[1,1] 0000 03FF 0 0 0 x x x x x x x x x x
RAM[2,1] 0400 07FF 0 0 1 x x x x x x x x x x
ROM[1,1][1,2] 0800 0BFF 0 1 0 x x x x x x x x x
ROM[2,1][2,2] 0C00 0FFF 0 1 1 x x x x x x x x x
Interface1 1000 1FFF 1 0 0 x x x x x x x x
Interface2 1400 17FF 1 0 1 x x x x x x x x
