…4th… Sem (Regular & Back)

COA & CS2006

(CS,ITCS&SE,CS&CE,,ECS)

SPRING END SEMESTER EXAMINATION-2018

4thSemester B.Tech & B.Tech Dual Degree
EVALUATION SCHEME
COMPUTER ORGANIZATION & ARCHITECTURE
CS 2006
1.[AKS]
a) Execute the following instruction where R0 is of 8 bit data and its content is 11111001.
a) Rshift L #2, R0 [1 mark]
b) Ashift R #1, R0 [1 mark]
Ans:
a) Assume RshiftL means logical shift right. After execution, content of R0 is 00111110.
b) AshiftR means arithmetic shift right. After execution, content of R0 is 11111100.

b) Differentiate between horizontal [1 mark]and vertical organization. [1 mark]

Ans: Vertical Organization: Highly encoded schemes that use compact codes to specify only a small
number of control functions in each microinstruction are referred to as vertical organization. This
vertical approach results in considerably slower operating speeds because more microinstructions are
needed to perform the desired control functions.
Horizontal organization: The minimally encoded scheme, in which many resources can be controlled
with a single microinstruction, is called as horizontal organization. This approach is useful when a
higher operating speed is desired and when the machine structure allows parallel use of resources.

c) In IA-32, which registers are used to fetch the instruction from memory as the PC does in other
processor? Explain. [2 mark]

Ans: In IA-32, instruction pointer register, eight general-purpose registers, the six segment registers
and FLAGS register are used to fetch the instruction from memory as the PC does in other processor.
These registers comprise a basic execution environment in which to execute a set of general-purpose
instructions. These instructions perform basic integer arithmetic on byte, word, and double word
integers, handle program flow control, operate on bit and byte strings, and address memory.

d) What is the hit ratio of the cache memory if cache memory access time is 5ns and main memory
access time is 25ns and average access time is 140ns? [2 mark]
Ans:// If student writes the formula with respective values, full mark will be awarded.
AMAT=hc + (1-h) M
140=5h + (1-h) 25
140=5h+25-25h
140=25-20h h= -5.75
e) A processor is connected to a 2GB × 32 bit memory module . A program is kept in 256th address of the
memory and the maximum length of each instruction of the program is of 32 bits. Then find out size of
MAR, MDR, IR and also the content of PC? [2 mark]
Ans: MAR=31 bits
MDR= 32 bits
IR= 32 bits
PC=31 bits
f) .[SD]Write “ENGINEER” using Big Endean and Little Endean format considering word length as 32
bits.
ANS. Big Endian[1 mark]
0 1 2 3

E N G I
N E E R
4 5 6 7

Little Endian[1 mark]

0 1 2 3

I G N E
R E E N
4 5 6 7

g. Specify the size of instruction decoder and step decoder size if the system supports 36
different instructions and each instruction requires maximum up to 7 steps to complete the
execution. [2mark]
ANS. instruction decoder size :- 6 : 64
step decoder size :- 3 : 8

h. Design the 2MB × 32 memory using 1024K × 8 RAM chip. [2 mark]

ANS:- ( 2 X 220 X 32 ) / ( 210 X 210 X 8 ) = 8 chips
2 ROW and 4 column array
1 bit row decoder
20 bit internal chip address

i. “Block replacement is not possible in Direct mapped cache”-Justify the statement. [2 mark]
ANS:- Each memory block has only one place to load in Cache memory.
Block j of the main memory maps to j modulo of the cache.
Hence replacement is not possible.

j. Given the following program fragment[2 mark]

Main Program First Subroutine Second Subroutine
1004 SUB R1, R2 6000 SUB1 ADD R1,R2 8012 SUB2 SUB R6, R1
1008 ADD R3, R4 6004 DIV R5, R1 8016 MUL R1, R5
1012 CALL SUB1 6008 CALL SUB2 8020 RETURN
1016 MUL R4, R5 6012 RETURN
Initially the stack pointer SP contains 4000.
What are the content of PC, SP, and the top of the stack?
i) After the subroutine call instruction is executed in the main program?

ANS:- PC=6000, SP=3996, ST ( top) = 1016

ii) After the subroutine call instruction is executed in the subroutine SUB1?
 ANS:- PC=8012, SP=3992, ST ( top) = 6012

iii) After the return from SUB2 subroutine?

ANS:- PC=6012, SP=3996, ST ( top) = 1016

2.a)[DH] An instruction is stored at location 202 with its address field at location 203. The address field
has the value 55. A processor register R55 contains the value 350. Evaluate the effective address if the
addressing mode of the instruction is :-
i. Direct addressing mode [1 mark]
ii. Immediate addressing mode[1 mark]
iii. Relative addressing mode[1 mark]
iv. Register indirect addressing mode[1 mark]

Ans:
i. Direct addressing mode , EA=55
v. Immediate addressing mode , EA= Not required
vi. Relative addressing mode, EA= 204+55=259
vii. Register indirect addressing mode EA= (R55)=350
b) Represent the decimal number -101.425 using IEEE 754 single precision floating point format.
Ans: [4 mark]
represent -101.425 in IEEE Standard format.
(1) Determine sign bit. S=1.
(2) Convert the number into fixed point binary without using sign.
101=1100101
.625=011011010010110………..(RECURRING, 0110 is repeated)
So 101.425= 1100101 . 011011010010110………..

(3) The mantissa must be normalized, that means the decimal point is placed to the right of the first non
zero significant bit.

101.425=1100101 . 011011010010110………..=1.100101011011010010110………..× 2 6
Mantissa is=100101011011010010110………..
Exponent is =6, it will be represented in Excess-127 i.e, 6+127=133 = 10000101
(4) mantissa has to represented in 23 bits, that means it is represented as
1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1.
(5) So the format is as follows

1 10000101 10010101101100110011001

3.a) .[BI] Consider the following program below where A,B,C,D and X are memory locations.
ADD A,B,R1;
DIV C,D,R2;
MUL R1,R2,X
Write down the equivalent code for following computers
(i) Stack Based computer[2 mark]
ii) Accumulator Based Computer [2 mark]
EVALUATION SCHEME:
Correct code for Stack Based computer: 2 marks, Correct code for Accumulator Based Computer: 2
marks, Step marking may be awarded by looking at the partial correctness of the logic used.
Ans: The program can be written in the form of following expression: X = (A+B) * (C/D)
i) Following is the equivalent code for Stack Based Computer:
PUSH A
PUSH B
ADD
PUSH C
PUSH D
DIV
MUL
POP X
ii) Following is the equivalent code for Accumulator Based Computer:
LOAD A
ADD B
STORE S
LOAD C
DIV D
MUL S
STORE X
b) Multiply (-15 × -8) using Booth’s multiplication algorithm. [4 mark]
EVALUATION SCHEME: Correct representation of Multiplicand and Multiplier = 1 mark,
Correct application of Booth’s Algorithm, e.g. Qi Qi-1 rule : 1 mark
Results obtained using Booth’s algorithm: 2 marks, Step marking could be awarded by looking at the
partial correctness of the logic.
Ans:
Multiplicand = M = -15, Multiplier = Q = -8
15 = 01111, -15 = 2’s complement of 15 = 10001, 8 = 01000, -8 = 10111 + 1 = 11000
So, M = 10001, Q = 11000, M’s 2’s complement = 01110 + 1 = 01111
1st way:
10001
11000
0-1000
00000
00000
00000
01111
00000
01111000 = 120
2nd way:

A Q Q(-1) N Operation
00000 11000 0 5 Right Shift
00000 01100 0 4 Right Shift
00000 00110 0 3 Right Shift
00000 00011 0 2 Right Shift
00000 00001 1 1 A=A–M
00000
01111
01111 00001 1 1 Right Shift
00111 10000 1 0 Right Shift
00011 11000 0 0
The product is A Q = 00011 11000 = 120

Q4. .[DS]
(a) A cache consists of a total of 512 blocks. The main memory contains 16K blocks, each consisting of 32
words.
i. What is the size of the main memory and cache memory? [1 mark]
ii. How many bits are there in each of the TAG, INDEX, and BLOCK OFFSET field in case of direct
mapping? [1 mark]
iii. How many bits are there in each of the TAG, and BLOCK OFFSET field in case of associative
mapping? [1 mark]
iv. How many bits are there in each of the TAG, SET, and BLOCK OFFSET field in case of 4-
way set-associative mapping? [1 mark]

(b) Perform division using restoring technique. [4 mark]

13 ÷ 4 =?

(ANSWER)
(a)
Total cache blocks = 512
Total words in cache =512 X 32 =16K.

Total main memory blocks = 16K Total words= 512K

Address bus size= 19 bits.

(i) Size of main memory=512 KB

Size of cache memory=16KB
(ii) TAG= 5 bits, Index/ BLOCK=9 bits, WORD=5 bits
(iii) TAG=14, WORD=5
(iv) TAG=7 bits, SET=7 bits, WORD=5 bits.
4 blocks= 1 set
512 blocks=128 set
So bits in set block = log2128 = 7 bits
5.a. [SB]ADD R1,R2,#5[4 mark]
Control sequence:
1.PCOUT, R=B, MARIN,Read,IncPC
2.WMFC
3.MDROUTB, R=B, IRIN
4.offset_field_of_IROUTA,R2OUTB, Select A,Add,R1IN,End
b) In SRAM, the state 0 or 1 is stored due to the conduction of transistors. [4mark]

Figure 5.4 of page 298

Internal Organization

(1)Two invertors are cross connected to form a latch.

(2)The latch is connected to two bit lines b0 and b0 ‘ through the transistor T1 and T2.
(3) The transistors are used as switches which are opened or closed under the control of word line.
(4)When wordline= 1(activated), the transistors are on, the cells are read or written into.
(5)When wordline= 0(not activated), the transistors are off, the cells or latch retains it’s state.

Read operation
Let the cell is in 1 state(set), so X=1 and Y=0.
(1)Address is placed by the processor and word line is selected.
(2)The transistor T1 and T2 starts conducting.
(3) Though X=1 and Y=0, high voltage is available in b0 and low voltage is available in b0 ‘.
(4)The sense / write circuit monitors the bit lines and transfers the state 1 to the output line.
Write operation
Let the state 0 is written into the cell.
(1)Address is placed by the processor and word line is selected. The data(start 0) is put into the lines
which is connected to sense / write circuit.
(2)The transistor T1 and T2 starts conducting.
(3) The sense / write circuit places a low voltage(0) in b0 and high voltage(1) in b0 ‘that makes the latch
reset. So state 0 is written into the cell.
Q6.(a)[NP]Daisy chain Approch for handling simultanus interrupt request[1 mark]
Explanation. [2 mark]
Digram [1 mark]

[1
(b)Virtual memory defination . [1 mark]
Address translation using TLB. [2 mark]
Diagram [1 mark]

Q.7. a[SP]. What are the different data transfer techniques present? Briefly explain DMA technique.
[4mark]

Three techniques are possible for IO data transfer: programmed IO, interrupt driven IO and direct
memory access.
Programmed IO-Data are transfer between processor and IO module by executing a program by the
processor.When the processor issues a command to the IO module, the processor wait until the IO
operation is completed.
Interrupt driven IO-The processor issues an IO command and continues to execute other
instructions.When the IO module complete the transfer it send an interrupt to the processor.
Direct Memory Access-
DMA involves an additional module on the system bus.
When the processor wishes to read or write a block of data, it issues a command to the DMA module.
The processor sends the read or write request, address of the IO device, the starting memory location
and number of words to be read or write. The processor then continue with other work. The MDA
module transfers the entire block of data with out going through the processor. When the transfer is
complete, the DMA module sends an interrupt signal to the processor.
b. Give two examples from each of the following categories of instruction explaining their functions.
I. Data Transfer operation[1 mark]
II. Arithmetic operation[1 mark]
III. Shift operation[1 mark]
IV. IV.Program Control operation[1 mark]

I.Data transfer operation:

MOVE: transfer a word or block from source to destination , e.g. MOVE R1,R2
LOAD: transfer a word from memory to processor , e.g. LOAD A
Ii.Arithmetic operation
ADD: e.g. ADD A,B add the content of A with content of B and store in B
INC R1 increment the value of R1 and store in R1
Iii.Shift operation
LShiftL #2,R Shift the bits of R towards left by two position and fill the vacant position by 0s.
LShiftR #2,R Shift the bits of R towards right by two position and fill the vacant position by 0s.
Iv.program control operation
BRE R1,R2,X branch to memory location X if contents of R1= contents of R2
BR Y branch to memory location Y
8.[DH]
a) Memory Interleaving : The distribution of memory addressees among all memory modules are carried
out in such way that all modules are busy to access a block of words .
Explanation – [3 mark]Diagram – [1 mark]
b) IA-32 Addressing modes[4 mark]
1. Immediate addressing mode Data is a part of instruction.
MOV AX,32; 32[AX]
E.A.= Value in the instruction
2. Direct Addressing Mode Address is a part of instruction. [ ] is used to indicate the direct addressing
mode.
MOV AX, [32]
E.A= Address / location
3.Register Direct Addressing mode Register is specified in the instruction.
MOV AX,BX;
E.A= Register
4.Register Indirect Addressing Mode Register is specified in the instruction and that register holds the
address of operand
MOV AX,[BX];
E.A= [Register]
For other addressing modes, the E.A. is calculated as follows
E.A= Base Reg +Index Reg + Displacement
5. Base with displacement
MOV AX, [EBP+60]
E.A= [Reg]+ displacement
6.Index with displacement
MOV AX, [SI*4+10]
E.A= [Reg* S]+ displacement
S= Scale factor=1/2/4/8
Base with index 
MOV AX, [BP+SI*4];
E.A= [Reg1]+ [Reg2]*S
8.Base with Index with displacement
MOV AX, [BP+SI*4 +10];
E.A= [Reg1]+ [Reg2]*S +Displacement
9. Implied Addressing mode
The address of operand is not specified in the instruction.
c) Memory Mapped I/O Vs I/O mapped I/O[4 mark]
Address space partitioning (How address is assigned to I/O device?)
The distribution of addresses among I/O devices is called address space partitioning which is dependent
upon the architecture of the processor. Two types of schemes are used and they are
(i)Memory mapped I/O  Some memory addresses are to access the I/O devices. So any machine
instruction that accesses the memory, can be used to access I/O device.
Example: Move R1, 1000// 1000 is an address of i/o device
Advantage: No extra instruction is used to access the I/O device.
Disadvantage : It reduces the address space.
(ii)I/O mapped I/O(Isolated I/O)Distinct addresses are used to access the I/O devices. Separate
instruction are used to transfer data between the I/O device and processor.
Example: OUT 10; //the content of accumulator is moved to 10( 10 is an address of i/o device)
Advantage: Address space is fully utilize for memory reference.
Disadvantage : Extra instruction is used for I/O data transfer.