Question bank by professor Tanya Shrivastava
Question Bank
Unit – 1
1. An instruction is stored at location 300 with its address field at location 301. The address field has the value
400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing
mode of the instruction is (a) direct; (b) immediate; (c) relative; (d) register indirect; (e) index with R1 as
the index register.
2. An instruction is stored at location 400 with its address field at location 401.The address field has the value
500.A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode
of the instruction is (i) direct (ii) immediate (iii) relative (iv) register indirect (v) index with R1 as index
register.
3. What are the different types of buses used in computer architecture?
4. Name different types of multipliers.
5. Name different types of registers.
6. What is meant by the term bus arbitration? Why it is needed? How can bus arbitration be implemented in
Daisy Chain mechanism?
7. What do you mean by processor organization? Explain various types of processor organization with
suitable example?
8. Explain general register organization and stack organization.
9. Differentiate between Register Stack and Memory Stack.
10. Differentiate between Computer architecture and Computer organization.
11. Register a holds the binary values 11101011.What is the register value after arithmetic shift right? Starting
from the initial number 11101011, determine the register value after arithmetic shift left, and state whether
there is an overflow.
12. What is mean by bus arbitration? List different types of bus arbitration.
13. Represent the following conditional control statements by two register transfer statements with control
functions. If(P=1) then (R1R2) else if (Q=1) then (R1R3)
14. A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with
multiplexers.
a. How many selection inputs are there in each multiplexer?
b. What size of multiplexers is needed?
c. How many multiplexers are there in the bus?
15. What is the role of multiplexer and decoder?
16. Explain functional units of computer system in detail.
Question bank by professor Tanya Shrivastava
Question bank by professor Tanya Shrivastava
17. What is an effective address? How it is calculated in different types of addressing modes? Explain.
18. Discuss the design of a typical input or output interface.
19. A digital computer has a common bus system for 8 registers of 16 bit each. The bus is constructed using
multiplexers.
How many select input are there in each multiplexer?
What is the size of multiplexers needed?
How many multiplexers are there in the bus?
Unit – 2
20. Discuss biasing with reference to floating point representation.
21. Explain IEEE-754 standard for floating point representation. Express (314.175)10 in all the IEEE-754
models.
22. Show the systematic multiplication process of (-12) × (-18) using Booth’s Algorithm.
23. Show the systematic multiplication process of (-15) × (17) using Booth’s Algorithm.
24. Explain in detail the principle of carry look ahead adder and design 4-bit CLA adder.
25. Show the systemic multiplication process of (20) X (-19) using Booth’s algorithm.
26. Explain IEEE standard for floating point representation. Represent the number (-1460.125)10 in single
precision and double precision format.
27. Explain IEEE standard for floating point representation. Represent the number (-215.18)10 in single
precision and double precision format.
28. Explain 2-bit by 2-bit Array multiplier.
29. Perform division operation process between (+9) ÷ (+3). Use the tabular approach for each step.
30. Illustrate the step by step division operation process between (+15) ÷ (3). Use the restoring division
algorithm and tabular approach for each step.
31. Illustrate the step by step division operation process between (-18) ÷ (-5). Use the non-restoring division
algorithm and tabular approach for each step.
32. Perform the division process of 00001111 by 0011(use a dividend of 8 bits) by Non-restoring Division
Method.
33. Represent (1259.125)10 in single and double precision format.
34. Represent the following decimal number in IEEE Standard floating point format in a single precision and
double precision representation method.
(85.125) 10
(-307.1875) 10
35. Represent the following decimal number in IEEE Standard floating point format in a single precision
method (32 bit) representation method.
(32.75) 10
Question bank by professor Tanya Shrivastava
Question bank by professor Tanya Shrivastava
(-506.257) 10
36. Design of an 8-bit ARITHMETIC LOGIC UNIT.
Unit – 3
37. Differentiate RISC and CISC.
38. List different types of control signals.
39. Explain the different cycles of an instruction execution.
40. What are different types of instruction format?
41. What are the different phases of an instruction cycle?
42. List the steps involved in an instruction cycle.
43. How does control unit of a computer works?
44. Define different types of microinstructions available.
45. Explain the concept of pipelining and also explain types of pipelining.
46. Illustrate the significance of pipelining. How pipelining is used to achieve parallel processing? Explain
space time diagram for 5 stages and 8 number of tasks.
47. Write a program to evaluate the arithmetic statement. P = ((X − 𝑌 + 𝑍) ∗ (A ^ B))/( C ^ D ∗ E) By using (i)
Two address instructions (ii) One address instructions (iii) Zero address instructions.
48. Evaluate the arithmetic statement. X = A + B * (((C - D * E) / F) / G) using a stack organized computer
with zero address and one address instructions.
49. Draw the flowchart for instruction cycle with neat diagram and explain.
50. What is a micro program sequencer? With block diagram, explain the working of micro program
sequencer.
51. Draw space time diagram for 4 segments pipeline with 8 tasks.
52. Discuss Instruction format and classify according to the basic computer systems. The Instruction format
has 16 bits, 12 bits are used to represent address part and one bit for mode part then Calculate how many
bits are required for opcode?
53. Convert the following arithmetic expressions from Infix to Reverse Polish Notation-
a. A*B+C*D-E*F
b. A*[B+C*D+E]/F*(G+H)
Unit – 4
54. Define the concept of locality of reference.
55. Define virtual memory.
56. Differentiate between Static RAM and Dynamic RAM
57. What is an associative memory? What are its advantages and disadvantages?
58. Explain 2D and 2.5D memory organization with diagram.
Question bank by professor Tanya Shrivastava
Question bank by professor Tanya Shrivastava
59. Differentiate between horizontal and vertical microprogramming.
60. A two way set associative cache memory uses blocks of four words. The cache can accommodate a total of
2048 words from main memory. The main memory size is 128K × 32
Formulate all pertinent information required to construct the cache memory. (Tag, index, data,
blocks, words)
What is the size of cache memory.
61. Discuss the Memory Hierarchy in computer system with regard to Speed, Size and Cost.
62. Write short notes on magnetic disk, magnetic tape and optical disk.
63. Consider a cache (M1) and memory (M2) hierarchy with following characteristics:
M1 : 16K word, 15 ns Access time
M2 : 1M word, 400 ns Access time
Assume 8-word cache blocks and set size 256 words with set associative mapping.
(i) Show and explain the mapping between M2 and M1.
(ii) Calculate the effective memory access time with cache hit ratio = 0.95.
64. Explain basic concept of memory hierarchy.
65. Differentiate between hardwired and micro programmed control unit. Explain each component of
hardwired control unit organization.
66. A computer uses RAM chips of 1024*1 capacity.
o How many chips are needed & how should their address lines be connected to provide a memory
capacity of 1024*8?
o How many chips are needed to provide a memory capacity of 16 KB?
67. Explain the direct mapping technique? Consider a digital computer has a memory unit of 64K X 16 and a
cache memory of 1K words. The cache uses direct mapping with a block size of four words.
o How many bits are there in the tag, index, block, and word fields of the address format?
o How many bits are there in each word of cache, and how they are divided into functions? Include a
valid bit.
o How many blocks can the cache accommodate?
68. The logical address space in a computer system consists of 128 segments. Each segment can have up to 32
pages of 4K words each. Physical memory consists of 4K blocks of 4K words each. Formulate the logical
and physical address formats.
69. Explain Address mapping and its types? Also explain replacement algorithm.
70. A block-set associative cache consists of a total of 64 blocks divided into 4 blocks sets. The main memory
contains 4096 blocks each consisting of 128 words.
How many bits are there in main memory address?
How many bits are therein each of the TAG, SET and WORD fields?
71. A certain magnetic disk has the following specifications-
a. (i)No. of recording=10 (ii)No of tracks/surface=256 (iii)No of sectors/track=32 (iv) No of
bytes/sector=128 (v)Disk rotation speed=2400 rpm
b. Calculate the following: (i)Disk Capacity (ii)Transfer rate (iii)Latency Time
Question bank by professor Tanya Shrivastava
Question bank by professor Tanya Shrivastava
72. Give classification of memory based on the method of access. Also discuss construction and working of
magnetic disk and various components of disk access time.
Unit – 5
73. In what way synchronous and asynchronous serial modes of data transfer differ?
74. What do you mean by asynchronous data transfer? Explain strobe control and handshaking mechanism.
75. Explain destination-initiated transfer using handshaking method.
76. Differentiate between synchronous and asynchronous data transfer? Explain Simplex, Half Duplex and
Full Duplex with Suitable Example.
77. What are the basic differences between interrupt initiated I/O and programmed I/O? Explain in detail.
78. Define interrupt. Also discuss different types of interrupt.
79. With a neat schematic diagram, explain about DMA controller and its mode of data transfer.
80. Why does the DMA get priority over CPU when both request memory transfer?
Question bank by professor Tanya Shrivastava
