GSFC University, Vadodara

Department of Computer Science and Engineering

Computer Organization
Question Bank
Semester - III (2024 - 25)

Unit I and II
1. Differentiate between Computer organization and Computer architecture

2. Give example of external and internal interrupt

3. Write and explain different Addressing modes
4. Write and explain different instruction formats with examples of each

5. What do you mean by interrupt, explain in details

6. What is the sequence of steps in instruction cycle and explain the register transfer for fetch phase
with necessary equation and diagram.
7. Explain the working of instruction register and instruction decoder

8. Explain in details the working of timing and control unit of the microprocessor
9. Explain program counter and stack pointer register
10. Draw and explain the general block diagram of microprocessor based system
11. A computer uses a memory unit with 128K words of 32 bits each, A binary instruction code
is stored in one word of memory. The instruction has four parts: an addressing mode specify
4 addressing modes. An operation code, a register code part to specify one o registers, and an
address part. a) How many bits are there in the operation code, the register code part, the
addressing to 16 mode part and the address part? raw the instruction word format and indicate
the number of bits in each part. How many bits are there in the data and address inputs oi the
memory?

12. A computer uses a memory unit with 512K words of 32 bits each. A binary instruction code
is stored in one word of memory. The instruction has four parts: an indirect bit, an operation
code, a register code part to specify one of 256 registers, and an address part. How many bits
are there in the addressing mode, operation code, the register code part and the address part?

13. What do you mean by registers, explain the registers and their use in microprocessor/computer
system

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14. A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code
is stored in one word of memory. The instruction has four parts: an indirect bit, an operation
code, a register code part to specify one of 64 registers, and an address part.

(a) How many bits are there in the operation code, the register code part and the address part?
(b) Draw the instruction word format and indicate the number of bits in each part.
(c) How many bits are there in the data and address inputs of the memory?
15. What is the difference between a direct and an indirect address instruction?

16. How many references to memory are needed for each type of instruction to bring an operand into
a processor register?
17. Draw a timing diagram, sequence counter (SC) is is cleared to 0 at time T3 if control signal C7
is active.
C7T 3 : SC ← 0

C7 is activated with the positive clock transition associated with T1.

18. What is the sequence of steps in instruction cycle and explain the register transfer for fetch phase
with necessary equation and diagram.
19. A bus organized CPU has 16 registers with 32 bits in each , an ALU , and a destination decoder.
(a) How many multiplexers are there in the A bus , and what is the size of each multiplexer?
(b) How many selection inputs are needed for mux A and mux B?
(c) How many inputs and outputs are there in the decoder?
(d) How many inputs and outputs are there in the ALU for data, including input and output
carries?
(e) Formulate a control word for the system assuming that the ALU has 35 operations.

20. A two-word instruction is stored in memory at an address designated by the symbol W. The
address field of the instruction (stored at W+1) is designated by the symbol Y. The operand
used during the execution of the instruction is stored at an address symbolized by Z. An index
register contains the value X. State how Z is calculated from the other addresses if the addressing
mode of the instruction is

(a) Direct
(b) Indirect
(c) Relative
(d) Indexed

21. A computer has 32-bit instructions and 12-bit addresses.If there are 250 two address instructions,
how many one - address instruction can be formulated?
22. Specify the control word that must be applied to the processor to implement the following
microoperations
(a)
R1 ← R2 + R3
(b)
R4 ← R4

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 (c)
R5 ← R5 − 1
(d)
R6 ← SHL R1
(e)
R7 ← IN P U T
23. A relative mode branch type of instruction is stored in memory at an address equivalent to
decimal 750 . the branch is made to an address equivalent to decimal 500.
(a) What should be the value of the relative address field of the instruction (in decimal)?
(b) Determine the relative address value in binary using 12 bits .(why must the number be in
2’s complement?)
(c) Determine the binary value in PC after the fetch phase and calculate the binary value of
500. Then show that the binary in PC plus the relative address calculated in part b is equal
to the binary value of 500.
24. An instruction is stored at location 300 with its address field at location 301. The address field
has the value 400 . A processor register R1 contains the number 200. Evaluate the effective
address if the addressing mode of the instruction is

(a) direct
(b) immediate
(c) relative
(d) register indirect
(e) index
with R1 as the index register.
25. Given the 16-bit value 1001101011001101. What operation must be performed in order to:
(a) Clear to 0 the first eight bits.
(b) Set to 1 the last eight bits.
(c) Complement the middle eight bits.
26. Given the 16-bit value 1010 0101 1001 1000, what operation must be performed, and what
operand is needed, in order to

(a) the most significant 8 bits to 1s?

(b) the bits in even positions (the leftmost bit is 15 and the rightmost bit is 0) to 0?
27. Given the 16 bit value 1001101011001001. What operations must be performed in order to :
clear to 0 the first eight bits and complement the middle eight bits?

28. A digital computer has a common bus system for 16 registers of 32 bit each. The bus is con-
structed with multiplexers.
(a) How many selection inputs are there in each multiplexer?
(b) What sizes of multiplexers are needed?
(c) How many multiplexers are there in a bus?

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29. The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction
format with four fields : an operation code field, a mode field to specify one of seven addressing
modes, a register address field to specify one of 60 processor registers and a memory address.
Specify the instruction format and the number of bits in each field if the instruction is in one
memory word.

30. Differentiate between RISC and CISC

31. Convert the following arithmetic expressions from infix to reverse polish notation.

(a)
A∗B+C ∗D+E∗F
(b)
A ∗ B + A ∗ (B ∗ D + C ∗ E)

(c)
A + B ∗ [(C ∗ D + E ∗ (F + G)]
(d)
A ∗ [B + C ∗ (D + E)]
F ∗ (G + H)
32. Convert the following arithmetic expressions from reverse polish notation to infix polish notation.
(a)
ABCDE + ∗ − /
(b)
ABCDE ∗ / − +
(c)
ABCDEF G + ∗ + ∗ + ∗
(d)
ABC ∗ /D − EF/+
33. Write a program to evaluate the arithmetic statement:

A − B + C ∗ (D ∗ E − F )
X=
G+H ∗K
(a) Using a general register computer with three address instructions.
(b) Using a general register computer with two address instructions.
(c) Using an accumulator type computer with one address instructions.
(d) Using a stack organized computer with zero-address operation instructions.
34. In certain scientific computations it is necessary to perform the arithmetic operation (Ai +Bi)(Ci
+ Di) with a stream of numbers . Specify a pipeline configuration to carry out this task . List
the contents of all registers in the pipeline for i=1 through 6.

Unit III
35. Perform the multiplication of two integer numbers 13 and 11 in binary

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36. Perform the following

(a) Perform 274 ÷ 13 using binary division

(b) Perform 11 ÷ 3 using binary division
(c) Perform 1001010 ÷ 1000 using binary division
(d) Perform 100010010 ÷ 11001 using binary division

37. Convert 2.37 decimal into short and long floating point representation

38. Convert -32.55 decimal into short and long floating point representation
39. What is floating point representation explain with suitable example
40. Explain Fixed point arithmetic operations with suitable example
41. Perform the following using fixed point arithmetic operation

(a) 10111 × 10011

(b) 13 × 11
(c) Perform 274 ÷ 13 using binary division
(d) Perform 11 ÷ 3 using binary division
(e) Perform 1001010 ÷ 1000 using binary division
(f) Perform 100010010 ÷ 11001 using binary division
42. Explain arithmetic logic unit in details
43. Explain single bus, two bus and three bus datapath system in ALU

44. Explain control unit design in computer organization

45. What is hardwired and microcoprogrammed control unit, explain in details
46. Differentiate between hardwired and microcoprogrammed control unit

Unit IV
47. Explain the structure of memory hierarchy

48. What are the various memory technologies? Explain in details

49. Differentiate SRAM from DRAM
50. What is direct-mapped cache? Explain with suitable example
51. Consider a cache with 64 blocks and a block size of 16 bytes. To what block number does byte
address 1200 map?
52. What is meant by virtual memory?
53. Explain cache memory with any one mapping technique.

54. Mostly Hard disk is preferred as secondary storage device rather than SRAM. Justify it.
55. Discuss the Memory Hierarchy in computer system with regard to Speed, Size and Cost?

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56. Illustrate the mapping process involved in transformation of data from main to Cache memory.
57. What is virtual memory? Explain the relation between address space and memory space in a
virtual memory system along with its memory table for mapping?

58. Explain Virtual address Mapping using Pages with necessary examples.
59. memory consisting of 4K blocks, a cache memory consisting of 128 blocks, and a block size of 16
words. Find word, block and tag field.
60. Compute word, block and tag field for the system having the following specification: size of the
main memory is 4K blocks, size of the cache is 128 blocks, and the block size is 16 words. Assume
that the system uses associative mapping:
61. Compute the three parameters (Word, Set, and Tag) for a memory system having the following
specification: size of the main memory is 4K blocks, size of the cache is 128 blocks, and the block
size is 16 words. Assume that the system uses set-associative mapping with four blocks per set.

62. Consider fully associative mapped cache of size 16 KB with block size 256 bytes. The size of the
main memory is 128 KB. Find (a) Number of bits in tag (b) Tag directory size
63. Consider fully associative mapped cache of size 512 KB with block size 1 KB. There are 17 bits
in the tag. Find (a) Size of main memory (b) Tag directory size

64. Consider fully associative mapped cache with block size 4 KB. The size of main memory is 16
GB. Find the number of bits in the tag.

Unit V

65. Explain in details the input and output devices

66. Explain I/O mapped and memory mapped I/O
67. Show the interfacing of 8 switches with the processor

68. Show the interfacing of 8 LED’s with the processor

69. Show the interfacing of 8 switches and 8 LED’s with the processor
70. Explain the differences between I/O mapped and memory mapped I/O
71. What is DMA controller, explain its significance for the data transfer

72. Explain in details the data transfer process using DMA controller
73. Explain interrupt and polling in details
74. Explain interrupt and polling with suitable example