Revision sheet of CMP421

CMPN321
 CMP421: Computer Architecture revision sheet for Mid Term
1. Which type of memory is primarily used as cache memory?
a. DRAM
b. RAM
c. ROM
d. SRAM*
2. What are two hardware requirements for computers that will be used to run multiple
virtual machines? (Choose two.)
a. large amounts of RAM*
b. a multicore CPU*
c. a high resolution video card
d. a high speed wireless adapter
e. multiple monitors
3. A source program is usually in _______
a) Assembly language
b) Machine level language
c) High-level language
d) Natural language
4. Which memory device is generally made of semiconductors?
a) RAM
b) Hard-disk
c) Floppy disk
d) Cd disk
5. The small extremely fast, RAM’s are called as _______
a) Cache
b) Heaps
c) Accumulators
d) Stacks
6. . The ALU makes use of _______ to store the intermediate results.
a) Accumulators
 b) Registers
c) Heap
d) Stack
7. . ______ are numbers and encoded characters, generally used as operands.
a) Input
b) Data
c) Information
d) Stored Values
8. The Input devices can send information to the processor.
a) When the status flag is set
b) When the data arrives regardless of the flag
c) Neither of the cases
d) Either of the cases
9. ______ bus structure is usually used to connect I/O devices.
a) Single bus
b) Multiple bus
c) Star bus
d) RAM bus
10. The time delay between two successive initiation of memory operation _______
a) Memory access time
b) Memory search time
c) Memory cycle time
d) Instruction delay
11. The decoded instruction is stored in ______
a) IR
b) PC
c) Registers
d) MDR
12. Which registers can interact with the secondary storage?
a) MAR
b) PC
c) IR
d) R0
13. During the execution of a program which gets initialized first?
a) MDR
b) IR
c) PC
d) MAR
14. Which of the register/s of the processor is/are connected to Memory Bus?
a) PC
b) MAR
c) IR
d) Both PC and MAR
15. The internal components of the processor are connected by _______
a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Ram bus

16. During the execution of the instructions, a copy of the instructions is placed in the
______
a) Register
b) RAM
c) System heap
d) Cache
17. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively.
Suppose A can execute an instruction with an average of 3 steps and B can execute with
an average of 5 steps. For the execution of the same instruction which processor is faster?
a) A
b) B
c) Both take the same time
d) Insufficient information
18. The clock rate of the processor can be improved by _________
a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using the overclocking method
d) All of the mentioned
19. CPI stands for _______
a) Characters Per Instruction Evaluation
b) Computer Processing Instruction Code
c) Average Cycles Per Instructions
d) Standard Processing Enhancement Corporation
20. SPEC stands for _______
a) Standard Performance Evaluation Code
b) System Processing Enhancing Code
c) System Performance Evaluation Corporation
d) Standard Processing Enhancement Corporation
21. 29. If a processor clock is rated as 1250 million cycles per second, then its clock period is
________
a) 1.9 * 10-10 sec
b) 1.6 * 10-9 sec
c) 1.25 * 10-10 sec
d) 8 * 10-10 sec
22. Basic internal computer components are
a) CPU, Data and Program memory, Input and Output Devices
b) Computer, keyboard, screen, and hard disks
c) Embedded systems and microcomputers
d) Hardware and software
23. Brain of computer is ____________
a) Control unit
b) Arithmetic and Logic unit
c) Central Processing Unit
d) Memory
24. What does MBR stand for?
a) Main Buffer Register
b) Memory Buffer Routine
c) Main Buffer Routine
d) Memory Buffer Register
25. What does PC stand for?
a) Program Changer
b) Program Counter
c) Performance Counter
d) Performance Changer
26. Which of the following holds the last instruction fetched?
a) PC
b) MAR
c) MBR
d) IR
27. The functions of execution and sequencing are performed by using ______________
a) Input Signals
b) Output Signals
c) Control Signals
d) CPU
28. Embedded system is
a. computing system with limited resources (Processor, Memory and I/O) used for
performing a specific task.
b. general purpose computing system with huge resources
c. CPU, memory, input, and output devices
d. Used for Graphical Applications
Complete CPU Memory i/o unit inter connection bus system
1- The main computer parts are-----------,---------------,---------------and------------
2- The main processor parts are-----------,-------------------,---------------and----------
3- The MBR stores------------------------------while MAR stores--------------------
4- The address of executed instruction is stored in--------------
5- Main characteristics of computer family are------------------,-------------, -----------
6- Improving computer structure& organization by------------------,--------------------,------
----
7- Computer function is---------------------------------while computer structure is------------
---------
8- Control unit is part of-------------------------
9- MIPS is stands for-----------------------------------
10- Increasing number of buses -------------------------the time of execution
11- Dedicated bus is----------------------while local bus is----------------
12- Asynchronized bus works with-----------------and more ---------------
13- Synchronous bus needs--------------------and more----------------
14- As the bus rate increase the----------------------------is--------------
15- Improving execution time by increasing bus rate is-------------------than ---------------
processor
16- However, as clock speed and logic density increase, a number of obstacles become
more significant. Do you agree with it and why? Explain your answer?
 EXERCISE: CHOOSE CORRECT ANSWER

2. The minimum time delay between two successive memory read operations is ______
a) Cycle time
b) Latency
c) Delay
d) None of the mentioned
5. The logical addresses generated by the cpu are mapped onto physical memory by
____________
a) Relocation register
b) TLB
c) MMU
d) None of the mentioned
5. The memory which is used to store the copy of data or instructions stored in larger memories,
inside the CPU is called _______
a) Level 1 cache
b) Level 2 cache
c) Registers
d) TLB
Cache
1. The reason for the implementation of the cache memory is ________
a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor and memory
c) To reduce the memory access and cycle time
d) All of the mentioned
2. The effectiveness of the cache memory is based on the property of ________
a) Locality of reference
b) Memory localization
c) Memory size
d) None of the mentioned
5. The correspondence between the main memory blocks and those in the cache is given by
_________
a) Hash function
b) Mapping function
c) Locale function
d) Assign function

ALU
4. The sign magnitude representation of -1 is __________
a) 0001
b) 1110
c) 1000
d) 1001
 Exercises

3.1 Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-
associative cache. Assume that the cache has a line size of four 32-bit words. Draw a
block diagram of this cache showing its organization and how the different address
fields are used to determine a cache hit/miss. Where in the cache is the word from
memory location ABCDE8F8 mapped?
Answer
Block frame size= 16 bytes= 4 double words
16 𝐾𝐵𝑦𝑡𝑒𝑠
Number of block frames in cache = 16 𝑏𝑦𝑡𝑒𝑠 = 1024
𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑏𝑙𝑜𝑐𝑘 𝑓𝑟𝑎𝑚𝑒𝑠 1024
Number of sets= = =256 sets
𝐴𝑠𝑠𝑜𝑐𝑖𝑎𝑡𝑡𝑖𝑣𝑖𝑙𝑦 4

3.2 Given the following specifications for an external cache memory: four-way set
associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit
words from main memory; used with a 16-bit processor that issues 24-bit addresses.
Design the cache structure with all pertinent information and show how it interprets the
processor’s addresses

3.3a. Consider an L1 cache with an access time of 1 ns and a hit ratio of H 0.95.
Suppose that we can change the cache design (size of cache, cache organization) such
that we increase H to 0.97, but increase access time to 1.5 ns. What conditions must be
met for this change to result in improved performance?
b. Explain why this result makes intuitive sense.
Equation 4.1 in William (T= TcxH+(1-H)(Tc+Tm) T=TcH+Tc-TcH+(1-H)Tm
T=Tc+(1-H)Tm

Average Access time = Tcache+(1-H)(Tmemory)=1+0.05X(T)

3.4 Consider a single-level cache with an access time of 2.5 ns, a line size of 64 bytes,
and a hit ratio of H 0.95. Main memory uses a block transfer capability that has a first
word (4 bytes) access time of 50 ns and an access time of 5 ns for each word
thereafter.
a. What is the access time when there is a cache miss? Assume that the cache waits
until the line has been fetched from main memory and then re-executes for a hit.
b. Suppose that increasing the line size to 128 bytes increases the H to 0.97.Does this
reduce the average memory access time?

Equation 4.1 in William (T= TcxH+(1-H)(Tc+Tm) T=TcH+Tc-TcH+(1-H)Tm

3.5 A computer has a cache, main memory, and a disk used for virtual memory. If a
referenced word is in the cache, 20 ns are required to access it. If it is in main memory
but not in the cache, 60 ns are needed to load it into the cache, and then the reference
is started again. If the word is not in main memory, 12 ms are required to fetch the word
from disk, followed by 60 ns to copy it to the cache, and then the reference is started
again. The cache hit ratio is 0.9 and the main memory hit ratio is 0.6.What is the
average time in nanoseconds required to access a referenced word on this system?

Correct the statement if wrong and verify it if right

2- Mapping of cache is implement to increase the performance of time False (increases hit ratio

3- Logical address is generated by MMU False (by CPU)

4- Logical cache transfers logical address to physical address False (translates logical address
to physical address)
5- Time of cache miss is the sum of cache access time and memory access time True (As it
search for the
instruction on
cache then
additional
memories
 6- Virtual memory is the cache memory False (Sum of all memories connected to computer and
in it
Dynamic Ram

MODULE ORGANIZATION
If a RAM chip contains only 1 bit per word, then clearly we will need at least a number of
chips equal to the number of bits per word. As an example, Figure 3.5 shows how a
memory module consisting of 256K 8-bit words could be organized. For 256K words, an
18-bit address is needed and is supplied to the module from some external source (e.g.,
the address lines of a bus to which the module is attached).

Figure 3.5 256-KByte Memory Organization

The address is presented to 8 256K 1-bit chips, each of which provides the input/output
of 1 bit. This organization works as long as the size of memory equals the number of
bits per chip. In the case in which larger memory is required, an array of chips is
needed. Figure 3.6 shows the possible organization of a memory consisting of 1M word
by 8 bits per word. In this case, we have four columns of chips, each column
containing 256K words arranged as in Figure 3.6. For 1M word, 20 address lines are
needed. The 18 least significant bits are routed to all 32 modules. The high-order 2 bits
are input to a group select logic module that sends a chip enable signal to one of the
four columns of modules.