1.
The amount of ROM needed to implement a 4-bit
multiplier is ?
a) 64 bits b) 128 bits c) 1 Kbits d) 2 Kbits
1.The amount of ROM needed to implement a 4-bit multiplier is ?
• a) 64 bits b) 128 bits c) 1 Kbits d) 2 Kbits
multiplication of two 4 bit number will result 2*4 bit.
multiplication of two 4 bit number requires 2*4 address lines
ROM size=* =
2.Match the following
(a) Immediate address mode (1) Local variables
(b) Direct address mode (2) Relocatable programs
(c) Indirect address mode (3) Pointer
(d) Index addressing mode (4) Locality of reference
(e) Base address mode (5) Arrays
(f) Relative address mode (6) Constant Operands
a) a6 b1 c3 d5 e2 f4 b) a5 b4 c6 d3 e1 f2
c) a3 b5 c2 d4 e1 f2 d) a6 b5 c2 d3 e1 f4
2.Match the following
(a) Immediate address mode (1) Local variables
(b) Direct address mode (2) Relocatable programs
(c) Indirect address mode (3) Pointer
(d) Index addressing mode (4) Locality of reference
(e) Base address mode (5) Arrays
(f) Relative address mode (6) Constant Operands
a) a6 b1 c3 d5 e2 f4 b) a5 b4 c6 d3 e1 f2
c) a3 b5 c2 d4 e1 f2 d) a6 b5 c2 d3 e1 f4
3.Register renaming is done in pipelined processors
a) as an alternative to register allocation at compile time
b) for efficient access to function parameters and local variables
c) to handle certain kinds of hazards
d) as part of address translation
3.Register renaming is done in pipelined processors
a) as an alternative to register allocation at compile time
b) for efficient access to function parameters and local variables
c) to handle certain kinds of hazards
d) as part of address translation
4.Memory interleaving is done to
a) Increase the amount of logical memory
b) Reduce memory access time
c) Simplify memory interfacing
d) Reduce page
4.Memory interleaving is done to
a) Increase the amount of logical memory
b) Reduce memory access time
c) Simplify memory interfacing
d) Reduce page
5.In an instruction execution pipeline, the earliest that the data TLB
(Translation Lookaside Buffer) can be accessed is
a) before effective address calculation has started
b) during effective address calculation
c) after effective address calculation has completed
d) after data cache lookup has completed
5.In an instruction execution pipeline, the earliest that the data TLB
(Translation Lookaside Buffer) can be accessed is
a) before effective address calculation has started
b) during effective address calculation
c) after effective address calculation has completed
d) after data cache lookup has completed
6.The correct matching for the following pairs is
A)DMA I\0 1)High speed RAM
B)Cache 2)Disk
C)Interrupt I\O 3)Printer
D)Condition code register 4)ALU
a) A4B3C1D2 b) A2B1C3D4
c) A4B3C2D1 d) A2B3C4D1
6.The correct matching for the following pairs is
A)DMA I\0 1)High speed RAM
B)Cache 2)Disk
C)Interrupt I\O 3)Printer
D)Condition code register 4)ALU
a) A4B3C1D2 b) A2B1C3D4
c) A4B3C2D1 d) A2B3C4D1
It has the work of transferring the data between Input Output devices and main memory with very less
interaction with the processor. The direct Memory Access Controller is a control unit, which has the work of
transferring data.
7.The technique whereby the DMA controller steals the access
cycles of the processor to operate is called ------
a) Fast Conning b) Memory Con
c) Cycle Stealing d) Memory Stealing
7.The technique whereby the DMA controller steals the access
cycles of the processor to operate is called ------
a) Fast Conning b) Memory Con
c) Cycle Stealing d) Memory Stealing
8. For the daisy chain scheme of connecting I/O devices, which of
the following statement is true?
a) It gives nonuniform priority to various devices
b) It is only useful for connecting slow devices to a processor
c) It requires a separate interrupt pin on the processor for each device
d) It gives uniform priority to all devices
8. For the daisy chain scheme of connecting I/O devices, which of
the following statement is true?
a) It gives nonuniform priority to various devices
b) It is only useful for connecting slow devices to a processor
c) It requires a separate interrupt pin on the processor for each device
d) It gives uniform priority to all devices
9.A machine with N different opcodes can contain how many
different sequences of micro-operations
a) b) c) d) N
9.A machine with N different opcodes can contain how many
different sequences of micro-operations
a) b) c) d) N
10. A cache has a 64 KB capacity, 128 -byte lines (blocks), and is 4 -way set
associative. The system containing the cache uses 32 -bit addresses. How many
lines (blocks) and sets does the cache have?
a) 64 b) 128 c) 256 d) 32
10. A cache has a 64 KB capacity, 128 -byte lines (blocks), and is 4 -way set
associative. The system containing the cache uses 32 -bit addresses. How many
lines (blocks) and sets does the cache have?
a) 64 b) 128 c) 256 d) 32
cache size=64KB= line/block size=128=
number of lines= =512 number of sets=512/4=128
11.n instruction set of a processor has 125 signals which can be
divided into 5 groups of mutually exclusive signals as follows:
Group 1 : 20 signals, Group 2 : 70 signals, Group 3 : 2 signals, Group
4 : 10 signals, Group 5 : 23 signals.
How many bits of the control words can be saved by using vertical
microprogramming over horizontal microprogramming?
(A) 0
(B) 103
(C) 22
(D) 55
11.n instruction set of a processor has 125 signals which can be divided into 5 groups of mutually exclusive
signals as follows:
Group 1 : 20 signals, Group 2 : 70 signals, Group 3 : 2 signals, Group 4 : 10 signals, Group 5 : 23 signals.
How many bits of the control words can be saved by using vertical microprogramming over horizontal
microprogramming?
(A) 0
(B) 103
(C) 22
(D) 55
in horizontal microprogramming needs 125 bit needed.
But in vertical microprogramming take the logarithm of each group so 5+7+1+4+5=22 bits
12.Arrange the following configurations for CPU in decreasing
order of operating speeds.
1. Hard wired control
2. Vertical microprogramming
3. Horizontal microprogramming
(a) 1 > 2 > 3 (b) 1 > 3 > 2
(c) 2 > 3 > 1 (d) 3 > 2 > 1
12.Arrange the following configurations for CPU in decreasing
order of operating speeds.
1. Hard wired control
2. Vertical microprogramming
3. Horizontal microprogramming
(a) 1 > 2 > 3 (b) 1 > 3 > 2
(c) 2 > 3 > 1 (d) 3 > 2 > 1
13. A given 2 level memory consists of a 30 ns average access time. If
the cache, as well as the memory access time here, is 20 ns and 150
ns, respectively, what would be the hit ratio?
a. 99%
b. 70%
c. 93%
d. 80%
13. A given 2 level memory consists of a 30 ns average access time. If
the cache, as well as the memory access time here, is 20 ns and 150
ns, respectively, what would be the hit ratio?
a. 99%
b. 70%
c. 93%
d. 80%
average m/y access time=h*cache access time+(1-h)*memory access time
30=h*20+(1-h)*150
130h=120
h=.93
14. Which of these memories would have the lowest access time in a
system:
a. Main Memory
b. Magnetic Disk
c. Registers
d. Cache
14. Which of these memories would have the lowest access time in a
system:
a. Main Memory
b. Magnetic Disk
c. Registers
d. Cache
15.The bit used to indicate whether the block was recently used or not
is _______
a) Reference bit
b) Dirty bit
c) Control bit
d) Idol bit
15.The bit used to indicate whether the block was recently used or not
is _______
a) Reference bit
b) Dirty bit
c) Control bit
d) Idol bit
16. SIMD represents an organization that _________
.(A) Refers to a computer system capable of processing several
programs at the same time
(B) Represents organization of single computer containing a control
unit, processor unit and a memory unit
(C) Includes many processing units under the supervision of a common
control unit
(D) None of the above
16. SIMD represents an organization that _________
.(A) Refers to a computer system capable of processing several
programs at the same time
(B) Represents organization of single computer containing a control
unit, processor unit and a memory unit
(C) Includes many processing units under the supervision of a
common control unit
(D) None of the above
17. In a non vectored interrupt.
(A) The branch address is assigned to a fixed location in memory
(B) The interrupting source supplies the branch information to the processor
through an interrupt vector
(C) The branch address is obtained from a register in the processor
(D) None of the above
17. In a non vectored interrupt.
(A) The branch address is assigned to a fixed location in memory
(B) The interrupting source supplies the branch information to the processor
through an interrupt vector
(C) The branch address is obtained from a register in the processor
(D) None of the above
18.A micro-program sequencer
(A) Generates the address of next micro instruction to be executed
(B) Generates the control signals to execute a microinstruction
(C) Sequentially averages all microinstructions in the control memory
(D) Enables the efficient handling of a micro program subroutine
18.A micro-program sequencer
(A) Generates the address of next micro instruction to be executed
(B) Generates the control signals to execute a microinstruction
(C) Sequentially averages all microinstructions in the control memory
(D) Enables the efficient handling of a micro program subroutine
19.How many 32K x 1 RAM chips are needed to provide a memory
capacity of 256K-bytes?
A)8
B)32
C)64
D)128
19.How many 32K x 1 RAM chips are needed to provide a memory
capacity of 256K-bytes?
A)8
B)32
C)64
D)128
256 Kbytes, i.e., 256 x 1024 x 8 bits.
RAM chips of capacity 32 Kbits = 32 x 1024 bits.
Number of RAM chips=(256 * 1024 * 8)/(32 * 1024) = 64
20. The performance of a pipelined processor suffers if :
A)The pipeline stage have different delays.
B)Consecutive instructions are dependent on each other.
C)The pipeline stage share hardware resources
D) All of the above
20. The performance of a pipelined processor suffers if :
A)The pipeline stage have different delays.
B)Consecutive instructions are dependent on each other.
C)The pipeline stage share hardware resources
D) All of the above
21) More than one word put in cache block to:
A)Exploit the temporal locality of reference of a program
B)Exploit the spatial locality of refernce of a program
C)Reduce miss penality
D)None of the above
21) More than one word put in cache block to:
A)Exploit the temporal locality of reference of a program
B)Exploit the spatial locality of reference of a program
C)Reduce miss penalty
D)None of the above
22.Comparing the time T1 taken for a single instruction on a
pipelined CPU with time T2 taken on a nonpipelined but identical
CPU, we can say that
A)T1=T2
B)T1>=T2
C)T1<=T2
D)None of the above
22.Comparing the time T1 taken for a single instruction on a
pipelined CPU with time T2 taken on a nonpipelined but identical
CPU, we can say that
A)T1=T2
B)T1>=T2
C)T1<=T2
D)None of the above
23. Which of the architecture is power
efficient?
a) CISC
b) RISC
c) ISA
d) IANA
23. Which of the architecture is power
efficient?
a) CISC
b) RISC
c) ISA
d) IANA
24. Which of the following statement is false about
dynamic RAM?
(a) DRAM needs a continuously refreshed memory to store data.
(b) It is slower than SRAM.
(c) It is more expensive than SRAM.
(d) All are correct.
24. Which of the following statement is false about dynamic RAM?
(a) DRAM needs a continuously refreshed memory to store data.
(b) It is slower than SRAM.
(c) It is more expensive than SRAM.
(d) All are correct.
25. EPROM is used for
(a) erasing the data of ROM
(b) reconstructing data of ROM
(c) duplicating ROM
(d) erasing and reconstructing data of ROM
26 Which of the following memory storage is slow?
(a) Magnetic disc
(b) RAM
(c) flash memories
(d) Optical disk
26 Which of the following memory storage is slow?
(a) Magnetic disc
(b) RAM
(c) flash memories
(d) Optical disk
Very compact in size and therefore very portable.
Electrical storage: Solid State Storage Devices
High speed of data transfer and low power
(SSD)
consumption.
27. What is the unique characteristic of RAID 6 ?
a) Distributed Parity
b) Stripping
c) Two independent distributed parity
d) Mirroring
27. What is the unique characteristic of RAID 6 ?
a) Distributed Parity
b) Stripping
c) Two independent distributed parity
d) Mirroring
28. Flynn's classification is ________________.
A.SISD
B.SIMD
C.MISD
D.MIMD
E.ALL OF THE ABOVE
28. Flynn's classification is ________________.
A.SISD
B.SIMD
C.MISD
D.MIMD
E.ALL OF THE ABOVE
29. Subtraction in computers is carried out by –
A)1's complement
B)2's complement
C)3's complement
D)9's complement
29. Subtraction in computers is carried out by –
A)1's complement
B)2's complement
C)3's complement
D)9's complement
30 .A computer has a word length of 8 bits (including sign). It is
required to determine the range of integers that can be stored in the
computer. If 2’s complement is used to represent the numbers, then
the range will be
A)-256 to 256
b)-256 to 255
c)-128 to 128
d)-128 to 127
30 .A computer has a word length of 8 bits (including sign).
It is required to determine the range of integers that can be
stored in the computer. If 2’s complement is used to
represent the numbers, then the range will be
A)-256 to 256
b)-256 to 255
c)-128 to 128
d)-128 to 127
31.A processor has an instruction cache with a hit rate of 90% and an
access time of 1 ns. If the cache miss penalty is 20 ns, what is the
average memory access time?
a) 1.1 ns b) 2 ns c) 2.2 ns d)3ns
31.A processor has an instruction cache with a hit rate of 90% and an
access time of 1 ns. If the cache miss penalty is 20 ns, what is the
average memory access time?
a) 1.1 ns b) 2 ns c) 2.2 ns d)3ns
The average memory access time can be calculated using the formula:
Average Access Time = Hit Rate * Access Time + Miss Rate * Miss
Penalty. Since the hit rate is 90% (0.9) and the miss penalty is 20 ns, the
average access time is (0.9 * 1 ns) + (0.1 * 20 ns) = 0.9 ns + 2 ns = 2.2
ns.
32. computer system uses a direct-mapped cache with a cache size of
8 KB and a block size of 32 bytes. How many bits are needed for the
cache index?
a) 5 bits b) 8 bits c) 9 bits d) 11 bits
32. computer system uses a direct-mapped cache with a cache size of
8 KB and a block size of 32 bytes. How many bits are needed for the
cache index?
a) 5 bits b) 8bits c) 9 bits d) 11 bits
the cache size is 8 KB (2^13 bytes) and the block size is 32 bytes (2^5),
the number of cache blocks is 2^13 / 2^5 = 2^8 = 256. Therefore, the
cache index requires 8 bits
33.Which memory type is the closest to the CPU and provides fast
access to frequently used data?
a) Cache memory b) Main memory (RAM)
c) Virtual memory d) Secondary memory (Hard Disk)
33.Which memory type is the closest to the CPU and provides fast
access to frequently used data?
a) Cache memory b) Main memory (RAM)
c) Virtual memory d) Secondary memory (Hard Disk)
34. Which addressing mode uses a base register plus an offset to calculate the
memory address?
a) Immediate addressing mode b) Direct addressing mode
c) Indirect addressing mode d) Indexed addressing mode
34. Which addressing mode uses a base register plus an offset to calculate the
memory address?
a) Immediate addressing mode b) Direct addressing mode
c) Indirect addressing mode d) Indexed addressing mode
35.A computer system uses a 32-bit virtual address and a 4 KB page
size. How many entries are there in the page table?
a) 256 entries b) 512 entries c) 1024 entries
d) 2048 entries
35.A computer system uses a 32-bit virtual address and a 4 KB page
size. How many entries are there in the page table?
a) 256 entries b) 512 entries c) 1024 entries
d) 2048 entries
The number of entries in the page table can be calculated by dividing
the virtual address space size by the page size. Since the virtual address
is 32 bits (2^32) and the page size is 4 KB (2^12), the number of entries
is 2^32 / 2^12 = 2^20 entries.
36. In a pipelined processor, which hazard occurs when the current
instruction depends on the result of a previous instruction that has
not yet completed?
a) Data hazard b) Control hazard
c) Structural hazard d) Pipeline hazard
36. In a pipelined processor, which hazard occurs when the current
instruction depends on the result of a previous instruction that has
not yet completed?
a) Data hazard b) Control hazard
c) Structural hazard d) Pipeline hazard
37.Which cache mapping technique provides the fastest access time
but has limited capacity?
a) Direct mapping b) Associative mapping
c) Set-associative mapping d) Fully associative mapping
37.Which cache mapping technique provides the fastest access time
but has limited capacity?
a) Direct mapping b) Associative mapping
c) Set-associative mapping d) Fully associative mapping
38.Which technique is used to reduce the effect of memory latency
in a pipelined processor?
a) Branch prediction b) Instruction-level parallelism
c) Out-of-order execution d) Loop unrolling
38.Which technique is used to reduce the effect of memory latency
in a pipelined processor?
a) Branch prediction b) Instruction-level parallelism
c) Out-of-order execution d) Loop unrolling
39. Which technique is used to minimize the impact of control
hazards in a pipelined processor?
a) Branch prediction b) Data forwarding
c) Loop unrolling d) Out-of-order execution
39. Which technique is used to minimize the impact of control
hazards in a pipelined processor?
a) Branch prediction b) Data forwarding
c) Loop unrolling d) Out-of-order execution
40. Example of immediate addressing mode is:
a) MOV A, B b) ADD A, [B]
c) SUB A, #10 d) JMP LABEL
40. Example of immediate addressing mode is:
a) MOV A, B b) ADD A, [B]
c) SUB A, #10 d) JMP LABEL
41. is the sequence of operations performed by CPU in
processing an instruction:
a)Execute cycle
b)Fetch cycle
c)Decode
d)Instruction cycle
41. is the sequence of operations performed by CPU in
processing an instruction:
a)Execute cycle
b)Fetch cycle
c)Decode
d)Instruction cycle
42. what is the BCD for a decimal number 559:
a. [0101 0101 1001]
b. [0101 0001 1010]
c. [0101 1001 1001]
d. [1001 1010 0101]
42. what is the BCD for a decimal number 559:
a. [0101 0101 1001]
b. [0101 0001 1010]
c. [0101 1001 1001]
d. [1001 1010 0101]
43. A code in which the total number of 1s in a valid (n+1) bit code
word is even, this is called an
a)Even parity code
b)Odd parity code
c)Both
d)None of these
43. A code in which the total number of 1s in a valid (n+1) bit code
word is even, this is called an
a)Even parity code
b)Odd parity code
c)Both
d)None of these
44. Which operation is extremely usefulin serial transfer of
data:
a)Logical micro operation
b)Arithmetic micro operation
c)Shift micro operation
d)None of these
44. Which operation is extremely useful in serial transfer of
data:
a)Logical micro operation
b)Arithmetic micro operation
c)Shift micro operation
d)None of these
45. Which method is used to detect double errors and pinpoint
erroneous bits:
a)Even parity method
b)Odd parity method
c)Check sum method
d)All of these
45. Which method is used to detect double errors and pinpoint
erroneous bits:
a)Even parity method
b)Odd parity method
c)Check sum method
d)All of these
46. Carry, Overflow, negative, zero results are also called ___.
a. Flag bits
b. Conditional bits
c. Status bits
d. None of the above
46. Carry, Overflow, negative, zero results are also called ___.
a. Flag bits
b. Conditional bits
c. Status bits
d. None of the above
46. Carry, Overflow, negative, zero results are also called ___.
a. Flag bits
b. Conditional bits
c. Status bits
d. None of the above
47. ___ control unit determines the address of the next instruction
be executed and loads it into the program counter.
a. Instruction Interpretation
b. Instruction sequencing
c. Instruction regulation
d. Instruction composition
47. ___ control unit determines the address of the next instruction
be executed and loads it into the program counter.
a. Instruction Interpretation
b. Instruction sequencing
c. Instruction regulation
d. Instruction composition
48. In ________ protocol the information is directly written into the
main memory.
a) Write through
b) Write back
c) Write first
d) None of the mentioned
48. In ________ protocol the information is directly written into the
main memory.
a) Write through
b) Write back
c) Write first
d) None of the mentioned
48. In ________ protocol the information is directly written into the
main memory.
a) Write through
b) Write back
c) Write first
d) None of the mentioned
49. In the case of, Zero-address instruction method the operands
are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
49. In the case of, Zero-address instruction method the operands
are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
50. In the following indexed addressing mode instruction, MOV
5(R1), LOC the effective address is ______
a) EA = 5+R1
b) EA = R1
c) EA = [R1]
d) EA = 5+[R1]
50. In the following indexed addressing mode instruction, MOV
5(R1), LOC the effective address is ______
a) EA = 5+R1
b) EA = R1
c) EA = [R1]
d) EA = 5+[R1]
