CBSE205L
Problem Set
Winter Semester 2024-25
Dr. Sunil Kumar
Problem
• Write the code to implement the expression A=(B*C)-D on 3-address, 2-
address, and 1-address machines. Do not rearrange the expression. In
accordance with programming language practice, computing expression
should not change the values of its operands. And also computes the
total memory traffic, memory to store and decode in bytes for both
instruction fetch and instruction execution for code and implements the
expression evaluation for the above said three machines. Assume that
opcode occupies one byte, address occupies three bytes, and data
values occupy three bytes and word length is three bytes.
• Assume that a benchmark has 100 instructions with a clock rate of
300 MHz. 20% of instructions are loads/stores (each takes 3 cycles),
40% of instructions are added (each takes 2 cycles), and 40% of
instructions are square root (each takes 60 cycles), what is the CPI
and MIPS rate for this benchmark?
• Explain the limitations of MIPS and MFLOPS.
• Calculate the CPU execution time if the processor's clock rate is 500
MHz, there are 50000 instructions to execute, and each instruction
requires 2.5 CPU cycles to complete.
• Suppose you have two implementations (A and B) of the same
instruction set architecture. Machine A has a clock cycle time of 4ns
and a CPI of 2.0 for a program. Machine B has a clock cycle time of
1ns and a CPI of 2 for a program. Which machine is faster for this
program, and by how much? Justify it.
• Our favourite program runs in 12 seconds on computer A, which has a 4GHz clock. We are trying
to help a computer designer build a computer, Which will run this program in 6 seconds. The
designer has determined that a substantial increase in the clock rate is possible, but this increase
will affect the rest of the CPU design, causing computer B to require 1.5 times as many clock cycles
as computer A for this program. What clock rate should we tell the designer to target?
• Consider the execution of a program which results in the execution of 2 million instructions
on a 500-MHz processor. The instruction mix and the CPI for each instruction type are given in
below the table. Compute MIPS (Million Instructions Per Second) Rating using given data.
• Consider two different machines, with two different instruction sets, both of which have a
clock rate of 200 MHz. The following measurements are recorded on the two machines
running a given set of benchmark programs: Determine the effective CPI, MIPS rate, and
execution time for each machine. Comment on the results.
ADDRESSING MODES - EXAMPLES - Address Memory
300 Load to AC Mode
PC = 300 301 Address = 500
302 Next instruction
R1 = 400
399 450
XR = 200
400 700
AC
500 800
Calculate Effective Addresses? 600 900
Addressing Effective Content 702 325
Mode Address of AC
800 300
Example 2: cache calculations
Main memory : 1024KB
Cache Line : 64 bytes
Cache Memory : 128KB TAG Line Number Line Offset
• Direct mapped:
TAG SET Line Offset
• 2-way associative
TAG SET Line Offset
• 4-way associative
Problems: Direct Mapping
• Consider a cache consisting of 64 blocks of 8 words each, for total of
2048(2K) words. Assume that the main memory is addressable by 16
bit address. Main memory is 64K which will be viewed as 4K
(4×1024=4096) blocks of 8 words each.
• MM: 2 GB, Cache Size: 512 MB, Block Size: 4 KB, Address bits?
• MM: 8 GB, Block Size: 16KB, No. of Tag bits: 8, Cache size?
Problem
• MM size: 64B, Cache Size: 32B, Block Size: 4 B, 2-way set associative.
Main memory address?
• MM size: 128 KB, Cache Size: 8 KB, Block Size: 128 B.
• Main memory address split:
1. 2-wat Set Associative
2. 4-wat Set Associative
3. 8-wat Set Associative
Problem
• MM Size: 8 MB, Block Size: 32 B, Tag bits: 10, 4-way Set Associative.
1. Main memory address split?
2. Cache Size?
• Cache Size: 1MB, Tag bits: 8, 4-way Set Associative. Byte addressable
MM size?
• Consider a fully associative mapped cache of size 64 KB with block size
512 bytes. The size of main memory is 128 KB.
1.Number of bits in tag
2.Tag directory size
Problem
• Consider a 32-bit microprocessor that has an on-chip 16-kB four-
way set-associative cache. Assume that the cache has a line size
of four 32-bit words. Draw a block diagram of this cache showing
its organization and how the different address fields are used to
determine a cache hit/miss. Identify the set number in cache for
mapping the given memory address FFFF6E3B.
1. Design 256 × 8 – bit RAM using 128 × 8 – bit RAM chips and 1024 × 16 – bit ROM
using 512 × 8 – bit ROM chips. and two interface units with 256 registers each. Each
register size is 8 bits. A memory mapped I/O configuration is used. The two higher -order
bits of the address bus are assigned 00 for RAM, 01 for ROM, and 10 for interface
registers.
a. Compute total number of decoders are needed for the above system?
b. Design a memory-address map for the above system
c. Show the chip layout for the above design
2. Design 256 × 16 – bit RAM using 256 × 8 – bit RAM chips and 256 × 8 – bit
ROM using 128 × 8 – bit ROM chips.
• Example 1: Consider Cache reference string: 1, 3,5,6,7,8 0, 3, 5,
6, 3 with 3 number of blocks in cache memory. Find the number of
cache miss for FIFO, LRU, LFU, Optimal page replacement.
A computer system employs a write-back cache with a 70% hit ratio for writes. The
cache operates in "Look Aside" and has a 80% read hit ratio. Reads account for 60%
of all memory references and writes account for 40%.If the main memory cycle time
is 200ns and the cache access time is 30ns, what would be the average access time for
all references (reads as well as writes)?
Exercise
• How control unit is different from ALU in the CPU?
• Distinguish between Hardwired Control Unit and Micro-Programmed
Control Unit.
• I/O Fundamental: Handshaking, Buffering
