Scribd
Upload
72 views15 pages

Assignment Set 03

The document discusses analyzing cache performance in a CPU-OS simulator by varying block size, cache size, and replacement algorithms. It also includes problems calculating CPI, MIPS rate, and execution time given an instruction mix and cycle counts, as well as determining cache indexing and tag bits for a direct mapped cache.

Uploaded by

Prabin Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
72 views15 pages

Assignment Set 03

The document discusses analyzing cache performance in a CPU-OS simulator by varying block size, cache size, and replacement algorithms. It also includes problems calculating CPI, MIPS rate, and execution time given an instruction mix and cycle counts, as well as determining cache indexing and tag bits for a direct mapped cache.

Uploaded by

Prabin Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 15

Contents

1. CPU-OS simulator questions. .......................................................................................................... 1


2. Problems that needs to be solved .................................................................................................. 2

1. CPU-OS simulator questions.


Please download CPU-OS simulator from the following link:

https://drive.google.com/drive/folders/12YUK52RQ-JhP0ddj6CD_oifW4sTMbsBl?usp=sharing

Enter the following program in CPU-OS simulator and observe, analyse and report metrics in the
sub questions with screenshots.

Please use the Documentation File provided to document all the results of this Assignment.
A. In the CPU-OS Simulator window. Select the Cache-Pipeline Tab. Select Cache type as
"Instruction". Click show cache. When the cache-control window opens change the
above mapping to Fully associative mapping, replacement algorithm as FIFO. Keep
block size as 2, cache size as 4. Report the total hits and misses. Vary the block size in
steps from 2 to 32 while retaining the cache size = 16. Tabulate the misses, hit and
calculate the hit ratio. Conclude on the optimal hit ratio. Explain the change and impact
on the hit ratio.

A. In the CPU-OS Simulator window. Select the Cache-Pipeline Tab. Select Cache type as
"Instruction". Click show cache. When the cache-control window opens change the
above mapping to Fully associative mapping, replacement algorithm as FIFO. Vary cache
size from 4 to 32 keeping block size constant at 16. Report the total hits and misses and
compute the Hit Ratio. Repeat for other Replacement Algorithms.

 Provide parameter and hit ratio screenshots.


 Explain the changes in the Hit Ratio.
 Compare and contrast different replacement algorithms and their effectiveness
with respect to this example.

2. Problems that needs to be solved


Please note this does not need CPU-OS simulator.

2. A 20 MHZ processor runs a benchmark program. Executed program consists of 100,000


instruction executions with the following instruction mix and clock cycle count.

Instruction type Instruction count Cycles per


instruction
Data transfer 40,000 2
Control transfer 20,000 2
Floating point 18,000 2
Integer 22,000 1

Calculate CPI, MIPS rate, execution time of this program.


3. Consider a direct mapped cache of size 32kb with block size of 32 bytes. CPU generates 32
bit addresses. What are the number of bits needed for cache indexing and the number of
tag bits respectively?

Solution 1.

You might also like