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Different File Formats (file extensions) Powered by

There are different type of the files generated during a design cycle or data received by the library vendor/foundry. Few of them Search This Blog
having specific extension. Just to know the extension, you can easily identity the type of content in that file.

I am listing down of the file extension. Please let me know if you find any extension is missing. I will add those later on.

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File Extensions:
*.v - Verilog source file. Normally it’s a source file your write. Design Compiler, and IC Compiler can use this format
for the gate-level netlist.
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*.vg, .g.v - Verilog gate-level netlist file. Sometimes people use these file extension to differentiate source files and
gate-level netlists.
*.svf - Automated setup file. This file helps Formality process design changes caused by other tools used in the with Google Friend Connect
design flow. Formality uses this file to assist the compare point matching and verification process. This information
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facilitates alignment of compare points in the designs that you are verifying. For each automated setup file that you
load, Formality processes the content and stores the information for use during the name-based compare point
matching period.
*.ddc - Synopsys internal database format. This format is recommended by Synopsys to hand gate-level netlists.
*.vcd - Value Change Dump format. This format is used to save signal transition trace information. This format is in
text format, therefore, the trace file in this format can get very large quickly. There are tools like vcd2vpd, vpd2vcd, and
vcd2saif switch back and forth between different formats.
*.vpd - VCD Plus. This is a proprietary compressed binary trace format from Synopsys. This file format is used to save
signal transition trace information as well. Already a member? Sign in
*.saif - Switching Activity Interchange Format. It’s another format to save signal transition trace information. SAIF
files support signals and ports for monitoring as well as constructs such as generates, enumerated types, records,
array of arrays, and integers.
*.tcl - Tool Command Language (Tcl) scripts. Tcl is used to drive Synopsys tools.
*.sdc - Synopsys Design Constraints. SDC is a Tcl-based format. All commands in an SDC file conform to the Tcl
syntax rules. You use an SDC file to communicate the design intent, including timing and area requirements between
EDA tools. An SDC file contains the following information: SDC version, SDC units, design constraints, and
comments.
*.lib - Technology Library source file. Technology libraries contain information about the characteristics and
functions of each cell provided in a semiconductor vendor’s library. Semiconductor vendors maintain and distribute the
technology libraries. In our case the vendor is Synopsys. Cell characteristics include information such as cell names,
pin names, area, delay arcs, and pin loading. The technology library also defines the conditions that must be met for a
functional design (for example, the maximum transition time for nets). These conditions are called design rule
constraints. In addition to cell information and design rule constraints, technology libraries specify the operating
conditions and wire load models specific to that technology.
*.db - Technology Library. This is a compiled version of *.lib in Synopsys database format.
*.plib - Physical Library source file. Physical libraries contain process information, and physical layout information of
the cells. This information is required for floor planning, RC estimation and extraction, placement, and routing.
*.pdb - Physical Library. This is a compiled version of *.plib in Synopsys database format. Total Pageviews

*.slib - Symbol Library source file. Symbol libraries contain definitions of the graphic symbols that represent library
cells in the design schematics. Semiconductor vendors maintain and distribute the symbol libraries. Design Compiler
3,015,701
uses symbol libraries to generate the design schematic. You must use Design Vision to view the design schematic.

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When you generate the design schematic, Design Compiler performs a one-to-one mapping of cells in the netlist to
cells in the symbol library.
*.sdb - Symbol Library. This is a compiled version of *.slib in Synopsys database format.
*.sldb - DesignWare Library. This file contains information about DesignWare libraries.
*.def - Design Exchange Format. This format is often used in Cadence tools to represent physical layout. Synopsys
tools normally use Milkyway format to save designs.
*.lef - Library Exchange Format. Standard cells are often saved in this format. Cadence tools also often use this
format. Synopsys tools normally use Milkyway format for standard cells.
*.rpt - Reports. This is not a proprietary format, it’s just a text format which saves generated reports by the tools when Subscribe To VLSI EXPERT
you use the automated makefiles and scripts.
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*.tf - Vendor Technology File. This file contains technology-specific information such as the names, characteristics
(physical and electrical) for each metal layer, and design rules. These information are required to route a design. Comments
*.itf - Interconnect Technology File. This file contains a description of the process crosssection and connectivity
section. It also describes the thicknesses and physical attributes of the conductor and dielectric layers.
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*.map - Mapping file. This file aligns names in the vendor technology file with the names in the process *.itf file.
2016 (1)
*.tluplus - TLU+ file. These files are generated from the *.itf files. TLUPlus models are a set of models containing Basic of Timing
advanced process effects that can be used by the parasitic extractors in Synopsys place-and-route tools for modeling. Analysis in Physical 2015 (15)
Design
*.spef - Standard Parasitic Exchange Format. File format to save parasitic information extracted by the place and 2014 (15)
route tool. "Timing Paths" : Static 2013 (12)
*.sbpf - Synopsys Binary Parasitic Format. A Synopsys proprietary compressed binary format of the *.spef. Size of Timing Analysis (STA)
2012 (15)
basic (Part 1)
the file shrinks quite a bit using this format.

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Different File Formats (file extensions) |VLSI Concepts http://www.vlsi-expert.com/2011/02/different-file-formats-file-extensions...

*.mw( Milkyway database) The Milkyway database consists of libraries that contain information about your design. Delay - "Wire Load 2011 (17)
Libraries contain information about design cells, standard cells, macro cells, and so on. They contain physical Model" : Static Timing September (1)
descriptions, such as metal, diffusion, and polygon geometries. Libraries also contain logical information (functionality Analysis (STA) basic
(Part 4c) August (1)
and timing characteristics) for every cell in the library. Finally, libraries contain technology information required for
design and fabrication. Milkyway provides two types of libraries that you can use: reference libraries and design May (1)
Delay - "Interconnect
libraries. Reference libraries contain standard cells and hard or soft macro cells, which are typically created by Delay Models" : Static April (2)
vendors. Reference libraries contain physical information necessary for design implementation. Physical information Timing Analysis (STA) March (5)
includes the routing directions and the placement unit tile dimensions, which is the width and height of the smallest basic (Part 4b)
February (7)
instance that can be placed. A design library contains a design cell. The design cell might contain references to
"Setup and Hold Time Basic of Timing
multiple reference libraries (standard cells and macro cells). Also, a design library can be a reference library for Violation" : Static Analysis in
another design library. The Milkyway library is stored as a UNIX directory with subdirectories, and every library is Timing Analysis (STA) Physical Design
managed by the Milkyway Environment. The top-level directory name corresponds to the name of the Milkyway library. basic (Part 3b)
Clock
Library subdirectories are classified into different views containing the appropriate information relevant to the library Reconvergence
"Setup and Hold
cells or the designs. In a Milkyway library there are different views for each cell, for example, NOR1.CEL and Time" : Static Timing Pessimism
NOR1.FRAM. This is unlike a .db formatted library where all the cells are in a single binary file. With a .db library, the Analysis (STA) basic (CRP) basic
entire library has to be read into memory. In the Milkyway Environment, the Synopsys tool loads the library data (Part 3a) Different File
relevant to the design as needed, reducing memory usage. The most commonly used Milkyway views are CEL and Formats (file
"Examples Of Setup extensions)
FRAM. CEL is the full layout view, and FRAM is the abstract view for place and route operations. and Hold time" : Static
simv - Compiled simulator. This is the output of vcs. In order to simulate, run the simulator by ./simv at the Timing Analysis (STA) Process Variation -
basic (Part 3c) Effects On
command line. Design, Different
alib-52 - characterized target technology library. A pseudo library which has mappings from Boolean functional circuits "Time Borrowing" : T...
to actual gates from the target library. This library provides Design Compiler with greater flexibility and a larger solution Static Timing Analysis ETM (Extracted
(STA) basic (Part 2) Timing Models) -
space to explore tradeoffs between area and delay during optimization.
More detail
Effect of Wire Length
On the Slew: Static ETM (Extracted
Timing Analysis (STA) Timing Models)
Basic (Part-7a) basics
Posted by VlsiExpertGroup at 2:34 AM
Synopsys Design
Reactions: Effect of Threshold Constraints
voltage: Static Timing (SDC) Basics
Analysis (STA) Basic
(Part-7c)
2010 (5)
11 comments: 2008 (1)
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Keertiprasad February 27, 2011 at 12:14 PM
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Everything in Brief but very useful. Thanks. A visitor from United
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good effort :-)
U miss the .sdf arrived
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Hi ...
.sdf(standerd delay format) viewed "DIGITAL
input for postSTA ..and contains cell & net delay info ... BASIC
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Analysis basic
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You could include .upf file extensions too.
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Anonymous July 2, 2013 at 4:21 PM

what is nxtgrd and ircx files which are used during physical verification?

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Sarah Martin June 1, 2015 at 3:27 PM

Great Post!

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johny steyn June 25, 2015 at 12:24 PM

Great Post! I was searching for these file extensions from a long time and finally I got these all together which help many of new

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Different File Formats (file extensions) |VLSI Concepts http://www.vlsi-expert.com/2011/02/different-file-formats-file-extensions...

bloggers including me to know the type of content of file by simply through file extensions. Thanks again and I’ll be grateful if you
continue this posting in future too. I’ll look forward for your new updates. If you are searching for the best VLSI Training Institute in
Jaipur then VLSI Engitech Pvt Ltd is the best option to choose.

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