DSP

• Digital Signal Processing (DSP)

– Is the manipulation of digital signals in order to modify their characteristic or to extract
useful information. Why digital and not analog?
– Digital signal allow programmability,
– Digital circuit allow for stable output than analog
– Microprocessors and computers have become so powerful
– only digitized signal can be processed by computers.
• Digital Signal Processor (DSP)
– DSP is a specialized microprocessor optimized for signal processing.
– General purpose microprocessors such as Pentium series microprocessors that are used
in PC are not optimized for signal processing purposes.

analog
A/D DSP D/A analog
signal
converter algorithms converter signal

General Block Diagram of a DSP System

Hardware tools:
DSP (DSKs), evaluation modules (EVMs) and other DSP boards
 For real-time DSP experiments, a
DSK/EVM/Emu. is suitable along with a host
system, which can be a typical PC.

Software tools:
Assembly language tools, DSP simulator, C
compiler and C source debugger.

Code Composer Studio (CCS)  IDE:

Simulates, C compiles and works with a DSK
DSP Software Development flow
C
Source
file

C
Compiler
Assemble
r Source

Assembler
Library
Archiver COFF build utility
Object Run time
file supp.Library
Library of Linker
Object file
Exec. Debugging
COFF file tools on a
To PC for PC
Emulatio
Absolute Cross-reference Hex n
lister lister conversion
utility
Hexadecimal
Object file

To
TMS320CXX
target system
Software Life Cycle - Waterfall Method
Requirements
Analysis
Architectural
Design
Detailed
Design

Coding

Unit Test

Integration
Test

System Test
 Texas Instruments’ TMS320 family

C2000 C5000 C6000

Lowest Cost Efficiency Performance &

Control Systems Best MIPS per Best Ease-of-Use
 Motor Control Watt / Dollar / Size
 Storage
 Multi Channel and Multi
 Wireless phones
 Digital Ctrl Systems
Function App's
 Internet audio players
 Comm Infrastructure
 Digital still cameras
 Wireless Base-stations
 Modems
 DSL
 Telephony
 Imaging
 VoIP
 Multi-media Servers
 Video
 TMS320 DSP Families
C2000 C5000 C6000

>50 Products >100 Products >30 Products

ASP: $3 - $15 ASP: $5 - $120 ASP: $10 - $350
 World’s most code-efficient DSP  World’s most power-  World’s highest-
efficient DSP performance DSP
 Advanced embedded control
applications  World’s most popular DSP  Used in high-bandwidth
comms and video
 Leadership integration of analog  Heart of handheld solutions equipment
and high-speed Flash memory in Internet era
 C55x fully code compatible  C64x fully code
 C28x fully code compatible compatible
Floating vs. Fixed point processors
• Applications which require:
– High precision.
– Wide dynamic range.
– High signal-to-noise ratio.
– Ease of use.
Need a floating point processor.
• Drawback of floating point processors:
– Higher power consumption.
– Can be more expensive.
– Can be slower than fixed-point counterparts and
larger in size.
Floating vs. Fixed point processors
• It is the application that dictates which device and platform to
use in order to achieve optimum performance at a low cost.
• For educational purposes, use the floating-point device (C6713)
as it can support both fixed and floating point operations.
• Fixed point processors:
• TMS320c2X, TMS320c5X and
TMS320c62X
• (Modulators, demodulators, carrier and clock
recovery etc.,)

• Floating point processors:

• TMS320c3X and TMS320c67X
• (Speech processing, control systems, equalization
etc.,)
Code Composer Studio
 DSP industry’s first
comprehensive, open
Integrated Development
Environment (IDE)
 Advanced visualization
 Intuitive ease-to-use
 Third-party plug-ins
 Visualization without
stopping the processor
The CCS is an integrated suite of DSP software development
tools
efficient 'C6000 C compiler, Assembly Optimizer with
the Code Composer IDE, Advanced Data Visualization,
standard open APIs, DSP/BIOS and Real-Time Data
Exchange(RTDX)
• Optimizing C compiler  fully exploits the architecture's instruction-
level parallelism and orthogonal
instruction set

• Assembly optimization  supports automatic scheduling, optimizing

and separation of parallel tasks from linear
assembly code

• Debugger  Conditional or hardware breakpoints are based on full C-

expressions, local variables or CPU register
symbols.

• Real-Time Analysis Using RTDX technology, DSP/BIOS provides a

real- time window into the target system
 Project Memory
files C Source
map
file

Data Graphics Dis-Assembly

display Display window
(Assembly source)
 Code Composer Studio CPU
Menus or Icons Help Window

Project Manager:
Source & object files
File dependencies
Compiler, Assembler &
Linker build options

Full C/C++ & Assembly

Debugging:
C & ASM Source
Mixed mode
Disassembly (patch)
Set Break Points
Set Probe Points

Editor:
Structure Expansion

Status Watch Window Graph Memory Window

Window Window
 Real-Time Processing
• Real-time processing means:
– The processing of a particular sample must occur within a given time
period or the system will not operate properly.
– Real-time DSP is inherently an interrupt driven process. The input
samples should only be processed using interrupt service routines
(ISR).
• Hard real-time system
– The system will fail if the processing is not done in a timely manner.
• Soft real-time system
– The system will tolerate some failures to meet real-time targets and still
continue to operate, but with some degradation in performance.

• The performance demands and power constraints of real-time

systems often mandate specialized hardware.
– That may include the digital signal processor (DSP), programmable
logic devices, application specific integrated circuits (ASIC), and etc.
 Real-time processing
Waiting Time
Processing Time

n n+1
Sample Time

• We can say that we have a real-time application if:

– Waiting Time  0
• DSP processors have to perform tasks in real-time,
so how do we define real-time?
• The definition of real-time depends on the
application.
 A Setup for Non-real-time Experiments

Code Composer Studio (IDE)

or
DSP Compiler / Assembler /
Linker / Simulator / Debugger

I/O through data

files

Host PC

Assembly language code and implementation flavor is present,

but real-time experiments cannot be carried out using this
setup.
 A Setup for Real-time Experiments

Code Composer Studio (IDE) mic

or
DSP Compiler / Assembler /
Linker / Simulator / Debugger

Signal
gen.

I/P O/P

Head-
phones
Host PC
DSP EVM

CRO

Assembly language code and implementation flavor is present.

Real-time experiments can be carried out using this setup.
Hardware vs. Microcode multiplication
• DSP processors are optimized to perform
multiplication and addition operations.
• Multiplication and addition are done in hardware
and in one cycle.
• Example: 4-bit multiply (unsigned).
Hardware Microcode
1011 1011
x 1110 x 1110
10011010 0000 Cycle 1
1011. Cycle 2
1011.. Cycle 3
1011... Cycle 4
10011010 Cycle 5
 Why Digital Control Techniques?
Controller PWM Power Elec.
Analog
or
Digital ?? Sensor(s)

Analog Controller Digital Controller

High bandwidth Insensitive to environment (temp, drift,…)
+ 
 High resolution

 S/w programmable / flexible solution

 Easy to understand / use  Precise / predictable behavior

 Historically lower cost  Advanced control possible (non-linear, multi-variable)

 Can perform multiple loops and “other” functions

 Component drift and aging / unstable  Bandwidth limitations (sampling loop)

 Component tolerances  PWM frequency and resolution limits

 Hardwired / not flexible  Numerical problems (quantization, rounding,…)

 Limited to classical control theory only  AD / DA boundary (resolution, speed, cost)

 CPU performance limitations
 Large parts count for complex systems
 Bias supplies, interface requirements
 Benefits of Digital Control
Filter Output
VI V PFC VI DC/DC V I
V I

Bridge
8 4

5 1
Traditional Analog
Inrush/ DC/DC
DC/DC Current/Load
Current/Load
Hot-plug PFC Control Converter
Converter Sharing
Sharing Power Supply
Control Control
Control Control
Control  Multiple chips for
Interface Multi-mode
Multi-mode control
Powercontrol
Power control
Circuit  Micro-controller for
Monitor Supervisory
Supervisory
(MCU)
(MCU?)
MCU
MCU Housekeeping
Housekeeping supervisory
Circuits
Circuits
 Dedicated design
Aux P/S To Host

Eliminate Components
Filter Output
V PFC DC/DC V Reduce Manufacturing Cost
Bridge
Better Performance Across Corners

One Design, Multiple Supplies

Failure Prediction
Aux P/S One Device, Multiple DC Outputs

Variable DC Output
Digital controller enables multi-threaded applications
 Analog Control System
e C P
R
+  (controller) (plant)
Y
-
“Analog Computation”
Differential equations
C2 C

C1
R
Energy
R2 R
R
Storage
Elements
R1
L

d 3 y(t ) d 2 y(t ) dy(t )

  k 0y(t )  f (t )
R2  1  R1C1s  3
k 2 2
k1
C ( s)    dt dt dt
R1  1  R2C2 s  Differential equations
1st, 2nd, 3rd,…order

Need to find: Laplace Transform

R1, R2, C1, C2
 Digital Control System
E Cd U D-A P
R
+  (controller) ZOH (plant) Y
-
A-D
S&H

Difference equation C

U (n)  a2  U (n  2)  a1  U (n  1)  Energy
R
Storage
b2  E (n  2)  b1  E (n  1)  b0  E (n) Elements
L
where  E (n)  R (n)  Y (n)

d 3 y(t ) d 2 y(t ) dy(t )

Need to find: 3
 k 2 2
 k1 k 0y(t )  f (t )
dt dt dt
a1, a2, b0, b1, b2 Differential equations
1st, 2nd, 3rd,…order
Laplace Transform
OR
Z Transform
 Time Sampled Systems
Digital Processor

- Control
A-D  Law
D-A
+
Ref

y(t) y(n) u(n) u(t)

sample
period
T

t t t t
Continuous Discrete
time signal time signal
Digitally Controlled Power Supply

DAC
(PWM)

DSC
“Plant”
ADC

0110101100
1011011101
0010100111
“High fidelity”
Translation boundary
 System Mapping
PFC – 3ph Interleaved
VOUT
F280xx Vin

Ch1
DSP ADC
Ch2
32 bit core
12 bit
60~100
(80nS)
MHz Ch16

1A
ePWM1 1B
2A Phase-Shifted Full Bridge
ePWM2 2B
3A VIN VOUT
ePWM3 3B

8A
ePWM8 8B
 Software Library Approach
CNTL CNTL Buck E HR E
P P
2P2Z 3P3Z Single W
Buck W
Ref Ref DRV M Single M
FB
Uout
FB
Uout DRV
Duty H EPWMnA Duty H EPWMnA
W W
Control 2-pole / 2-zero Control 3-pole / 3-zero
Buck Single Output High Resolution Buck
IIR-FILT IIR-FILT
2P2Z 3P3Z EPWM1A PFC E
MPIL E
EPWM1B 2PHIL P
P W
f f DRV W DRV M
EPWM2A
M
Duty EPWMnA
In Out In Out EPWM2B H
H Adj W EPWMnB
2nd order IIR filter 3rd order IIR filter Duty W
Power Factor 2-phase
Multi-Phase Interleaved Interleaved
SinGen1 SGenHP1

HHB
E IBM
P E
Freq Freq DRV W FB P EPWMnA

Gain Out Gain Out

M DRV W
EPWMnB
M
EPWMnA
Offset Offset Duty H In
EPWM(n+1)A
W EPWMnB H
DelLL
Sine Wave generator High precision Sine Gen W EPWM(n+1)B
Half H-Bridge DelRL

IBM method Full Bridge

SSartSEQ
INV
PSFB E
SQR EPWMnA Ch0
DRV P
ADC
A
Ch1
W D
EPWMnB Ch3
In Out
Delay
M DRV C
Ch4
Phase
EPWM(n+1)A
Inverse Square function Slope Out H H
Llegdb
W Rslt W
Target EPWM(n+1)B
Rlegdb

Soft Start and Sequencing Phase Shifted Full Bridge Analog-Digital Converter driver
CPU dependency only:
• Math / algorithms
Peripheral Drivers
Depends on:
• Per-Unit math (0-100%) • PWM frequency
• Independent of Hardware • System clock frequency
E
BUCK P
CNTL DRV W
2P2Z M
Vref Ref Duty H
(Q15) Out In EPWM1A
Fdbk (Q15) W

ADC
SEQ1 A
DRV D
Vout Rslt0
C
ADC_A0
(Q15)
H ADC_A1
W ADC_A2
// pointer & Net declarations
int *CNTL_Ref1, *CNTL_Fdbk1, *CNTL_Out1; ADC_A3
int *BUCK_In1, *ADC_Rslt1;
int Vref, Duty, Vout;

// “connect” the modules Depends on:

CNTL_Ref1 = &Vref; • # ADC bits (10 / 12 ?)
CNTL_Out1 = &Duty; BUCK_In1 = &Duty;
CNTL_Fdbk1 = &Vout; ADC_Rslt1 = &Vout; • Unipolar, Bipolar ?
• Offset ?
 Dual Buck Example
BG ISR
Start / Stop trigger
Single Power Stage
Voltage E

S-start / SEQ Controller BUCK P Vin Vout1

W
CNTL
DRV M
2P2Z
Vref1 H
Ref Uout DutyCmd1 Duty W EPWM1A DRV Buck
FB
400 kHz
400 kHz
A
ADC D
DRV C

H
Vout1 rslt0 W Ch0
400 kHz

Single Power Stage

Voltage E

S-start / SEQ Controller BUCK P Vin Vout2

W
CNTL
DRV M
2P2Z
Vref2 H
Ref Uout DutyCmd2 Duty W EPWM2A DRV Buck
FB
400 kHz
400 kHz
A
ADC D
DRV C

H
Vout2 rslt0 W Ch1
400 kHz
 Software Block Execution
(400 kHz)

SStartSeq
Context Save
Comms
ADC_DRV(1)

CNTL_2P2Z(1) Loop-1

BUCK_DRV(1)

ISR body
ADC_DRV(2)

CNTL_2P2Z(2) Loop-2
Other....
BUCK_DRV(2)

Context
Restore
Driving the Power Stage with PWM Waveforms

• Open-Loop System Block Diagram

• Generating PWM using the ePWM Module
• Power Stage Topologies and Software Library
Support
 Simple Open-Loop Diagram
Single Power Stage
E
HR P Vin1 Vout1
BUCK W
Watch Window DRV M

H
Duty1 Duty1 In W EPWMnA DRV Buck

Duty2
ADC A
D
Duty3 1CH
C
DRV
Duty1
H
slider Vfdbk Vout1 Rslt W Ch0
 Scaleable PWM Peripherals
xSYNCI

SYNCI

EPWM1INTn EPWM1AO  Resources allocated on a per channel basis

EPWM1
EPWM1SOC
Module EPWM1BO  Each channel (module) supports 2
SYNCO independent PWM outputs (A&B)
xSYNCO

SYNCI  # Channels easily scaleable – software reuse

EPWM2INTn
EPWM2
EPWM2AO
 Time-base synch feature for all channels
PIE EPWM2SOC
Module GPIO
EPWM2BO
Mux  6 modules (12 PWM outputs) on F2808
SYNCO
 Key features:
Phase & edge control
SYNCI
New counting modes
EPWM6INTn EPWM6AO Independent deadband
EPWM6SOC EPWM6
Module EPWM6BO
Flexible trip-zones
TZ1n to TZ6n
SOC SYNCO High frequency chopper mode
xSOC

VBus32
ADC
to ECAP1 module (sync in)
 ePWM Module Block Diagram
Time-Base (TB)
Sync
TBPRD Shadow (16) CTR=ZERO In/Out
Select EPWMxSYNCO
TBPRD Active (16) CTR=CMPB Mux

Disabled
S0 S1
CTR=PRD

TBCTL[SYNCOSEL]
16
EPWMxSYNCI
Counter TBCTL[SWFSYNC]
UP / DWN TBCTL[CNTLDE] (software forced sync)

(16 bit)

TBCNT CTR=ZERO
Active (16) CTR_Dir

16

Phase
TBPHS Active (16) CTR=PRD
Control
EPWMxINTn
CTR=ZERO
Event
Trigger &
CTR=CMPA EPWMxSOCA
Interrupt
(ET)
Counter Compare (CC) CTR=CMPB
EPWMxSOCB
CTR_Dir

16 CTR=CMPA

Action
Qualifier
16 (AQ)

CMPA Active (16)

EPWMA EPWMxAO

CMPA Shadow (16) Trip

Dead PWM
Band Chopper Zone
(DB) (PC) (TZ)
16 CTR=CMPB
EPWMB EPWMxBO
16

CMPB Active (16) EPWMxTZINTn

CMPB Shadow (16) TZ1n to TZ6n

CTR=ZERO
 Module Sync and Phase Control
TBCTR
FFFFh
Master Module
Ext Sync In
(optional)
Master 600 600
TBPRD
Phase Reg En SyncIn

EPWM1A
CNT=Zero
CNT=CMPB EPWM1B 0000
1 X
SyncOut CTR=Zero
(SycnOut)
time
TBCTR
FFFFh 
Phase = 120o
Slave Module
Slave 600 600
TBPRD
Phase Reg En SyncIn
1 EPWM2A 200 200
CNT=Zero TBPHS
CNT=CMPB EPWM2B
0000
2 X
SyncOut
SyncIn

time
 Action Qualifier Module (AQ)
Key Features TBCTR = Period

 Multi event driven waveform generator TBCTR = Zero Action EPWMA

 Events drive outputs A and B independently. TBCTR = Compare A

Qualifier
 Full control on waveform polarity Module
 Full transparency on waveform construction
TBCTR = Compare B (AQ) EPWMB

 S/W forcing events supported SW force

 All events can generate interrupts & ADC SOC

TBCTR Direction
Actions
Events
Nothing Clear Lo Set Hi Toggle

Zero Z Z Z Z
TBCTR
(ZRO) T
CMPA CA CA CA CA PRD
TBCTR Period
(CAu) T
(Up) CBu CBd
equals: CMPB CB CB CB CB CMPB
(CBu) T
CAu CAd
P P P P CMPA
Period
(PRD) T ZRO
CMPA CA CA CA CA Zero
TBCTR (CAd) T
(Down)
equals: CMPB CB CB CB CB
(CBd) T
SW SW SW SW
S/W force
T
Simple Waveform Construction
TBCTR
TBPRD
value

Z P CB CA Z P CB CA Z P

EPWMA

Z P CB CA Z P CB CA Z P

EPWMB

TBCTR
TBPRD
value

CA CB CA CB

EPWMA

Z Z Z
T T T

EPWMB
 Fault Management Support
Vin Vout1
‘2808

EPWM1A Iin I1
EPWM2A
Iin EPWM1A Buck #1
HiZ

TZ1
ShutDown
I2
TZ2
CL2 Vout2

TZ3
CL1 I1
IsetCL1
Action on
Fault
I2
EPWM1B EPWM2A Buck #2
IsetCL2 HiZ
EPWM2B
IsetSD
ECAP1

IsetSD

Iin

Trip Zones: I1 IsetCL1

6 independent zones (TZ1~TZ6) I2
IsetCL2
Force High, Low or HiZ on trip
One-time trip  catastrophic failure
Cycle-by-cycle  current limit mode EPWM1A

TZ1~TZ6 can trigger interrupt

EPWM2A
 Multi-Phase Interleaved (MPI)
Ext Sync In
(optional)
Master
Phase Reg En SyncIn

EPWM1A
CNT=Zero
CNT=CMPB EPWM1B Vin
1 X
SyncOut

EPWM1A EPWM2A EPWM3A

Slave
Phase Reg En SyncIn
1 EPWM2A
CNT=Zero
CNT=CMPB EPWM2B

2 X Vout
SyncOut

EPWM1B EPWM2B EPWM3B

Slave
Phase Reg En SyncIn

EPWM3A
CNT=Zero
CNT=CMPB EPWM3B

3 X
SyncOut
 Switching Requirements – MPI
P P P
I I I

• Asymmetrical PWM case

• Complementary output
generated by dead-band unit
P CA CB
A
P CA P
• CMPB triggers ADC SOC
Pulse Center
EPWM1A INIT-time
1
• Period (1,2,3)
• CAu Action (1,2,3)
• PRD Action (1,2,3)
P CA CB
A
P CA
• Phase (2,3)
• PRD Interrupt (1)
EPWM2A
• CBu ADC SOC (1,2,3)

• Dead-band
RUN-time
CB

CA P CA
A
P • CMPA (1,2,3)
• CMPB (1,2,3)
EPWM3A
 Half H-Bridge (HHB)
VDC_bus VOUT

Ext Sync In
(optional)
Master
EPWM1A
Phase Reg En SyncIn

EPWM1A
CNT=Zero
CNT=CMPB EPWM1B

1 X
SyncOut

EPWM1B
 Switching Requirements – HHB
CMPA CMPA
modulation modulation • Up/Down Count
range range
• Asymmetrical PWM
• dead-band on A only
• 50 % max Modulation
CA CB Z CA Z (controlled by CMPA)
A
EPWM1B INIT-time
• ZRO Action (A,B)
Z CB CA Z CA • CAd Action
A • CAu Action
EPWM1A DBRED DBRED
• CBd ADC trigger
• CBd ADC trigger
• DBRED
Compare A modulation range:
0 < CMPA < ( PRD – ½ x DBRED ) RUN-time
• CMPA
• CMPB (optional)
 Phase Shifted Full Bridge (PSFB)
Ext Sync In

Master
(optional)
VDC_bus VOUT
Phase Reg En SyncIn
 
EPWM1A
CNT=Zero
CNT=CMPB EPWM1B
EPWM1A EPWM2A
1 X
SyncOut

Slave
Phase Reg En SyncIn
Var EPWM2A
CNT=Zero
CNT=CMPB EPWM2B
EPWM1B EPWM2B
2 X
SyncOut
 Switching Requirements – PSFB
Z
I
Z
I
Z
I
• Asymmetrical PWM
• Using dead-band module
• Phase (Φ) is the control variable
• Duty fixed at ~ 50%
Z CB CA Z CB CA Z
• RED / FED control ZVS trans.
A A i.e. via resonance
EPWM1A RED
• CMPB can trigger ADC SOC
ZVS
transition

EPWM1B
Power
Phase
FED INIT-time
ZVS
transition
• Period (1,2)
variable
• CMPA (1,2) ~ 50%
• CAu action (1,2)
• ZRO action (1,2)
Z CB CA
A
Z CB CA
A
Z
• CBu trigger for ADC SOC

EPWM2A RED
RUN-time
• Phase (2) – every cycle
EPWM2B
Power
Phase FED
• FED / RED (1,2) – slow loop
 Software Driver Module – PSFB
50% duty

PSFB E
EPWM1A
DRV P
W EPWM1B
M
Net1 phase EPWM1A llegdb
EPWM2A Left leg
H dead-band
Net2 llegdb
W EPWM2B
EPWM1B Power
Net3 rlegdb Phase
llegdb

phase
VDC_bus VOUT

EPWM1A EPWM2A

EPWM2A rlegdb
right leg
dead-band
Power
EPWM2B Phase
EPWM1B EPWM2B rlegdb

“Left leg” “Right leg”

 Software Driver Module – PFC2PHIL
PFC E
2PHIL P EPWM1A
DRV W
M
Net1 Duty
H EPWM1B
Net2 Adj W

EPWM1A +/-
Adj

VDC_bus

+/-
EPWM1B Adj

EPWM1A EPWM1B
1