Simplify and Optimize Your Design with Logic and

Level Shifters

Standard Logic and Translation

Shreyas Rao
Detroit 2018

1
 Agenda: Simplify and Optimize Your Design with Logic and Level Shifters

• Overview of Standard Logic Portfolio

• Understanding CMOS circuits
• Common Applications Questions
• Simple system solutions
• Use Cases for Logic and Level Translators
• Building Blocks examples
• Open Forum for QA/Feedback/Suggestions

TI Information-Selective Disclosure
 Standard Logic – Overview
Gates Transceivers
Voltage Translation Buffers Multi-gates FFLR Specialty Logic Encoders
Decoders

Product families Product families Product families Product families Product families
• Direction controlled • Gates • Multi-gates*, • Configurable, Combo Logic • Transceivers
• Auto direction • Buffers • Buffers, • Logic comparators, Counters • Encoders
• Application specific • Drivers • Flip flop & Laches • Monostable multivibrators • Decoders
• Translating gates • Shift registers • Misc (Terminators, Adders, Timers)
Sectors/EEs Sectors/EEs Sectors/EEs Sectors/EEs Sectors/EEs
• HEV/EV • Infotainment • Sensor Fusion • Infotainment • Body Electronics
• ADAS • Power Train • Surround sound • ADAS • Cluster
• Infotainment • Server • Industrial Automation • Factory Auto, Server • Building Automation
• Motor Drive • Building Automation • Test and Measurement • Test & Meas, Motor • Servers, Grid
Drive
Popular Devices Popular Devices Popular Devices Popular Devices Popular Devices
• SN74AXC8T245 • SN74LVC1G17-Q1 • SN74LV125A-Q1 • SN74HC193-Q1 • SN74AHC245-Q1
8 bit, 0.65V-3.6V Translator 1-bit Schmitt Trigger Buffer 4-bit Buffer with Enable 4-Bit Synchronous Counter 8-bit Bus Transceiver w/Enable

• LSF0204-Q1 • SN74AUP1G08 • SN74HC21-Q1 • SN74LV123A-Q1 • SN74HC253

4-bit, 0.9V- 5.5V Translator Low Power Single AND Gate Dual 4-Input AND Gate Retriggerable One-shot Dual 4 to 1 Encoder w/Enable

• TXS0104E-Q1 • SN74LVC1G00-Q1 • SN74AHC595-Q1 • SN74HC4060-Q1 • SN74HC138-Q1

4-bit bidirectional
TI Information-Selective translator
Disclosure Single channel NAND gate 8-bit Shift Register w/enable Oscillator + 14-bit Counter Single 3 to 8 Decoder/Demux
 CMOS Input Characteristics
VO
VCC MP ON
Shoot-through Current MN ON
VCC

MN OFF

MP OFF
MP ON

MN ON
V IL
MP
VCC Vt
2

MN
V IH
0 VI

0 V CC/ 2 V CC

ICC
MP ON
MN ON

MN OFF

MP OFF
MN ON
MP ON
ΔICC VI
0 VCC/2 VCC

TI Information-Selective Disclosure
 Logic Use Case: Combining Power Good Signals
Power Good with AND Gate Power Good Options Signal Enable using AND Gate

Tx Signal 1

Active High
DC-DC AND
Active High
DC-DC Power Good
Processor Power Good NAND Processor
DC-DC Active low
AND Enable Enable
DC-DC Active High
Tx Signal 2
Enable
AND
What problem it solves? Enable

• Identifying power good status of the

system, where multiple DC-DCs are used.
What problem it solves? What problem it solves?
• Identifying power good status of the • AND gates can be used to gate signals.
system, where multiple DC-DCs are used.
Power Good Enable The second inputs can be used to force the
Gates
AND is used when the output of the DC- Input Signal output low or allow a signal to be
DC is active high as well as the enable transmitted.
input of the processor is active high NOR Active Low Active High

NAND Active High Active Low

Popular Products Popular Products
• SN74LVC1G08 | SN74HC21A-Q1 AND Active High Active High • SN74LVC2G08 | SN74ALVC08A-Q1

OR Active Low Active Low

TI Information-Selective Disclosure
 Logic Use Case: Aggregating Error Signals

Enable a Switch Enable upon Error Reset MCU upon Error using OR Activate Buzzer Upon Error using OR

Low
Voltage
Error
MCU Power
Switch MCU
Error Error
Sensor AND Speaker
OR Reset OR
AND
OR OE
DC-DC Error Voltage MCU Error

Regulator Thermal
Error

What problem it solves? What problem it solves? What problem it solves?

• Combining error signals to enable a • Activates MCU reset when an error • Combining error signals to turn on a
switch. occurs. buzzer.

Popular Products Popular Products Popular Products

• SN74AHC1G32 | SN74LVC32A-Q1 • SN74AHC1G32 | SN74LVC32A-Q1 • SN74AHC1G32-Q1 | SN74LVC1G32

TI Information-Selective Disclosure
 Logic Use Case: XOR Gate
Phase Comparator using XOR Single Ended to Differential signal

Phase Locked Loop/Clock Alignment

Vcc

PWM
X(t) PWM
VCO
PWM

What problem it solves? What problem it solves?

Commonly used in communications, Dual XOR gate can be used to convert
an XOR gate can be used to convert the single ended signal to differential
the phase difference to a PWM signal. signal with low skew.

Popular Products Popular Products

SN74LVC1G86 | SN74AUC1G86 SN74LVC2G86 | SN74AUC2G86

10
TI Information-Selective Disclosure
 What happens if VI > VCC?
2.5V VCC

5V Input
AND 2.5V Output
3.3V Input

* Positive sign indicates sinking current, negative current indicates sourcing current.

TI Information-Selective Disclosure
 Partial Power Down
VCC VCC
Bias VCC L3 – Live Insertion
Power-Up 3-State L2 – Hot Insertion
IOFF L1 – Partial Power Down
Electrical Isolation
• Allows voltage on Input/output when VCC = 0
• Prevents unexpected device behavior during power-up or power- 0V
down
• Prevents signals from sourcing current through parasitic diodes 5V Input
• IOFF spec is required for partial power down operations AND
• Explanation of IOFF and the three levels of electrical protection 3.3V Input

Families Supporting Partial Power Down (Ioff )

ABT, ALVT, AVC, AUC, AUP, GTL, GTLP, LV-A, LVC, LVT, VME
12
TI Information-Selective Disclosure
 What do I do with unused inputs?
VO
MP ON
MN ON
VCC

MN OFF

MP OFF
MP ON

MN ON
V IL

VCC Vt
2

V IH
0 VI

0 V CC/ 2 V CC

ICC
MP ON
MN ON

MN OFF

MP OFF
MN ON
MP ON
ΔICC VI
0 VCC/2 VCC

TI Information-Selective Disclosure
 Bus Hold
Problem
Floating logic inputs tend to drift to the logic
threshold region and cause excessive current draw
from VCC, in addition to oscillation.

Solution

Bus-hold circuitry pulls the logic input to its last known state.

Value

Pullup and pulldown resistors are no longer required or

recommended. Inputs will not float to unstable levels.

14
TI Information-Selective Disclosure
 Unused Inputs – What do I do

Utilizing NAND/NOR as Inverting Buffer Utilizing OR/AND as a Buffer

.
DC-DC Active High Shift Register1

DC-DC Active Low Shift Register2

.

What problem it solves? What problem it solves?

• Utilizing a NAND gate as an inverter • Utilizing an OR gate as a buffer when
when spare gates are available in multi spare gates are available in multi input
input gates. In this case, the desired gates. In this case the buffer is being
signal needs to be inverted for further used as a delay between the shift
comparison. registers.

Popular Products Popular Products

• SN74AHC1G00-Q1 | SN74AHC00-Q1 • SN74AHC1G32-Q1 | SN74LVC32A-Q1

TI Information-Selective Disclosure
 What happens when the inputs has slow rise time?

Bad Circuits

Oscillations

Slow Rising Edge input results in output oscillations

(Inverter)

VCC

Excessive
ICC
Current
+
½ VCC
–

TI Information-Selective Disclosure
 Schmitt-Trigger Overview
VO

VCC

VCC

VI
VCC/2
0
VT- VT+ VCC
VI VO
VCC

TI Information-Selective Disclosure
 Logic Use Case: Correcting Slow, Noisy Inputs

Increase Edge Rate w/Schmitt Trigger Mechanical Push Button Debounce

5V

Oscillator MCU MCU

Push
Button

What problem it solves? What problem it solves?

• Creates a sharp rising edge for slow • Creates a single sharp pulse instead of a
rising or noisy input signals to eliminate series of pulses which could trigger the
on/off timing discrepancy. output multiple times on a single button
press.

Popular Products Popular Products

• SN74LVC1G17-Q1 | SN74LVC2G17 • SN74LVC14A | SN74LVC2G17-Q1

TI Information-Selective Disclosure
 Logic use case: Adding a time delay
Time Delay using Schmitt Trigger Rising Edge Time Delay Falling Edge Time Delay
using Schmitt Trigger Buffer using Schmitt Trigger Buffer

What problem it solves? What problem it solves? What problem it solves?

• The RC circuit creates a time delay that • The shown diode added to the RC circuit • The shown diode added to the RC circuit
can be specified by the user that is then will allow falling edges to bypass the will allow rising edges to bypass the
fed into the buffer, returning the pulse of delay delay
the delay at the output.

Popular Products Popular Products Popular Products

• SN74LVC1G17-Q1 | SN74LVC2G17 • SN74LVC1G17-Q1 | SN74LVC3G17 • SN74LVC1G17-Q1 | SN74LVC2G14

TI Information-Selective Disclosure
 Do we have gates with Schmitt-trigger inputs?
SN74LVC1G97-Q1
Configurable Gate

AND NOR

SN74AUP1G99 SN74LVC1G97-Q1
2-to-1 Data Selector 2-Input AND Gate

TI Information-Selective Disclosure
 CMOS Output Characteristics
VCC

rON

rON

IOL

ISC
Nearly Constant

Max FET Current @ VCC

Resistance

n ce
ta
si s
t Re
an
st
C on
e al
Id
VOL
0

VOL (max)
VOL (typ)
VCC/2 VCC

TI Information-Selective Disclosure
 Logic use case: Increasing drive strength

Peripheral driver requiring higher current Parallel Outputs for High Current Drive

32mA 64mA
Buffer

Indicator
Processor Buffer
LED
32mA
Buffer

What problem it solves? What problem it solves?

• Used to increase drive strength between • When putting two components in
the processor and a peripheral devices. parallel their current will add, thus
(ex. LED) increasing the current drive.

Popular Products
Popular Products
• SN74LVC125A-Q1
• SN74LVC1G07 (Open Drain)
SN74LV125A-Q1 *Timing issues can occur if done with buffers from
different packages

TI Information-Selective Disclosure
 Logic use case: Improving signal quality
Unidirectional Switch using 3-State Bidirectional communication using
Buffer for long traces Fan Out using Octal Buffer Buffer Transceiver
Ribbon
Cable
Octal Octal or
Back Plane
Buffer Buffer

Processor
CPU Driver LED
LED
LED
Processor1 Buffer Processor2 Octal Octal
En Bus Bus Slave
MCU Transceiver Transceiver
Device
Tx Buffer Controlled
Signal output
Driver LED
LED
LED

What problem it solves? What problem it solves? What problem it solves? What problem it solves?
• Used to drive high capacitance • Increases current drive from CPU • Allows for signal to pass when • Allows for bidirectional
lines or long traces. to multiple peripherals enabled. communication between a master
• Distribute load capacitance and slave device while keeping
signal integrity.

Popular Products Popular Products Popular Products Popular Products

• SN74LVC1G17 | SN74LV125A- • SN74AHC244A | SN74LVC244A- • SN74LVC1G125-Q1 | • SN74AHC245-Q1
Q1 Q1 SN74AUP1G125

TI Information-Selective Disclosure
 Open-Drain devices- Isolation and translation
Up/Down Translation using Open Voltage Source Separation Wired-AND/OR logic using Open
Drain Buffer using Open Drain Buffer Drain buffer
Vx=3.3V
VS2=3.3V from system
VS1=3.3V VS1=3.3V from Battery
rail

MCU

FPGA 1.8V MCU FPGA 1.8V

Controller MCU

What problem it solves? What problem it solves? What problem it solves?

• Utilized as flexible voltage translation • Used to separate two voltage • One chip solution to integrate Logic-
from a processor to an external domains AND function & signal translation
peripheral using OD buffer (also termed as
Wired-AND)

Popular Products Popular Products Popular Products

• SN74LVC1G07 | SN74LVC07A-Q1 • SN74LVC1G07-Q1 | SN74LVC07A • SN74LVC1G07 | SN74LVC07A

TI Information-Selective Disclosure
CMOS power consumption
Total Power Consumption 1
VCC
PTOTAL = PS + PT + PLC + PLR
2

• Static Power Consumption (PS)

3

PS = VCC ICC(max)
4
• Resistive Load Power Consumption (PLR)
PLR = sum[ Dn ( VCC – VOHn ) ( VOHn / RLn) ]
• Dynamic Power Consumption
• Transient Power Consumption (PT) VCC := supply voltage
ICC(max) := max static supply current (from datasheet)
2
PT = Cpd VCC fI NSW Cpd := dynamic power-dissipation capacitance (from
datasheet)
fI := input frequency
• Capacitive Load Power Consumption (PLC) NSW := number of inputs switching
CLn := Load capacitance at each output, 1 through n
PLC = sum[ CLn fOn ] VCC 2
fOn := Output frequency at each output, 1 through n
Dn := Duty cycle of output
TI Information-Selective Disclosure VOHn := Output high voltage @ load current (from datasheet)
 Understanding Thermal Values

ΔT = PTOTAL RθJA
Example
LVC244A ΔT = 100mW * 177.4 °C/W
Max
Current
ΔT = 17.7°C
@ 2V If operating at 125°C, the junction would increase to
125+17.7 = 142.7°C
* The majority of logic device will never hit the maximum junction temperature if
operated within the datasheet limits. RθJA is the most commonly required
thermal value

LVC244A
Max
Current
@ 3.6V

TI Information-Selective Disclosure
 Logic Use Case: Output expansion with limited I/Os

MCU to Multiple Indicator LED’s Driving Stepper Motor w/Shift Register 7-Segment Display using Shift Register
using a Shift Register

Indicator
LED
Stepper
MCU Shift Motor MCU
Shift
Processor Shift Indicator Register Driver Register
LED
Register Stepper
Clk Clk
Indicator Motor
Clk LED

Indicator
LED

What problem it solves? What problem it solves? What problem it solves?

• Used to expand the MCU’s number of • Used to expand the MCU’s number of • Used to expand the MCU’s number of
outputs for individual LED control outputs for stepper motor control outputs for 7 segment displays

Popular Products Popular Products Popular Products

• SN74AHC595-Q1 | SN74HC595 • CD4021B-Q1 | SN74HC595 • SN74AHC595-Q1 | CD4021B

TI Information-Selective Disclosure
 TI Design: Ultra-Small, Flexible LED Expansion

RCLK
Shift
QA-H LED

SRCLK
Register Matrix
Design Challenges SN74HC595B
8x8

SER
Building a design that can drive an LED
Matrix or 7-segment display in a space- Yn
constrained environment and a limited RCLK QH’

RCLK
number of outputs Shift Buffer
SRCLK QA-H 8

SRCLK
Register Driver
SER SN74HC595B SN74LVC244A

SER
Solution / Value
• Subsystem Adaptable to a Wide Range of Space-
BOOSTXL-SHIFTLED
Constrained Applications 7-Segment and 8x8 LED Matrix BoosterPack

• Only Three GPIO Pins Required to Drive Any

Multiple of Eight Channels Blog: The next-generation
QFN: Do you have what it
• X1QFN smallest available logic packaging for high takes to use it?
pin count devices
TIDA-01233
• Total Solution size fits within the board area of a
single 7 segment display

33
TI Information-Selective Disclosure
 Logic Use Case: Clock division and Flip-Flop
Buck converter control using SR Flip
Clock Division using D-Flip Flop Multiple Clock Divisions using counter
Flop

5 kHz

D Flip 0 0 0 0

Flop Counter 0 0 1 1
10 kHz
Clk Clk 0 1 0 1

What problem it solves? What problem it solves? What problem it solves?

• Used when a user wants to decrease • Utilized when a 2n clock division is • Synchronous buck controller using SR
clock frequency required flip flop
• For example, a 4 bit counter can do a • Controlled timing of Pass FET and
16x clock division reverse current FET

Popular Products Popular Products Popular Products

• SN74LVC1G374 | SN74AHC74Q-Q1 • SN74HC163-Q1 | SN74HC193 • SN74AUP1G74 | SN74LVC2G74

TI Information-Selective Disclosure
Translation by Interface: Serial Peripheral Interface (SPI)

Does your system have a SPI interface to

a peripheral such as: VCCA VCCB

Bluetooth Low Energy Module

GPS Module Key Careabouts:
WiFi Module SCLK SCLK Push-Pull Architecture
Sensors (Image, Temp, Pressure, etc.) 4 Individual Channel
Accelerometer Direction Control Recommendation:
TXB0104-Q1
MOSI MOSI Low Current
Memory SN74AXC4T774-Q1*
Consumption
Drone GPS
Why: Simultaneous Individually SoC Module Bit Count  3 or 4
Addressable Communication between MISO MISO
central processor and peripheral Data Rate  200 Mbps
Voltage  1.8 to 3.3V

SS SS
Direction Controlled Translation Use-Cases
Audio Encoding with Inter-IC Sound (I2S) or Pulse-Code Modulation (PCM)

VCCA VCCB VCCA VCCB

Does your system have an audio codec Key Careabouts:

MCLK MCLK
ADC or DAC communicating over I2S or WCLK WCLK

PCM with a CPU or DSP? Push-Pull Architecture

WCLK WCLK
Codec BCLK BCLK Codec 2 by 2 Channel Recommendation:
DSP or
Why: Bidirectional Support and Signal or DAC
DSP
or
or
DAC Direction Control SN74AVC4T245-Q1
CPU or
Redriving with Translation BCLK BCLK
ADC
CPU or SN74AXC4T245-Q1
Bit Count  3 to 4
SD SD ADC

SD SD Data Rate  48 Mbps

Master Slave
Voltage  1.8 to 3.3V
Slave Master

VCCA VCCB
Key Careabouts:
Does your I2S or PCM signaling require
individual channel control? Push-Pull Architecture
WCLK WCLK

4 Individual Channel
Why: Bidirectional Support with individual Direction Control Recommendation:
BCLK BCLK
channel control DSP
Codec
or
TXB0104-Q1
or DAC Bit Count  4 SN74AXC4T774-Q1
CPU or
Data Rate  48 Mbps
DIN DIN ADC

DOUT DOUT
Voltage  1.8 to 3.3V

Stage 1 Stage 2 Stage 3 Stage 4 Stage 5

Direction Controlled Translation Use-Cases
Peripheral Interface with Universal Asynchronous Receiver-Transmitter (UART)

Does your system have a UART interface

VCCA VCCB
to a peripheral such as:
Bluetooth Low Energy Module
GPS Module Key Careabouts:
Sensors (Image, Temp, Pressure, etc.) RXD RXD
Push-Pull Architecture
Memory 2 by 2 Channel
Secondary Microcontroller Direction Control Recommendation:
CTS CTS SN74AVC4T245
USB to UART Bridge Low Current SN74AXC4T245-Q1
Switch/
Consumption
Router BLE
Why: Simultaneous Bidirectional ASIC Module Bit Count  4
Communication between central Chipset TXD TXD
Data Rate  20 Mbps
processor and peripheral
Voltage  1.8 to 3.3V

RTS RTS

Stage 1 Stage 2 Stage 3 Stage 4 Stage 5

Direction Controlled Translation Use-Cases
Programming and Debug with JTAG

VCCA VCCB

Does your system utilize JTAG to Key Careabouts:

provide in-system programming or TMS TMS

debug? Push-Pull Architecture

TCK TCK 4 Individual Channel Recommendation:
Why: Simultaneous Individually SN74AVC4T774
JTAG Direction Control
Addressable Communication with Debugger
FPGA
SN74AXC4T774-Q1
Translation TDI TDI Bit Count  4
Data Rate  200 Mbps
TDO TDO

Voltage  1.8 to 3.3V

Key Careabouts:
Does your debug port run on a reduced VCCA VCCB
pin count JTAG with only 2 pins? Push-Pull Architecture
2 Bit Unidirectional
Why: Unidirectional Translation and TMSC TMSC Recommendation:
Bit Count  2 SN74AVC2T45
Redriving
SN74AXC1T45
JTAG
Programmer
MCU Data Rate  200 Mbps
Voltage  1.8 to 3.3V
TCK TCK

Stage 1 Stage 2 Stage 3 Stage 4 Stage 5

 Unidirectional translation: 2N7001T

Discrete FET replacement LED driving using Unidirectional level

with Unidirectional level shifter shifter
VCCB

R1 Q2 C1 1.8V 2N7001T
Vout(VCCB)
1.8V Q1 Q3

3.3V

1.8V 2N7001T
1.8V 2N7001T 3.3V

What problem it solves? What problem it solves?

• Replace discrete FETs using TI’s • Drive a LED indicator using
unidirectional translation gates unidirectional translation

Popular Products Popular Products

• 2N7001T-Q1 | SN74AUP1T34-Q1 • 2N7001T-Q1 | SN74AUP1T34-Q1 |
SN74LV1T34

TI Information-Selective Disclosure
 Block Diagram: ADAS Domain Controller

SPI Interface
with Level Translator
Power Good Status Flag to uP

Processor Reset upon Thermal Error or SPI

1.8V
System Reset Input Translator

Processor MCU
Translator
Active High
Power Good
DC-DC Processor
Temp AND Enable
Error Processor
Sensor DC-DC Active High
Reset What problem it solves? Enable
OR
System Input • Communication channel interfaces such as SPI/
Reset UART require a translator to account for the
different operating voltages.
What problem it solves?
• Identifies power good status of the system,
where
Popular multiple DC-DCs are used. Low cost
Products
What problem it solves? method of system
• TXB0104-Q1 power good|implementation
| SN74AVC4T774
• Activates a reset when thermal sensor error instead of using processor GPIOs for individual
SN74AXC8T245-Q1
occurs or system reset input sent to processor power good signals.

Popular Products
Popular Products
• SN74LVC1G08-Q1 | SN74HC21A-Q1
• SN74AHC1G32-Q1 | SN74LVC32A-Q1
Block Diagram: Automotive Head Unit
Communication through I2C / I2S Channel Power Good Status Flag to uP
Configuration
with LevelTypical # sockets PWR Good to MCU
Translator Voltage Conditioning Module AND
Pre Gate
Integrated Head Unit 4-5 Boost
5V @ 100ma PWR Good
5V @ ~500ma
Reverse
Battery Wide VIN
Entry Level AM/FM Tuner Module Protection Buck

PWR Good
CMOS
Processor LVI2C Translator
LV Sensor I2S Level
SPI Interface
3.3V
LDO
LDO Translator
MCU
Active High
with Level Translator
Audio
Communication
Power Good through SDIO (SD card)
Vbat_RBP LV

AMP
AM/FM
DSP DC-DC Processor DC/DC
Tuner DAC
Audio Channel and Processor with
Processor I2S Translator AND Enable
DSP Level Translator
DC-DC Active High
Processor Reset upon Thermal Error or
5V @ ~100ma Enable Enhance SPIDrive Strength using Buffer
Signal
1.8V
3.3V Translator
System Reset Input3.3V
Processor GPS

AMP

Audio
AMP
LV LDO BT + DSP 4/5 Speakers
Analog Mux SDIO 80 – 125W
Translator
What problem it solves?
What problem it solves? • Identifies power good status
Processor of the system,
Translator SDIO
• Translates I2C / I2S communication signals
Wireless Connectivity Module where multiple DC-DCs are used. Low cost
between processor and peripherals (Audio method of system power good implementation Graphics HMI
Temp sensor)
Error which are Processor Vbat_RBP

AMP
DSP / CMOS 5Vat different
@ ~100ma IO instead of using 3.3V Audio Line Out
processor GPIOs for individual
Sensor
voltage levels (3.3V to 1.8V). What problem it solves?
Processor Buffer Indicator
OR Reset Optical Drive power good signals. LCD LED
Popular Products Input 5V • CommunicationBias channel interfaces such as SPI/
LED Backlight
System Supply Driver
• TXB0104-Q1 UART require a translator to account for the
AMP

Reset| TXS0102-Q1 | LSF0102-Q1

LV LDO Drive ASIC Popular Products

ESD
CAN
different
CAN operating voltages.Temp
• SN74LVC1G08-Q1
What problem it | SN74HC21A-Q1
solves? Gamma
Sensor Buffer
• Translates SDIO communication signals
Pushbuttons/Knobs

ESD
Temp between processor and SD card which are at
Media Interface Sensor I2C/SPI Popular Products
differentGraphics
IO voltage levels (3.3V to 1.8V)
ESD

AMP

Audio Line In
• What

ESD
What problem it solves? MCU/MPU
Level
Translator
Touch Screen
Controller
TXB0104-Q1
problem it| SN74AVC4T774
solves? |
• Activates a reset when thermal sensor error Level SDIO • SN74AXC8T245
Used to increase drive strength between the
Popular Products
ESD

SD
Card Translator
occurs or system reset input sent to processor Temp Sensor processor and indicator LED

Array
• TWL1200-Q1| SN74AVCA406E

Filter
18b/24b RGB
ERROR
OR
5V @ 100ma System Reset Gate
RESET

Popular Products
ESD

Popular Products
USB 2.x USB Switch
Buffer / Driver LED Indicator
• SN74AHC1G32-Q1 | SN74LVC32A-Q1 USB • SN74LVC1G125-Q1
SN74AHCT1G125-Q1
48
Selecting the Right Voltage Level Translator for
Common Interfaces

49
 Quick Select for Translation Devices
Select by Interface Select by Translation and Supply Configuration
Interface 2 Ch 4 Ch 6Ch 8 Ch Configuration Supply 1 Ch 2 Ch 4 Ch 8 Ch

AVC4T774
SPI --
TXB0104
-- AXC8T245
1.65 – 5.5V TXS0101 TXS0102 TXS0104E
TXS0108E
(1.2 – 5.5V)

UART --
AVC4T774
-- AXC8T245 Auto Bidirectional
TXB0104
(Dual Supply) 1.2 – 5.5V TXB0101 TXB0102 TXB0104 TXB0108
AVC4T774
JTAG --
TXB0104
-- AXC8T245
0.95 – 5.5V LSF0101 LSF0102 LSF0204 LSF0108
TXB0104
I2S --
AVC4T245
-- AXC8T245
0.65-3.6 AXC1T45   AXC8T245

TXS0102 TXS0104E TXS0108E Direction Controlled

I2C LSF0102 LSF0204
--
LSF0108 1.2-3.6 AXC1T45 AVC2T45 AVC4T245 AXC8T245
(Dual Supply)
TXS0102 TXS0104E TXS0108E
MDIO LSF0102 LSF0204
--
LSF0108 1.65-5.5 LVC1T45 LVC2T45  LVC8T245

TXS0102 TXS0104E TXS0108E

SMBus LSF0102 LSF0204
--
LSF0108
Single 1.65 -5.5V LV1T125  LV4T125 --
Supply
RMII/RGMII -- -- TXB0106 AXC8T245
Unidirection
Dual 0.65 – 3.6V AXC1T45
AVC2T244 AVC4T234
AXC8T245
Supply (0.9 - 3.6V) (0.9 - 3.6)
Quad-SPI -- -- TXB0106 TXB0108

TXS0206 SN74AUP1T
SDIO -- -- -- 2.3-3.6 -- -- --
TXS0206-29 Family
Translating Gates
AVC2T872 AND, OR, NOR…
IC-USB --
TXS0202
-- --
(Single Supply) SN74LV1T
1.65-5.5 -- LV4T125 --
TXS0206 Family
SD/MMC -- --
TXS0206-29
--
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Auto-Bidirectional Translators
Metrics TXB TXS LSF

Drive strength Very low drive of 20ua Passive translation with Passive translation with NMOS; no
due to 4K buffer NMOS; no drive drive

Applications/ Interface Mostly suitable for push- Suitable for open drain Push pull and open drain
pull applications applications applications

Speed Up to 140Mbps Up to 24Mbps High speed up to 200Mbps

Translation flexibility Buffered; Fixed Integrated 10k resistors- Flexible translation due to external
translation reduces BOM cost of the resistors
system; but inflexible
Frequency vs load balance trade-
off

I/O ports Referenced to Vcca or Referenced to Vcca or Vccb Multi-voltage translation in single
Vccb device

Edge- acceleration Integrated one-shot Integrated one-shot No integrated one-shot

Vih/Vil requirements Datasheet spec has D/S has Vih /Vil spec, no Ron No Vih / Vil conditions, has Ron
Vih/Vil for the FET spec

Additional care-about Vcc<=Vccb Vcca<=Vccb Vccb>Vcca+0.8

51
Voltage level translator product portfolio

Unidirectional Direction controlled Auto-Direction Translation + Logic Gates

sensing

VCCA VCCB VCCA VCCB VCCA VCCB VCCA VCCB VCC

A
A B A B
A B A B B Y
C
DIR
• 1-,2-,4-bit • 1-,2-,4-,6-, 8-, 16-, 24-,32-bit • 1-,2-,4-,6-,8-bit • 1-,4-bit
• Level translating • Level translating • Level translating • Level translating
• Push-pull IOs • High Speed (190Mhz) • High Speed 100Mhz • Perform Logic function + Translation
• Fast translation (190Mhz) • Push-pull Ios • Push-pull IOs, Open-drain IOs • Fast Operation (190Mhz)
• Low Power (1mA) • Low Power (60uA) • Most versatile solutions • Low Power (1mA)
Hero Parts Hero Parts Hero Parts Hero Parts
• 2N7001T • SN74LVC8T245 • TXS0102 • SN74LV1T00
• SN74AUP1T34 • SN74AXC8T245 • TXB0304 • SN74AUP1T08
• SN74AVC4T234 • SN74AXC1T45 • TXB0108 • SN74LV1T34
• SN74AVC2T244 • SN74AVC4T774 • LSF0108 • SN74AUP1T57
Specific application Specific application
• SPI, UART Specific application Specific application
• Sensor I/F • I2S • SD Card • Chipset logic
• LV chipset IO • IC-USB • SIM Card • Control logics for compute
• PC/Compute Control IO • JTAG • IC-USB • Control logic for comms
• RGMII

53
Backup: Logic Special Features
 Bus Hold
Problem
Floating logic inputs tend to drift to the logic
threshold region and cause excessive current draw
from VCC, in addition to oscillation.

Solution

Bus-hold circuitry pulls the logic input to its last known state.

Value

Pullup and pulldown resistors are no longer required or

recommended. Inputs will not float to unstable levels.

55
TI Information-Selective Disclosure
 Series Damping Resistors
Problem
Z0

Signal integrity issues due to noise on edges at output

Solution VCC
Series damping resistors slow edges and provide better
impedance matching and line termination

25Ω

Value

Eliminates the need for external series resistors

RLC current impulse response

https://en.wikipedia.org/wiki/RLC_circuit
56
TI Information-Selective Disclosure
 Partial Power Down
Bias VCC L3 – Live Insertion
Power-Up 3-State L2 – Hot Insertion
IOFF L1 – Partial Power Down
Electrical Isolation

• Allows voltage on output when VCC = 0

• Prevents unexpected device behavior during power-up or power-
down
• Prevents signals from sourcing current through parasitic diodes
• Allows for power down of partial circuits within a system
• IOFF spec is required for partial power down operations
• Explanation of IOFF and the three levels of electrical protection

Families Supporting Partial Power Down (Ioff )

ABT, ALVT, AVC, AUC, AUP, GTL, GTLP, LV-A, LVC, LVT, VME
57
TI Information-Selective Disclosure
 Hot Insertion
Example
Bias VCC L3 – Live Insertion
Circuit Implementation
Power-Up 3-State L2 – Hot Insertion
Supply PU3S Circuit
IOFF L1 – Partial Power Down Voltage
Electrical Isolation VCC

• Problem: Outputs sometimes “follow” VCC at low voltages Supply

as VCC ramps trip point
• Power-Up 3-State (PU3S) prevents this “following” until
VCC reaches a trip point. Output
• Prevents bus to be loaded down upon power-up Off (Z) On Off (Z)
• IOFF and PU3S specs required for hot insertion
• PU3S App Note

Families Supporting Hot Insertion (Ioff and Power-up 3-state)

ABT, ALVT, GTLP, LVCZ, LVT, VME

58
TI Information-Selective Disclosure
 Live Insertion Circuit Implementation
Bias VCC L3 – Live Insertion Pre-Charge Circuit
with pre-charge
Power-Up 3-State L2 – Hot Insertion with out pre-charge

IOFF L1 – Partial Power Down

BIAS VCC 
Electrical Isolation
VCC  Pre-Charge
• BIAS VCC Prevents unwanted glitches at the I/O Circuit
• IOFF, PU3S, and BIAS VCC required for Live Insertion I/O 
• Staggered pins require pre-charge functionality Output
• Live Insertion App Note Stage
GND 
  
Card Connector

Socket Pin
Families Supporting Live Insertion vcc I/O BIAS VGND
(Ioff, Power-up 3-state, and BIAS VCC) CC

ABTE, GTLP, FB, VME

59
TI Information-Selective Disclosure
 Logic Feature List †
 Bus Hold – ABT, ALVC, ALVT, AVC, AUC, FCT, GTL, GTLP, LVC, LVT, VME
– Bus-hold circuitry in selected logic families helps solve the problem of floating inputs and eliminates the need for pull-up or
pull-down resistors by holding the last known state of the input. See II(HOLD) or IBHL, IBHH, IBHLO, and IBHHO on data sheet. The
Bus Hold devices typically have an “H” in the part number
 Series Damping Resistors – ABT, ALVC, ALVT, F, GTLP, LVC, LVT, VME
– Series damping resistors limit signal overshoot and undershoot by providing better impedance matching and line termination
without the need for external resistors.
 Partial Power Down (Level 1 Isolation - Ioff) – ABT, ALVT, AVC, AUC, AUP, CBTLV, CBT-C, GTL, GTLP LV-A, LVC, LVT, VME
– IOFF circuitry prevents the device from being damaged during hot insertion. See IOFF specifications on data sheet.
 Hot Insertion (Level 2 Isolation – Ioff and Power-up 3-state) – ABT, ALVT, GTLP, LVCZ, LVT, VME
– Power-up 3-state ensures valid output levels during power up and valid Z on the outputs during power down. See IOZPU,
IOZPD.
 Live Insertion (Level 3 Isolation – Ioff, Power-up 3-state, and BIAS VCC) – GTLP, FB, CBT, CBTLV, VME
– Precharges I/O capacitance, preventing glitching of active data.
 Mixed-Voltage-Tolerant I/Os and Level Shifting – AVC, ALVC, ALVT, AUC, AUP, GTL, GTLP, LV-A, LVC, LVT
– Systems use mixed supply voltages and TLL or CMOS levels in many designs. Most advanced-logic families allow mixed-
signal interfacing and provide level-shifting functions for certain mixed-voltage applications.
 JTAG – ABT, ACT, BCT, LVT
(†selected functions)
60
TI Information-Selective Disclosure
TI Design: Automotive-Qualified 16-Bit Rotary Quadrature Decoder

Design Challenges Visit: ti.com/tidesigns

Creating a simple front-end digital decoder
for a quadrature encoder (rotary knob), Part number: TIDA-00580
while minimizing processing time from an
MCU Rotary decoder circuitry fits inside the red circle,
behind the rotary knob
Solution / Value
• I2C interface
• Works with any rotary quadrature encoder
• Overvoltage tolerant inputs allow for a
wide variety of input voltage ranges
• Voltage translation allows for 2-V to 5-V
logic outputs
• Open-drain interrupt output indicates to
the MCU when a change has occurred
• Low power standby operation
• Frees up MCU operating time

62
TI Information-Selective Disclosure