Data Science and Engineering (2018) 3:263–276

https://doi.org/10.1007/s41019-018-0072-6

The New Hardware Development Trend and the Challenges in Data

Management and Analysis
Wei Pan1 · Zhanhuai Li1 · Yansong Zhang2 · Chuliang Weng3

Received: 28 May 2018 / Accepted: 29 August 2018 / Published online: 24 September 2018
© The Author(s) 2018

Abstract
Hardware techniques and environments underwent significant transformations in the field of information technology, rep-
resented by high-performance processors and hardware accelerators characterized by abundant heterogeneous parallelism,
nonvolatile memory with hybrid storage hierarchies, and RDMA-enabled high-speed network. Recent hardware trends in
these areas deeply affect data management and analysis applications. In this paper, we first introduce the development trend
of the new hardware in computation, storage, and network dimensions. Then, the related research techniques which affect
the upper data management system design are reviewed. Finally, challenges and opportunities are addressed for the key
technologies of data management and analysis in new hardware environments.

Keywords  Data management · Data analysis · Heterogeneous hardware

1 Introduction and cost performance. Under the various application work-

loads, the traditional data management and analysis tech-
The development of data management and analysis systems niques are facing unprecedented challenges. Essentially, the
largely benefits from the advancement of the hardware and challenges posed by big data are caused by the contradiction
software technologies. Hardware and software are the two where the existing data processing infrastructures are inca-
major elements that constitute a computing system. The soft- pable of meeting the diverse demands in data processing.
ware performance could directly benefit from the advance- Data processing infrastructure generally includes the
ment of hardware, but it is also limited by the characteristics underlying hardware environment and the upper software
of the hardware. Therefore, there has to be trade-offs in the system. The design principles, architecture selection, core
design of software frameworks and systems. In the mean- functions, strategy mode, and optimization techniques of
time, the demands for software performance also promote the upper software system largely depend on the computer
the advancements and innovations of hardware technolo- hardware. Today’s hardware technologies and environments
gies. For data management and analysis systems, the hard- are undergoing dramatic changes. Specifically, the advent
ware determines the performance limit of data access and of high-performance processors and hardware accelerators,
query processing. To fully utilize the hardware, the software new nonvolatile memory (NVM), and a high-speed network
should optimize the design of algorithms and data structure are rapidly changing the base support for traditional data
according to the hardware. The traditional compute-inten- management and analysis systems. These new hardware
sive applications and recent data-intensive applications both is expected to break through the architecture of the entire
have placed high demands on hardware performance such computer system and convert the assumptions of the upper
as access latency, capacity, bandwidth, energy consumption software. They also require that the architecture of data man-
agement and analysis software and related technologies have
hardware awareness.
* Zhanhuai Li
lizhh@nwpu.edu.cn
1
Northwest Polytechnical University, Xi’an, China
2
Renmin University of China, Beijing, China
3
East China Normal University, Shanghai, China

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264 W. Pan et al.

2 The Trend of Hardware After 2005, high-performance processor technology has

entered the multi-core era and multi-core parallel process-
In recent years, storage, processor, and network technolo- ing technology has become the mainstream. But although
gies have made a great breakthrough. As shown in Fig. 1, a data processing capability has been significantly enhanced
growing set of new hardware, architecture, and features are in multi-core architectures, software cannot automatically
becoming the foundation of the future computing platforms. gain the benefits. Instead, programmers have to transform
The current trends indicate that these techniques are signifi- the traditional serial programs into parallel programs, and
cantly changing the underlying environment of traditional optimize the algorithm performance for the LLC (Last
data management and analysis systems, including high- Level Cache) of multi-core processors. Nowadays, the per-
performance processors and hardware accelerators, NVM, formance of multi-core processors has been significantly
RDMA-capable (remote direct memory access) networks. improved with the semiconductor technology. For exam-
Significantly, the ongoing underlying environments, marked ple, the 14-nm Xeon processor currently integrates up to
by heterogeneous multi-core architecture and hybrid stor- 24 cores, supporting up to 3.07 TB memory and 85 GB/s
age hierarchy, make the already complicated software design memory bandwidth. However, x86 processor still has the
space become more sophisticated [1–4]. disadvantages of low integration, high power consumption,
and high price. Also the general-purpose multi-core proces-
2.1 The Trend of Processor Technologies sors can hardly to meet the demands of the highly concurrent
applications. The development of the processor is going to
The development of processor technology has gone through be specifically optimized for an application, i.e., specialized
for more than 40 years. Its development roadmap has shifted hardware accelerators.
from scale-up to scale-out, and the aim dramatically shifts GPU, Xeon Phi, field programmable gate array (FPGA),
away from pursuing higher clock speed and instead focuses and the like are representative of dedicated hardware accel-
on creating more cores per processor. According to Moore’s erators. By exploiting GPUs, Xeon Phi coprocessors, and
law, pushing the computing frequency of the processor con- FPGAs, parts of compute-intensive and data-intensive
tinuously is one of the most important ways to improve the workload can be offloaded from the CPU efficiently. Some
performance of the computer in the era of serial computing. fundamental hardware characteristics of these accelerators
At the same time, lots of optimization techniques, such as are given in Table 1. There is no doubt that the processing
the instruction-level parallelism (ILP), pipeline, prefetch- environment within the computer system becomes more and
ing, branch prediction, out-of-order instruction execution, more complicated, and correspondingly, the data manage-
multi-level cache, and hyper-threading, can be automatically ment and analysis systems might try to seek diversified ways
identified and utilized by the processor and the compiler. to actively adapt to new situations.
Therefore, software can consistently and transparently enjoy
free and regular performance gains. However, limited by 2.2 The Trend of Storage Technologies
the heat, power consumption, instruction-level parallelism,
manufacturing processes, and other factors, the scale-up As high-performance processors and hardware accel-
approach reaches the ceiling. erator technologies develop rapidly, the performance gap
between CPU and storage keeps widening year by year [5].
The “memory wall” makes the data access become a non-
negligible performance bottleneck. Faced with the slow I/O
capabilities of traditional secondary storage devices, data
management and analysis systems have had to adopt some
design strategies such as cache pools, concurrency control,
and disk-oriented algorithms and data structure to mitigate
or hide I/O performance gap. However, I/O bottlenecks still
severely constrain the processing power of data-intensive
computing.
It is especially interesting that the new storage medium
represented by NVM [6] provides a potential avenue to break
the I/O bottleneck. The NVM is actually a general term for a
type of storage technology which does not represent a spe-
cific storage technology or medium. It is also referred to
as storage class memory (SCM) in some research literature
Fig. 1  New hardware and environment [7]. Typically, NVMs include phase change memory (PCM),

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The New Hardware Development Trend and the Challenges in Data Management and Analysis 265

Table 1  Processor characters
Type Xeon E7-8890 V4 Xeon Phi 7290F Xeon Phi 724P NVIDIA Tesla V100

#core/#thread 24/48 72/288 68/272 5120 CUDA

cores/640 tensor
cores
Core frequency 2.20 GHz 1.50 GHz 1.3 GHz 1.455 GHz
Memory capacity 3.07 TB 384 GB 16 GB 16 GB HBM2 VRAM
Cache capacity 60 MB L3 36 MB L2/16 GB HBM 34 MB L2 6 MB L2
Memory type DDR4-1866/4 channels DDR4-2400/6 channels MCDRAM/16 channels HBM2
Memory bandwidth (GB/s) 85 115.2 500 900
Price $7174.00 $3368.00 $3324.00 $149,000.00

magnetoresistive random access memory (MRAM), resistive bandwidth can be applied to the on-board storage of many-
random access memory (RRAM), and ferroelectronic RAM core processors, delivering high-performance data cache
(FeRAM). Although the characteristics and manufacturing support for the powerful parallel processing. With the NVM
processes of these memories are obviously different, they technology, the multi-level hybrid storage environment will
generally have some common features, including durability, certainly break the balance among the CPU, main memory,
high storage density, low-latency random read/write, and system bus, and external memory in the traditional com-
fine-grained byte addressing. The specifications are given in puter architecture. It will also change the existing storage
Table 2. From a performance point of view, NVM is close to hierarchy and optimize data access critical paths to bridge
the DDR memory, but also has a nonvolatile feature. There- the performance gap between storage tiers, providing new
fore, it may gradually become the main storage device, while opportunities for data management and analytics [8].
DDR memory is used as a temporary data cache. At present,
flash memory technology is today a mature technology. Take 2.3 The Trend of Network Technologies
a single PCIe flash memory for example. Its capacity can
reach up to 12.8 TB, and read/write performance is also In addition to the local storage I/O bottleneck, the network
high. Based on this, it can be a cache between RAM and I/O bottleneck is also the main performance issue in the
hard disk and also can be an alternative of the hard drive datacenter. Under traditional Ethernet network, the lim-
as a persistent storage device. In terms of energy consump- ited data transmission capability and the non-trivial CPU
tion, DRAM consumes less energy under high load. On overhead of the TPC/IP stack have severely impacted the
the contrary, it consumes more energy under low load than performance of distributed data processing. Therefore, the
other storage devices because refreshing the entire DRAM is overall throughput of distributed database system is sharply
required. The common feature of the NVM is that they have reduced under the influence of the high proportion of distrib-
dual capabilities of both DRAM-like high-speed access and uted transactions, which lead to potentially heavy network
disk-like persistence, effectively breaking the “performance IO. Based on this, the existing data management systems
wall” of traditional storage medium that cannot overcome. have to resort to some specific strategies such as coordinated
At the same time, the development of new storage tech- partitioning, relaxed consistency assurance, and determinis-
nologies has also had a significant impact on processor tech- tic execution scheme to control or reduce the ratio of distrib-
nology. The 3D stacking technology that enhances higher uted transactions. However, most of these measures suffer

Table 2  Performance metrics of different storage devices

Attribute DRAM PCM (25 nm) MRAM RRAM FeRAM Flash SSD HDD

Nonvolatile No Yes Yes Yes Yes Yes Yes

Density ­(um2/bit) 0.00380 0.00250 0.00740 0.00580 0.00355 0.00210 0.00006
Read latency (ns) 55 48 20 116 55 25,000 3,000,000
Write latency (ns) 55 150 20 145 55 200,000 3,000,000
Read power consumption (pJ/bit) 12.5 2 0.02 4.81 2.13 250 2500
Write power consumption (pJ/bit) 12.5 19.2 0.03 13.8 10.12 250 2500
Lifespan > 1015 108 1015 108 1014 104 > 1015

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from unreasonable assumptions and applicable conditions, From the classical iterative pipeline processing model
or opaqueness to application developers. In particular, the [11] to the column processing model [12] and finally to
scalability of the system is still greatly limited, especially the vector processing model optimization [13] that is the
when the workload does not have the distinguishable char- combination of the former two, the traditional software-
acteristics to be split independently. based data processing model has reached a mature stage.
It is important to note that the increased contention like- Though, the advent of JIT real-time compilation tech-
lihood is the most cited reasons when discussing the scal- niques [14] and optimization techniques combined with
ability issue of distributed transactions, but in [9], the author vector processing models [15] provides new optimization
showed that the most important factor is the CPU overhead space at the register level. However, with the  deepen-
of the TCP/IP stack incurred by traditional Ethernet net- ing and development of research, software-based optimi-
work. In other words, software-oriented optimization will zation techniques are gradually touching their “ceiling.”
not fundamentally address the scalability issue within dis- Academics and industry are beginning to explore some
tributed environments. In recent years, the high-performance new ways to accelerate the performance of data process-
RDMA-enabled network is dramatically improving the net- ing through software/hardware co-design. Instruction-
work latency and ensures that users can bypass the CPU level optimization [16], coprocessor query optimization
when transferring data on the network. InfiniBand, iWARP, [17, 18], hardware customization [19], workload hardware
and RoCE are all RDMA-enabled network protocols, with migration [20], increasing hardware-level parallelism [21],
appropriate  hardware that can accelerate operations to hardware-level operators [22], and so on are used to pro-
increase the value of application. With price reduction in vide hardware-level performance optimization. However,
RDMA-related hardware, more and more emerging indus- the differences between the new processor and x86 proces-
try clusters working on the RDMA-related network environ- sor fundamentally change the assumptions of traditional
ment, requiring a fundamental rethinking of the design of database software design on hardware. Databases are fac-
data management and analysis systems, include but not lim- ing with more complicated architectural issues on hetero-
ited to distributed query, transaction processing, and other geneous computing platforms. In the future, the researcher
core functions [10]. needs to break the software-centric design idea which is
Although the development of new hardware exhibits com- effective for the traditional database systems.
plicated variety and the composition of the hardware envi- The design of traditional databases has to trade-off among
ronment is also uncertain, it is foreseeable that they eventu- a number of important factors such as latency, storage capac-
ally will become the standard hardware components in the ity, cost effectiveness, and the choice between volatile and
future. Data management and analysis on modern hardware nonvolatile storage devices. The unique properties of NVM
will become a new research hotspots field. bring the opportunity to the development of data manage-
ment systems, but it also introduces some new constraints.
The literature [23] conducted a forward-looking research
3 Research Status and exploration in this area. The results show that neither the
disk-oriented systems nor the memory-oriented systems are
The new hardware will change the traditional computing, ideally suited for NVM-based storage hierarchy, especially
storage, and network systems and put a directly impact on when the skew in the workload is high. The authors also
the architecture and design scheme of the data management found that storage I/O is no longer the main performance
and analysis systems. It will also pose challenges on the core bottleneck in the NVM storage environment [24]; instead, a
functionalities and related key technologies including index- significant amount of cost on how to organize, update, and
ing, analysis, and transaction processing. In the next part, we replace data will become new performance bottlenecks. For
will introduce the present state of domestic and international NVM-based storage hierarchy, WAL (Write-Ahead Log-
relevant research. ging) and logical logs that are common in the traditional
database also have a large variety of unnecessary operations
3.1 System Architecture and Design Schemes [25]. These issues indicate that diversified NVM-based stor-
in Platforms with New Hardware age hierarchy will lead to the new requirements for cache
replacement [26], data distribution [27], data migration [28],
The advent of high-performance processors and new accel- metadata management [29], query execution plan [30], fault
erators has led to the shift from single-CPU architectures recovery [25], and other aspects to explore corresponding
systems to heterogeneous, hybrid processing architectures. design strategies to better adapt to new environments. There-
Data processing strategies and optimization techniques fore, NVM-specific or NVM-oriented architecture designed
have evolved from standardization to customization and to utilize the nonvolatile property of NVM is necessary. The
from software optimization to hardware optimization. research about this area is just beginning; CMU’s N-Store

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[31] presents exploratory research on how to build prototype data directly with the processor using a memory bus or a
database system on NVM-based storage hierarchy. dedicated bus, memory objects that do not need to be seri-
RDMA-enabled network is changing the assumption in alized into disk can be directly created with heap. Typical
traditional distributed data management systems in which research works include NV-heap [46], Mnemosyne [48],
network I/O is the primary performance bottleneck. Some and HEAPO [49]. In addition, the NVM memory environ-
systems [32, 33] have introduced RDMA inside, but they ment also brings a series of new problems to be solved, such
just carry out some add-on optimizations for RDMA later; as ordering [47], atomic operations [50], and consistency
the original architecture is obsolete. As a result, they can- guarantee [51]. In contrast, file-based NVM abstraction can
not take full advantage of the opportunities presented by take advantage of the semantics of existing file systems in
RDMA. It has been demonstrated [34] that migrating a namespaces, access control, read–write protection, and so
legacy system to an RDMA-enabled network simply cannot on. But, in the design, in addition to take full advantage of
fully exploit the benefits of the high-performance network; the fine-grained addressing and in-place update capability
neither the shared-nothing architecture nor the distributed of NVM, the impact of frequent writes on NVM lifetime
shared-memory architecture can bring out the full potential needs to be considered [52]. Besides, file abstraction has a
of RDMA. For a shared-nothing architecture, the optimi- long data access path which implies some unnecessary soft-
zation goal is to maximize data localization, but the static ware overhead [53]. PRAMFS [54], BPFS [47], and SIMFS
partitioning technique [35] or dynamic partitioning strategy [55] are all typical NVM-oriented file systems. Whether
does not fundamentally resolve the problem of frequent net- abstracting the NVM in the way of persisting memory heap
work communication [36]. Even with IPoIB (IP over Infini- or file system can become the basic building block for the
band) support, for shared-nothing architecture, it is difficult upper data processing technology [56]. However, they can
to gain the most improvement on data-flow model and con- only provide low-level assurance on atomicity. Some of the
trol-flow model simultaneously [9]. Similarly, for distributed high-level features (such as transaction semantics [57], non-
shared-memory architectures, there is no built-in support for volatile data structures [58], etc.) also require corresponding
cache coherency; accessing cache via RDMA could have change and improvement in upper data management system.
significant performance side effects if mismanaged from Different performance characteristics of NVMs will affect
client [37]. At the same time, garbage collection and cache the data access and processing strategies of the heteroge-
management might also be affected by it. In the RDMA net- neous processor architecture. On the contrary, the comput-
work, the uniform abstraction for remote and local memory ing characteristics of the processors also affect the storage
has proven to be inefficient [38]. Research [9] shows that policy. For example, under the coupled CPU/GPU processor
the emerging RDMA-enabled high-performance network architecture, the data distribution and the exchange should be
technologies necessitate a fundamental redesign of the way designed according to the characteristics of low-latency CPU
we build distributed data management system in the future. data access and the large-granularity GPU data processing.
In addition, if NVM can be used to add a large-capacity, low-
3.2 Storage and Indexing Techniques in Platforms cost, high-performance storage tier under traditional DRAM,
with New Hardware hardware accelerators such as GPU can access NVM stor-
age directly across the memory through dedicated data chan-
Since NVM can serve as both internal and external mem- nel, reducing the data transfer cost in traditional storage
ory, the boundaries between the original internal and exter- hierarchies [59]. We need to realize that hybrid storage and
nal memory are obscured, making the composition of the heterogeneous computing architecture will exist for a long
underlying NVM storage diverse. Because different NVMs time. The ideal technical route in the future is to divide the
have their own features on access delay, durability, etc., it is data processing into different processing stages according
theoretically possible to replace traditional storage medium to the type of workload and to concentrate the computing
without changing the storage hierarchy [39–41] or mix on the smaller data set to achieve the goal of accelerating
with them [42, 43]. In addition, NVMs also can enrich the critical workloads through hardware accelerators. It is the
storage hierarchies as a LLC [44] or as a new cache layer ideal state to concentrate 80% of the computational load on
between RAM and HDD [45], which further reduce read/ 20% of the data [60], which simplifies data distribution and
write latency across storage tiers. The variety of the storage computing distribution strategies across hybrid storage and
environment also places considerable complexity in imple- heterogeneous computing platforms.
menting data management and analysis techniques. In addition to improving data management and analytics
From data management perspective, how to integrate support at the storage level, indexes are also key technolo-
NVM into the I/O stack is a very important research topic. gies for efficiently organizing data to accelerate the perfor-
There are two typical ways to abstract NVM, as persistence mance of upper-level data analytics. Traditional local index-
heap [46] or as file system [47]. Because NVM can exchange ing and optimization techniques based on B+ tree, R-tree,

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268 W. Pan et al.

or KD-tree [61–63] are designed for the block-level storage. relaxed. In the future, how to design, organize, and oper-
Due to the significant difference between NVM and disk, the ate write-limited algorithms and data structures is an urgent
effectiveness of the existing indexes can be severely affected question. However, it is important to note that with NVM
in NVM storage environments. For NVM, the large number asymmetric read/write costs, the major performance bottle-
of writes caused by index updates not only reduces their necks have shifted from the ratio of sequential and random
lifespan but also degrades their performance. To reduce fre- disk I/O to the ratio of NVM read and write. As a result,
quent updates and writes of small amounts of data, merge previous cost models [77] inevitably fail to characterize
updates [64] or late updates [65], which are frequently used access patterns of NVM accurately. Furthermore, heteroge-
on flash indexes, are typical approaches. Future indexing neous computing architectures and hybrid storage hierarchy
technologies for NVM should be more effective in control- will further complicate the cost estimation in new hardware
ling the read and write paths and impact areas that result environments [30, 73]. Therefore, how to ensure the validity
from index updates, as well as enabling layered indexing and correctness of the cost model under the new hardware
techniques for the NVM storage hierarchies. At the same environment is also a challenging issue. In the NVM storage
time, concurrency control on indexes such as B+ tree also environment, the basic design principle for NVM-oriented
shows obvious scalability bottlenecks in highly concurrent algorithms and data structures is to reduce the NVM write
heterogeneous computing architectures. The coarse-grained operations as much as possible. Put another way, write-
range locks of traditional index structures and the critical limited (NVM-aware, NVM-friendly) algorithms and data
regions corresponding to latches are the main reasons for structures are the possible strategy.
limiting the degree of concurrency. Some levels of optimiza- From the point of view of processor development, query
tion techniques such as multi-granularity locking [66] and optimization technologies have gone through several dif-
latch avoidance [67] increase the degree of concurrency of ferent stages with the evolution of hardware. During dif-
indexed access updates, but they also unavoidably introduce ferent development stages, there are significant differences
the issue of consistency verification, increased transaction in query optimization goals, from mitigating disk-oriented
failure rates, and higher overhead. In the future, the indexing I/O to designing cache-conscious data structures and access
technology for highly concurrent heterogeneous computing methods [78–81] and developing efficient parallel algorithm
infrastructure needs a more lightweight and flexible lock [40, 82, 83]. Nowadays, the processor technology moves
protocol to balance the consistency, maximum concurrency, from multi-core to many-core which greatly differs from the
and lock protocol simplicity. multi-core processor in terms of core integration, number
of threads, cache structure, and memory access. The object
3.3 Query Processing and Optimization in Platforms that should be optimized has been turned into SIMD [84,
with New Hardware 85], GPUs, APUs, Xeon Phi coprocessors, and FPGAs [18,
86–88]. The query optimization is becoming more and more
The basic assumption of the traditional query algorithms and dependent on the underlying hardware. But current query
data structures on the underlying storage environment does optimization techniques for new hardware are in an awkward
not stand in NVM storage environment. Therefore, the tra- position: lacking the holistic consideration for evolving hard-
ditional algorithms and data structures are difficult to obtain ware, the algorithm requires constant changes to accommo-
the ideal effect in the NVM storage environment. date different hardware features, from predicate processing
Reducing NVM-oriented writes is a major strategy in [89] to join [90] to index [91]. From a perspective of the
previous studies. A number of technologies, which include overall architecture, the difficulty of query optimization is
unnecessary write avoiding [39], write cancelation and write further increased under new hardware architecture.
pausing strategies [68], dead write prediction [69], cache In optimization techniques for join algorithm, a hot
coherence enabled refresh policy [70], and PCM-aware research topic in recent years is to explore whether hard-
swap algorithm [71], are used to optimize the NVM writes. ware-conscious or hardware-oblivious algorithm designs are
With these underlying optimizations for drivers, FTL, and the best choices for new hardware environments. The goal of
memory controller, the algorithms can directly benefit, but hardware-conscious algorithms is the pursuit of the highest
algorithms can also be optimized from a higher level. In performance, whose guiding ideology is to fully consider
this level, there are two ways to control or reduce NVM the hardware-specific characteristics to optimize join algo-
writes: One is to take advantage of extra caches [72, 73] to rithms; instead, the goal of hardware-oblivious algorithms is
mitigate NVM write requests with the help of DRAM; the the pursuit of generalizing and simplify, whose guiding prin-
other is to utilize the low-overhead NVM reads and in-time ciple is to design the join algorithm based on the common
calculations to waive the costly NVM writes [58, 74]. For characteristics of the hardware. The competition between
further reducing NVM writes, even parts of constraints on the two technology routes has intensified in recent years,
data structures or algorithms [74–76] can be appropriately from the basic CPU platform [92] to the NUMA platform

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[93], and it will certainly be extended to the new processor many different optimization technologies on NVM-oriented
platforms in the future. The underlying reason behind this logging, including two-layer logging architecture [56], log
phenomenon is that it is difficult to quantify the optimization redundancies elimination [100], cost-effective approaches
techniques, as in the field of in-memory database technol- [101], decentralized logging [102] and others. In some
ogy, although there are numerous hash structures and join sense, the existing logging technologies for NVM are actu-
algorithms currently [94–96], the simple question of which ally stop-gap solutions [102]. For future NVM-based sys-
is the best in-memory hash join algorithm is still unknown tems, the ultimate solution is that to develop logging tech-
[97]. In the future, when the new hardware environment is nology on pure-NVM environment, where the entire storage
more and more complicated, performance should not be the system, including the multi-level cache on processor, will
only indicator to evaluate the advantages and disadvantages consist of NVM. Current research generally lacks attention
of algorithm. More attention should be paid to improving the on the durability of NVM; thus, finding a more appropri-
adaptability and scalability of algorithms on heterogeneous ate trade-off among high-speed I/O, nonvolatility, and poor
platforms. write tolerance is the focus of future NVM logging research.
Concurrent control effectively protects the isolation prop-
3.4 Transaction Processing in Platforms with New erty of transactions. From the execution logic of the upper
Hardware layers of different concurrency control protocols, it seems
that the underlying storage is isolated and transparent. But
Recovery and concurrency control are the core functions of in essence, the specific implementation of concurrency con-
transaction processing in DBMS. They are closely related trol and its overhead ratio in system are closely related to
to the underlying storage and computing environment. Dis- the underlying storage environment. Under the traditional
tributed transaction processing is also closely related to the two-tier storage hierarchy, the lock manager for concurrency
network environment. control in memory is almost negligible, because the disk I/O
WAL-based recovery methods [98] can be significantly bottlenecks are predominant. But in NVM storage environ-
affected in NVM environments. First, because the data writ- ment, with the decrease in the cost of disk I/O, the memory
ten on the NVM are persistent, transactions are not forced overhead incurred by lock manager becomes a new bottle-
to be stored to disk when submitted, and the design rules neck [103]. In addition, with the multi-core processors, the
for flush-before-commit in the WAL are broken. Moreover, contradiction between the high parallelism brought by rich
because of NVM high-speed random read/write capabili- hardware context and the consistency of data maintenance
ties, the advantages of the cache turn into disadvantages. will further aggravate the complexity of lock concurrency
In extreme cases, transactional update data can also have control [104–106]. The traditional blocking strategies, such
significant redundancies in different locations (log buff- as blocking synchronization and busy-waiting, are difficult to
ers, swap areas, disks) [25]. The NVM environment not apply [107]. To reduce the overhead of concurrency control,
only has an impact on the assumptions and strategies of it is necessary to control the lock manager’s resource compe-
WAL, but also brings some new issues. The way to ensure tition. The research mainly focuses on reducing the number
the atomic NVM write operation is the most fundamental of locks with three main approaches, including latch-free
problem. Through some hardware-level primitives [25] and data structures [108], lightweight concurrency primitives
optimization on processor cache [50], this problem can be [109], and distributed lock manager [110]. In addition, for
guaranteed partially. In addition, due to the effect of out- MVCC, there is a tight location coupling between the index
of-order optimization in modern processor environments, and the multi-version records in the physical storage. This
there is a new demand in serializing the data written into will result in serious performance degradation when updat-
NVM to ensure the order of log records. Memory barriers ing the index. In a hybrid NVM environment, an intermedi-
[47] became the main solution, but the read/write latencies ate layer constructed by low-latency NVM can be used to
caused by memory barriers in turn degrade the transactional decouple the relationship between the physical representa-
throughput based on WAL. Thus, the introduction of NVM tion and the logical representation of the multi-version log
changes the assumptions in the log design, which will inevi- [111]. This study that builds a new storage layer to ease the
tably introduce new technical issues. bottleneck of reading and writing is worth learning.
There is a tight coupling between the log technology and The approach to improving the extensibility of distrib-
NVM environment. In the case of directly replacing the uted transactions has always been the central question in
external storage by NVM, the goal of log technology opti- building distributed transactional systems. On the basis of
mization is to reduce the software side effects incurred by a large number of previous studies [112–114], the research-
ARIES-style logs [99]. In the NVM memory environment, ers have already formed a basic consensus that it is difficult
it can be further subdivided into different levels, including to guarantee the scalability of systems with a large num-
hybrid DRAM/NVM and NVM only. Currently there are ber of distributed transactions. Therefore, research focuses

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270 W. Pan et al.

on how to avoid distributed transactions [115, 116] and to the future, it is necessary to research with the overall system
control and optimize the proportion of distributed transac- and core functions. In view of the coexistence of traditional
tions [117–119]. Most of these technologies are not trans- hardware and new hardware as well as the common prob-
parent to application developers and need to be carefully lems of extracting and abstracting differentiated hardware,
controlled or preprocessed at the application layer [120]. the future research will be based on perception, customi-
On the other hand, a large number of studies are also explor- zation, integration, adaptation, and even reconstruction in
ing how to deregulate strict transactions semantic. Under studying the appropriate architecture, components, strate-
this background, the paradigm of data management is also gies, and technologies, in order to release the computing and
shifting from SQL, NoSQL [121] to NewSQL [122, 123]. storage capacity brought by the new hardware.
This development once again shows that, for a large num-
ber of critical applications, it is impossible to forego the
transaction mechanism even with requirements of scalability 4 Research Challenges and Future Research
[124]. However, these requirements are hard to meet in the Directions
traditional network. In traditional network environments,
limited bandwidth, high latency, and overhead make distrib- 4.1 Challenges
uted transactions not scalable. With RDMA-enabled high-
performance network, the previously unmanageable hard- Software’s chances of being any more successful depend
ware limitations and software costs are expected to be fully on whether they can accurately insight into holistic impacts
mitigated [38]. The RDMA-enabled network addresses the on the system design; define performance bounds of the
two most important difficulties encountered with traditional hardware; put forward new assumptions on new environ-
distributed transaction scaling: limited bandwidth and high ment; and seek for the good trade-off. These are all the chal-
CPU overhead in data transfers. Some RDMA-aware data lenges that data management and analytics systems must
management systems [32] have also emerged, but such sys- cope with.
tems are primarily concerned with direct RDMA support at
the storage tier, and transaction processing is not the focus. 1. Firstly, at the system level, new hardware and environ-
Other RDMA-aware systems [125] focus on transactional ment have a systemic impact on existing technologies.
processing, but they still adopt centralized managers that This may introduce new performance bottlenecks after
affect the scalability of distributed transactions. In addition, eliminating existing ones. Therefore, it is necessary to
although some data management systems that fully adopt examine their impact in a higher-level context. In the
RDMA support distributed transactions, they have only have heterogeneous computing environment composed by
limited consistent isolation levels, such as serialization [38] new processors and accelerators, although the insuf-
and snapshot isolation [9, 34]. Relevant research [9] shows ficiency of large-scale parallel capabilities can be off-
that the underlying architecture of data management should set, the problems of the memory wall, von-Neumann
to be redesigned, such as the separation of storage and com- bottleneck, and energy wall may become even worse
puting. Only in this way, it is possible to fully exploit all in the new heterogeneous computing environment. The
the advantages of RDMA-enabled networks to achieve fully communication delay between heterogeneous process-
scalable distributed transactions. ing units, limited cache capacity, and the non-uniform
The new hardware and environment has many encour- storage access cost may become a new performance
aging and superior features, but it is impossible to auto- problem. In the environment of new nonvolatile storage,
matically enjoy the “free lunch” by simply migrating exist- the restrictions in disk I/O stack can be eliminated, but
ing technologies onto the new platform. Traditional data the new NVM I/O stack will significantly magnify the
management and analysis techniques are based on the x86 software overhead that is typically ignored in traditional
architecture, two-tier storage hierarchy, and TCP/IP-Ether- I/O stack. Therefore, redesigning the software stack to
net. The huge differences from heterogeneous computing reduce its overhead ratio has become a more important
architectures, nonvolatile hybrid storage environments, and design principle. In high-performance network architec-
high-performance networking systems determine that the tures, while network I/O latency is no longer a major
traditional design principles and rules of thumb are difficult constriction in system design, the efficiency of processor
to apply. In addition, in the new hardware environment, inef- caches and local memory becomes more important.
ficient or useless components, and technologies in traditional 2. Secondly, the design philosophy of the algorithm and
data management and analysis systems also largely limit the data structure in the new hardware environment needs to
efficiency of the hardware. Meanwhile, under the trend of be changed. Directly migrating or partially tuning algo-
diversified development of the hardware environment, there rithms and data structures cannot fully exploit the char-
lacks the corresponding architectures and technologies. In acteristics of the new hardware. At the processor level,

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The New Hardware Development Trend and the Challenges in Data Management and Analysis 271

data structures and cache-centric algorithms designed logical order. If a single NVM is used to simplify tra-
for x86-based processors are not designed to match the ditional storage tiers, the data serializing on the NVM
hardware features of the compute-centric many-core must be addressed.
processor. Many mature query processing techniques 4. Finally, under the new hardware environment, hard-
may fail in platforms with many-core processors. Data- ware/software co-design is the inevitable way for the
base has long been designed based on the ideas of serial data management and analysis system. The new hard-
and small-scale parallel processing-based programming. ware technology has its inherent advantages and dis-
This makes the traditional query algorithms difficult advantages, which cannot completely replace the origi-
to convert to a large-scale parallel processing mode. nal hardware. For a long time, it is inevitable that the
At the storage level, although the NVM has both the traditional hardware and new hardware coexist. While
advantages of internal and external memory, NVM also providing diversified hardware choices, this also leads to
has some negative features such as asymmetric read/ more complicated design strategies, more difficult opti-
write costs and low write endurance. These features are mization techniques and more difficult performance tun-
significantly different with traditional storage environ- ing space. In a heterogeneous computing environment,
ment, so previous studies on memory, disk, and flash using coprocessor or co-placement to achieve custom-
cannot achieve ideal performance within a new storage ized data processing acceleration has created signifi-
hierarchy containing NVM. At the network level, the cant differences in system architecture. Moreover, the
RDMA-enabled cluster is a new hybrid architecture, threshold of parallel programming has become increas-
which is distinct from message-passing architecture or ingly high, and the gap between software and hardware
shared-memory architecture. Therefore, the technologies is becoming larger than ever before. In some cases, the
in the non-uniform memory access architecture cannot development of software lags behind hardware. In many
be directly applied to the RDMA cluster environment. applications, the actual utilization rate of hardware is
3. Thirdly, the impact of new hardware and environments well below the upper limit of the performance [126].
on data management and analytics technologies is com- However, the new memory devices have significant dif-
prehensive, deep, and crosscutting. Due to the new fea- ferentiation and diversification. There is great flexibility
tures of the new hardware environment, the functionali- and uncertainty in making use of the new nonvolatile
ties of data management systems cannot be tailored to memory to construct a NVM environment. Whether the
adapt to the new hardware environment. In heterogene- components constitute a simple or a mixed form, and
ous computing environments with new processors and whether the status is equivalent or undetermined, the
accelerators, the parallel processing capacity is greatly upper data management and analysis technology has
improved. However, the richer hardware contexts also also brought great challenges to research. In high-perfor-
pose stringent challenges on achieving high throughput mance network system, although InfiniBand has consid-
and maintaining data consistency. The impact of NVM ered RDMA from the beginning, the traditional Ethernet
on the logging will fundamentally change the length of has also proposed the solution to support RDMA. There
the critical path of transactions. The reduction in the is no exact answer at present on which kind of plan can
transaction submission time will result in lock competi- form the intact industry ecology at the end. Therefore, it
tion, affecting the overall system concurrency capacity is even more necessary to conduct cutting-edge research
and the throughput. With low-latency and high-band- as soon as possible to explore a new data management
width, high-performance networks will change the sys- architecture suitable for high-performance network envi-
tem’s basic assumptions that distributed transactions are ronments.
difficult to extend. This is also true with the optimization
objective of minimizing network latency when designing
distributed algorithms. Cache utilization in multi-core 4.2 Future Research
architectures will become the new optimization direc-
tion. In addition, some of the existing data management New hardware environments such as heterogeneous com-
components have composite functions. For example, the puting architectures, hybrid storage environments, and
existing buffer not only relieves the I/O bottleneck of high-performance network will surely change the base
the entire system, but also reduces the overhead of the support of traditional data management and analysis sys-
recovery mechanism. A more complicated scenario is tems. It will bring significant opportunities for the devel-
the crosscutting effect between the new hardware and the opment of key technologies. The future of research can
environment. For example, the out-of-order instruction start from the following aspects.
execution techniques in processors can cause the cached
data to be not accessed and executed in the application’s

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272 W. Pan et al.

1. Lightly coupled system architecture and collaborative zation and reconstruction techniques as well as the data
design scheme The computing, storage, and networking access accelerating and data filtering technology in the
environments have heterogeneity, diversity, and hybrid- FPGA, the preprocessing on the original data can be
ism. The different environmental components have a effectively completed. This will reduce the amount of
significant impact on the design of the upper data man- data to be transferred, thereby alleviating bottlenecks of
agement system architecture. To effectively leverage the data access in large-scale data processing. Moreover, the
power of new hardware, the seamless integration of new NVM environment has a richer storage hierarchy, while
hardware into the data management stack is an impor- new processor technology also provides additional data
tant fundamental research topic. To be compatible with processing capabilities for indexing. Therefore, multi-
diverse hardware environments and to reduce the risk of level and processor-conscious indexing technology is
failure in highly coupled optimization techniques with also a future research direction.
specific hardware, the different heterogeneous, hybrid 3. Hardware-aware query processing and performance
hardware environments must be effectively abstracted optimization Query processing is the core operation
and virtualized. Abstraction technology can extract in data analysis, involving a series of complex activi-
common features for hardware, reduce the low-level ties in the data extraction process. The high degree of
over coupling while ensuring hardware awareness, and parallelism and customizable capabilities provided by
provide flexible customization and service support for heterogeneous computing architectures, as well as the
upper-layer technologies. In the meantime, the execu- new I/O features of NVM environments, make previous
tion cost and the proportions of different operations will query processing and optimization mechanisms difficult
change under the new hardware environment, and the to apply. Future research may focus on two aspects. One
bottleneck of the system is also shifting. As a result, the is query optimization technology in NVM environment:
negligible overhead in traditional software stacks would high-speed NVM read and write, byte addressable,
be significantly magnified. Therefore, based on this, new asymmetric read and write, and other features. It will
performance bottlenecks need to be found, a reasonable exert a significant impact on traditional query opera-
software stack needs to be redesigned, and the software tions such as join, sort, and aggregation. At the same
overhead in the new hardware environment needs to be time, NVM has changed the composition of traditional
reduced. In addition, the new hardware environment storage hierarchy and also affected the traditional meas-
has advantages including low latency, high capacity, urement hypothesis of estimating query cost, which is
high bandwidth, and high speed read and write. This based on the cost of disk I/O. Therefore, it is neces-
has brought new opportunities for development of the sary to study the cost model in NVM environment and
integration of OLTP and OLAP system and achieving the design and optimization of write-limited algorithms
convergent OLTAP system. and data structures, so that the negative impact of NVM
2. Storage and index management with mixed heterogene- write operations is alleviated. On the other hand, query
ous hardware environments Because of both internal optimization technology under heterogeneous processor
and external memory capabilities, the new nonvolatile platforms: the introduction of a new processor increases
memory obscures the clear boundaries between exist- the dimension of heterogeneous computing platforms,
ing storages. This also offers a considerable degree of resulting in the increased complexity of the query opti-
freedom for the construction of the new nonvolatile mization techniques. This poses a huge challenge to the
storage environment and storage methods. The method design of query optimizers. Collaborative query pro-
can provide a powerful guarantee for accelerating the cessing technology, query optimization technology, and
processing of data in the upper layer. Although the high- hybrid query execution plan generation technology are
speed I/O capabilities of NVM offer opportunities for all ways to improve the query efficiency in the hetero-
enhancing data access performance, NVM only ensures geneous computing platform.
nonvolatility only at the device level. At the system 4. New hardware-enabled transaction processing technolo-
lever, however, the caching mechanisms may introduce gies Concurrency control and recovery are core func-
the inconsistency issue. Therefore, in the future, col- tions in data management which ensure transaction iso-
laborative technology needs to be studied at different lation and persistence. Their design and implementation
levels such as architecture, strategy, and implementa- are tightly related to the underlying computing and stor-
tion. In addition, as a dedicated acceleration hardware, age environment. At the same time, high-performance
FPGA has its own unique advantages in accelerating network environments also provide new opportunities
data processing. In particular, the combination of NVM for distributed transaction processing which were dif-
features can further enhance the data processing effi- ficult to scale out. First of all, the storage hierarchy and
ciency. Therefore, with the data storage engine optimi- the new access characteristics have the most significant

13
The New Hardware Development Trend and the Challenges in Data Management and Analysis 273

impact on transaction recovery technology. Database Open Access  This article is distributed under the terms of the Crea-
recovery technology needs to be optimized accord- tive Commons Attribution 4.0 International License (http://creat​iveco​
mmons​.org/licen​ses/by/4.0/), which permits unrestricted use, distribu-
ing to the features of NVM. Recovery technology for tion, and reproduction in any medium, provided you give appropriate
NVM, partitioning technology, and concurrent control credit to the original author(s) and the source, provide a link to the
protocol based on NVM are all urgent research topics. Creative Commons license, and indicate if changes were made.
Second, transactions typically involve multiple types
of operations as well as synchronization among them.
However, general-purpose processors and specialized References
accelerators have different data processing modes. Sep-
arating the transactional processing performed by the 1. Bordawekar RR, Sadoghi M (2016) Accelerating database work-
loads by software–hardware-system co-design. In: 2016 IEEE
general-purpose CPU, and offloading part of the work- 32nd international conference on data engineering (ICDE).
load to specialized processor, is capable of enhancing IEEE, pp 1428–1431
the performance of transaction processing. Therefore, 2. Viglas SD (2015) Data management in non-volatile memory. In:
studying the load balancing and I/O optimization tech- Proceedings of the 2015 ACM SIGMOD international confer-
ence on management of data. ACM, pp 1707–1711
nologies that accelerate the transaction processing is an 3. Ailamaki A (2015) Databases and hardware: the beginning
effective way to solve the performance bottlenecks in and sequel of a beautiful friendship. Proc VLDB Endow
transaction processing. Furthermore, in RDMA-enabled 8(12):2058–2061
network, the assumption about distributed transactions 4. Swanson S, Caulfield AM (2013) Refactor, reduce, recycle:
restructuring the i/o stack for the future of storage. Computer
cannot scale will cease to exist. RDMA-enabled distrib- 46(8):52–59
uted commit protocols and pessimistic and optimistic 5. Lim K, Chang J, Mudge T et al (2009) Disaggregated memory for
concurrency control approaches for RDMA may all be expansion and sharing in blade servers. ACM SIGARCH Comput
potential research directions. Archit News 37(3):267–278
6. Xue CJ, Sun G, Zhang Y et al (2011) Emerging non-volatile
memories: opportunities and challenges. In: 2011 Proceedings of
the 9th international conference on hardware/software codesign
and system synthesis (CODES + ISSS). IEEE, pp 325–334
5 Conclusion 7. Freitas R (2010) Storage class memory: technology, systems and
applications. In: 2010 IEEE hot chips 22 symposium (HCS).
The new hardware and its constructed environment will IEEE, pp 1–37
8. Arulraj J, Pavlo A (2017) How to build a non-volatile mem-
deeply influence the architecture of the entire computing ory database management system. In: Proceedings of the 2017
system and change the previous assumptions of the upper- ACM international conference on management of data. ACM, pp
layer software. While providing higher physical perfor- 1753–1758
mance, software architectures and related technologies for 9. Zamanian E, Binnig C, Harris T et  al (2017) The end of a
myth: distributed transactions can scale. Proc VLDB Endow
data management and analysis are also required to sense and 10(6):685–696
adapt to the new hardware features. The new hardware envi- 10. Barthels C, Alonso G, Hoefler T (2017) Designing databases
ronment has made the trade-off between data management for future high-performance networks. IEEE Data Eng Bull
and analytics system design space more complex, posing 40(1):15–26
11. Graefe G (1994) Volcano/spl minus/an extensible and paral-
multidimensional research challenges. In the future, there lel query evaluation system. IEEE Trans Knowl Data Eng
is an urgent need to break the oldness of the traditional data 6(1):120–135
management and analysis software. It is also necessary to 12. Idreos S, Groffen F, Nes N et al (2012) MonetDB: two decades of
manage and analyze the core system functions based on the research in column-oriented database architectures. Q Bull IEEE
Comput Soc Tech Comm Database Eng 35(1):40–45
characteristics of hardware environments and explore and 13. Zukowski M, van de Wiel M, Boncz P (2012) Vectorwise: A
research new data processing modes, architectures, and tech- vectorized analytical DBMS. In: 2012 IEEE 28th international
nologies from the bottom up. conference on data engineering (ICDE). IEEE, pp 1349–1350
14. Neumann T (2011) Efficiently compiling efficient query plans for
Acknowledgements  The authors would like to thank Mike Dixon for modern hardware. Proc VLDB Endow 4(9):539–550
polishing the paper. He is an older gentleman from Salt Lake City. This 15. Lang H, Mühlbauer T, Funke F et al (2016) Data blocks: hybrid
work is supported by the National Natural Science Foundation of China OLTP and OLAP on compressed storage using both vectoriza-
under Grant Nos. 61472321, 61672432, 61732014, and 61332006 and tion and compilation. In: Proceedings of the 2016 international
the National High Technology Research and Development Program of conference on management of data. ACM, pp 311–326
China under Grant No. 2015AA015307. 16. Polychroniou O, Raghavan A, Ross KA (2015) Rethinking SIMD
vectorization for in-memory databases. In: Proceedings of the
2015 ACM SIGMOD international conference on management
Compliance with Ethical Standards  of data. ACM, pp 1493–1508
17. Sukhwani B, Thoennes M, Min H et al (2015) A hardware/soft-
Conflict of interest  The authors declare that they have no competing ware approach for database query acceleration with fpgas. Int J
interests. Parallel Program 43(6):1129–1159

13

274 W. Pan et al.

18. Meister A, Breß S, Saake G (2015) Toward GPU-accelerated 39. Bishnoi R, Oboril F, Ebrahimi M et al (2014) Avoiding unneces-
database optimization. Datenbank Spektrum 15(2):131–140 sary write operations in STT-MRAM for low power implementa-
19. Jha S, He B, Lu M et al (2015) Improving main memory hash tion. In: 2014 15th international symposium on quality electronic
joins on Intel Xeon Phi processors: an experimental approach. design (ISQED). IEEE, pp 548–553
Proc VLDB Endow 8(6):642–653 40. Yue J, Zhu Y (2013) Accelerating write by exploiting PCM
20. Woods L, István Z, Alonso G (2014) Ibex: an intelligent storage asymmetries. In: 2013 IEEE 19th international symposium on
engine with support for advanced SQL offloading. Proc VLDB high performance computer architecture (HPCA2013). IEEE, pp
Endow 7(11):963–974 282–293
21. Woods L, Alonso G, Teubner J (2015) Parallelizing data process- 41. Yang J, Minturn DB, Hady F (2012) When poll is better than
ing on FPGAs with shifter lists. ACM Trans Reconfig Technol interrupt. FAST 12:3
Syst (TRETS) 8(2):7 42. Qureshi MK, Srinivasan V, Rivers JA (2009) Scalable high
22. He B, Yang K, Fang R et al (2008) Relational joins on graphics performance main memory system using phase-change
processors. In: Proceedings of the 2008 ACM SIGMOD inter- memory technology. ACM SIGARCH Comput Archit News
national conference on management of data. ACM, pp 511–524 37(3):24–33
23. DeBrabant J, Arulraj J, Pavlo A et al (2014) A prolegomenon on 43. Dhiman G, Ayoub R, Rosing T (2009) PDRAM: a hybrid
OLTP database systems for non-volatile memory. In: ADMS@ PRAM and DRAM main memory system. In: 46th ACM/
VLDB IEEE design automation conference, 2009, DAC’09. IEEE,
24. Pavlo A (2015) Emerging hardware trends in large-scale transac- pp 664–669
tion processing. IEEE Internet Comput 19(3):68–71 44. Wang Z, Shan S, Cao T et al (2013) WADE: writeback-aware
25. Coburn J, Bunker T, Schwarz M et al (2013) From ARIES to dynamic cache management for NVM-based main memory sys-
MARS: transaction support for next-generation, solid-state tem. ACM Trans Archit Code Optim (TACO) 10(4):51
drives. In: Proceedings of the twenty-fourth ACM symposium 45. Seok H, Park Y, Park KH (2011) Migration based page caching
on operating systems principles. ACM, pp 197–212 algorithm for a hybrid main memory of DRAM and PRAM. In:
26. DeBrabant J, Pavlo A, Tu S et al (2013) Anti-caching: a new Proceedings of the 2011 ACM symposium on applied computing.
approach to database management system architecture. Proc ACM, pp 595–599
VLDB Endow 6(14):1942–1953 46. Coburn J, Caulfield AM, Akel A et al (2011) NV-Heaps: making
27. Kim D, Lee S, Chung J et al (2012) Hybrid DRAM/PRAM-based persistent objects fast and safe with next-generation, non-volatile
main memory for single-chip CPU/GPU. In: Proceedings of the memories. ACM Sigplan Not 46(3):105–118
49th annual design automation conference. ACM, pp 888–896 47. Condit J, Nightingale EB, Frost C et al (2009) Better I/O through
28. Yoon HB, Meza J, Ausavarungnirun R et al (2012) Row buffer byte-addressable, persistent memory. In: Proceedings of the
locality aware caching policies for hybrid memories. In: 2012 ACM SIGOPS 22nd symposium on operating systems principles.
IEEE 30th international conference on computer design (ICCD). ACM, pp 133–146
IEEE, pp 337–344 48. Volos H, Tack AJ, Swift MM (2011) Mnemosyne: lightweight
29. Meza J, Chang J, Yoon HB et al (2012) Enabling efficient and persistent memory. ACM SIGARCH Comput Archit News ACM
scalable hybrid memories using fine-granularity DRAM cache 39(1):91–104
management. IEEE Comput Archit Lett 11(2):61–64 49. Hwang T, Jung J, Won Y (2015) Heapo: heap-based persistent
30. Manegold S, Boncz P, Kersten ML (2002) Generic database cost object store. ACM Trans Storage (TOS) 11(1):3
models for hierarchical memory systems. In: Proceedings of the 50. Giles E, Doshi K, Varman P (2013) Bridging the programming
28th international conference on very large data bases. VLDB gap between persistent and volatile memory using WrAP. In:
endowment, pp 191–202 Proceedings of the ACM international conference on computing
31. Carnegie Mellon Database Group [EB/OL] (2016) N-Store. frontiers. ACM, p 30
http://db.cs.cmu.edu/proje​cts/nvm/. Accessed 22 Nov 2017 51. Zhao J, Li S, Yoon DH et al (2013) Kiln: closing the performance
32. Tinnefeld C, Kossmann D, Grund M et al (2013) Elastic online gap between systems with and without persistence support. In:
analytical processing on ramcloud. In: Proceedings of the 16th 2013 46th annual IEEE/ACM international symposium on micro-
international conference on extending database technology. architecture (MICRO). IEEE, pp 421–432
ACM, pp 454–464 52. Lee S, Kim J, Lee M et al (2014) Last block logging mecha-
33. Li F, Das S, Syamala M et al (2016) Accelerating relational data- nism for improving performance and lifetime on SCM-based file
bases by leveraging remote memory and RDMA. In: Proceedings system. In: Proceedings of the 8th international conference on
of the 2016 international conference on management of data. ubiquitous information management and communication. ACM,
ACM, pp 355–370 p 38
34. Binnig C, Crotty A, Galakatos A et al (2016) The end of slow net- 53. Caulfield AM, De A, Coburn J et al (2010) Moneta: a high-
works: it’s time for a redesign. Proc VLDB Endow 9(7):528–539 performance storage array architecture for next-generation,
35. Elmore AJ, Arora V, Taft R et al (2015) Squall: fine-grained live non-volatile memories. In: Proceedings of the 2010 43rd annual
reconfiguration for partitioned main memory databases. In: Pro- IEEE/ACM international symposium on microarchitecture. IEEE
ceedings of the 2015 ACM SIGMOD International conference Computer Society, pp 385–395
on management of data. ACM, pp 299–313 54. PRAMFS Team (2016) Protected and persistent RAM file system
36. Polychroniou O, Sen R, Ross KA (2014) Track join: distributed [EB/OL]. http://pRamfs​ .Source​ Forge​ .net. Accessed 16 Mar 2018
joins with minimal network traffic. In: Proceedings of the 2014 55. Sha EHM, Chen X, Zhuge Q et al (2016) A new design of in-
ACM SIGMOD international conference on management of data. memory file system based on file virtual address framework.
ACM, pp 1483–1494 IEEE Trans Comput 65(10):2959–2972
37. Kalia A, Kaminsky M, Andersen DG (2014) Using RDMA effi- 56. Fang R, Hsiao HI, He B et al (2011) High performance data-
ciently for key-value services. ACM SIGCOMM Comput Com- base logging using storage class memory. In: 2011 IEEE 27th
mun Rev 44(4):295–306 international conference on data engineering (ICDE). IEEE, pp
38. Dragojević A, Narayanan D, Hodson O et al (2014) FaRM: fast 1221–1231
remote memory. In: Proceedings of the 11th USENIX conference
on networked systems design and implementation, pp 401–414

13
The New Hardware Development Trend and the Challenges in Data Management and Analysis 275

57. Caulfield AM, Mollov TI, Eisner LA et al (2012) Providing safe, 75. Viglas SD (2012) Adapting the B+-tree for asymmetric I/O. In:
user space access to fast, solid state disks. ACM SIGARCH East European conference on advances in databases and informa-
Comput Archit News 40(1):387–400 tion systems. Springer, Berlin, pp 399–412
58. Venkataraman S, Tolia N, Ranganathan P et al (2011) Consist- 76. Chi P, Lee WC, Xie Y (2014) Making B+-tree efficient in PCM-
ent and durable data structures for non-volatile byte-addressable based main memory. In: Proceedings of the 2014 international
memory. FAST 11:61–75 symposium on low power electronics and design. ACM, pp
59. Zhang J, Donofrio D, Shalf J et al (2015) Nvmmu: a non-volatile 69–74
memory management unit for heterogeneous GPU-SSD architec- 77. Bausch D, Petrov I, Buchmann A (2012) Making cost-based
tures. In: 2015 international conference on parallel architecture query optimization asymmetry-aware. In: Proceedings of the
and compilation (PACT). IEEE, pp 13–24 eighth international workshop on data management on new hard-
60. Zhang Y, Zhou X, Zhang Y et al (2016) Virtual denormaliza- ware. ACM, pp 24–32
tion via array index reference for main memory OLAP. IEEE 78. Ailamaki A, DeWitt DJ, Hill MD (2002) Data page layouts for
Trans Knowl Data Eng 28(4):1061–1074 relational databases on deep memory hierarchies. VLDB J Int J
61. Wu S, Jiang D, Ooi BC et al (2010) Efficient B-tree based Very Large Data Bases 11(3):198–215
indexing for cloud data processing. Proc VLDB Endow 79. Lee IH, Lee SG, Shim J (2011) Making T-trees cache conscious
3(1–2):1207–1218 on commodity microprocessors. J Inf Sci Eng 27(1):143–161
62. Wang J, Wu S, Gao H et al (2010) Indexing multi-dimensional 80. Manegold S, Boncz P, Kersten M (2002) Optimizing main-
data in a cloud system. In: Proceedings of the 2010 ACM SIG- memory join on modern hardware. IEEE Trans Knowl Data Eng
MOD international conference on management of data. ACM, 14(4):709–730
pp 591–602 81. Hankins RA, Patel JM (2003) Data morphing: an adaptive,
63. Ding L, Qiao B, Wang G et al (2011) An efficient quad-tree cache-conscious storage technique. In: Proceedings of the 29th
based index structure for cloud data management. In: WAIM, international conference on very large data bases, vol 29. VLDB
pp 238–250 Endowment, pp 417–428
64. Jin R, Cho HJ, Chung TS (2014) A group round robin based 82. Răducanu B, Boncz P, Zukowski M (2013) Micro adaptivity in
B-tree index storage scheme for flash memory devices. In: vectorwise. In: Proceedings of the 2013 ACM SIGMOD interna-
Proceedings of the 8th international conference on ubiquitous tional conference on management of data. ACM, pp 1231–1242
information management and communication. ACM, p 29 83. Johnson R, Raman V, Sidle R et al (2008) Row-wise parallel
65. On ST, Hu H, Li Y et  al (2009) Lazy-update B+-tree for predicate evaluation. Proc VLDB Endow 1(1):622–634
flash devices. In: Tenth international conference on mobile 84. Balkesen C, Teubner J, Alonso G et al (2013) Main-memory hash
data management: systems, services and middleware, 2009, joins on multi-core CPUs: tuning to the underlying hardware. In:
MDM’09. IEEE, pp 323–328 2013 IEEE 29th international conference on data engineering
66. Lomet D (2004) Simple, robust and highly concurrent B-trees (ICDE). IEEE, pp 362–373
with node deletion. In: Proceedings. 20th international confer- 85. Balkesen C, Alonso G, Teubner J et  al (2013) Multi-core,
ence on data engineering. IEEE, pp 18–27 main-memory joins: sort vs. hash revisited. Proc VLDB Endow
67. Levandoski JJ, Lomet DB, Sengupta S (2013) The Bw-tree: a 7(1):85–96
B-tree for new hardware platforms. In: 2013 IEEE 29th inter- 86. He J, Zhang S, He B (2014) In-cache query co-processing on cou-
national conference on data engineering (ICDE). IEEE, pp pled CPU–GPU architectures. Proc VLDB Endow 8(4):329–340
302–313 87. Cheng X, He B, Lu M, et al (2016) Efficient query processing
68. Qureshi MK, Franceschini MM, Lastras-Montano LA (2010) on many-core architectures: a case study with Intel Xeon Phi
Improving read performance of phase change memories via write processor. In: Proceedings of the 2016 international conference
cancellation and write pausing. In: 2010 IEEE 16th international on management of data. ACM, pp 2081–2084
symposium on high performance computer architecture (HPCA). 88. Werner S, Heinrich D, Stelzner M et al (2016) Accelerated join
IEEE, pp 1–11 evaluation in Semantic Web databases by using FPGAs. Concurr
69. Ahn J, Yoo S, Choi K (2014) DASCA: dead write prediction Comput Pract Exp 28(7):2031–2051
assisted STT-RAM cache architecture. In: 2014 IEEE 20th inter- 89. Sitaridi EA, Ross KA (2016) GPU-accelerated string matching
national symposium on high performance computer architecture for database applications. VLDB J 25(5):719–740
(HPCA). IEEE, pp 25–36 90. He J, Lu M, He B (2013) Revisiting co-processing for hash
70. Li J, Shi L, Li Q et al (2013) Cache coherence enabled adaptive joins on the coupled cpu-gpu architecture. Proc VLDB Endow
refresh for volatile STT-RAM. In: Proceedings of the conference 6(10):889–900
on design, automation and test in Europe. EDA consortium, pp 91. Zhang Y, Zhang Y, Su M et al (2013) HG-Bitmap join index: a
1247–1250 hybrid GPU/CPU bitmap join index mechanism for OLAP. In:
71. Ferreira AP, Zhou M, Bock S et al (2010) Increasing PCM main International conference on web information systems engineer-
memory lifetime. In: Proceedings of the conference on design, ing. Springer, Berlin, pp 23–36
automation and test in Europe. European Design and Automation 92. Blanas S, Li Y, Patel JM (2011) Design and evaluation of main
Association, pp 914–919 memory hash join algorithms for multi-core CPUs. In: Proceed-
72. Vamsikrishna MV, Su Z, Tan KL (2012) A write efficient pcm- ings of the 2011 ACM SIGMOD international conference on
aware sort. In: International conference on database and expert management of data. ACM, pp 37–48
systems applications. Springer, Berlin, pp 86–100 93. Albutiu MC, Kemper A, Neumann T (2012) Massively parallel
73. Garg V, Singh A, Haritsa JR (2015) Towards making data- sort-merge joins in main memory multi-core database systems.
base systems PCM-compliant. In: International conference on Proc VLDB Endow 5(10):1064–1075
database and expert systems applications. Springer, Cham, pp 94. Pagh R, Wei Z, Yi K et al (2010) Cache-oblivious hashing. In:
269–284 Proceedings of the twenty-ninth ACM SIGMOD-SIGACT-
74. Chen S, Gibbons PB, Nath S et al (2011) Rethinking database SIGART symposium on principles of database systems. ACM,
algorithms for phase change memory. In: Conference on innova- pp 297–304
tive data systems research, pp 21–31 95. Mitzenmacher M (2016) A new approach to analyzing robin
hood hashing. In: 2016 proceedings of the thirteenth workshop

13

276 W. Pan et al.

on analytic algorithmics and combinatorics (ANALCO). Society 111. Sadoghi M, Ross KA, Canim M et al (2013) Making updates disk-
for Industrial and Applied Mathematics, pp 10–24 I/O friendly using SSDs. Proc VLDB Endow 6(11):997–1008
96. Richter S, Alvarez V, Dittrich J (2015) A seven-dimensional 112. Kallman R, Kimura H, Natkins J et al (2008) H-store: a high-
analysis of hashing methods and its implications on query pro- performance, distributed main memory transaction processing
cessing. Proc VLDB Endow 9(3):96–107 system. Proc VLDB Endow 1(2):1496–1499
97. Schuh S, Chen X, Dittrich J (2016) An experimental comparison 113. Dragojević A, Narayanan D, Nightingale EB et al (2015) No
of thirteen relational equi-joins in main memory. In: Proceedings compromises: distributed transactions with consistency, avail-
of the 2016 international conference on management of data. ability, and performance. In: Proceedings of the 25th symposium
ACM, pp 1961–1976 on operating systems principles. ACM, pp 54–70
98. Mohan C, Haderle D, Lindsay B et al (1992) ARIES: a transac- 114. Levandoski JJ, Lomet DB, Sengupta S et al (2015) High perfor-
tion recovery method supporting fine-granularity locking and mance transactions in deuteronomy. In: CIDR
partial rollbacks using write-ahead logging. ACM Trans Data- 115. Zhenkun Y, Chuanhui Y, Zhen L (2013) OceanBase—a massive
base Syst (TODS) 17(1):94–162 structured data storage management system. E Sci Technol Appl
99. Pelley S, Wenisch TF, Gold BT et al (2013) Storage management 4(1):41–48
in the NVRAM era. Proc VLDB Endow 7(2):121–132 116. Bailis P, Davidson A, Fekete A et  al (2013) Highly avail-
100. Gao S, Xu J, Härder T et al (2015) PCMLogging: optimizing able transactions: virtues and limitations. Proc VLDB Endow
transaction logging and recovery performance with PCM. IEEE 7(3):181–192
Trans Knowl Data Eng 27(12):3332–3346 117. Stonebraker M, Madden S, Abadi DJ et al (2007) The end of
101. Huang J, Schwan K, Qureshi MK (2014) NVRAM-aware logging an architectural era: (it’s time for a complete rewrite). In: Pro-
in transaction systems. Proc VLDB Endow 8(4):389–400 ceedings of the 33rd international conference on very large data
102. Wang T, Johnson R (2014) Scalable logging through emerging bases. VLDB Endowment, pp 1150–1160
non-volatile memory. Proc VLDB Endow 7(10):865–876 118. Pavlo A, Curino C, Zdonik S (2012) Skew-aware automatic data-
103. Harizopoulos S, Abadi DJ, Madden S et al (2008) OLTP through base partitioning in shared-nothing, parallel OLTP systems. In:
the looking glass, and what we found there. In: Proceedings of Proceedings of the 2012 ACM SIGMOD international confer-
the 2008 ACM SIGMOD international conference on manage- ence on management of data. ACM, pp 61–72
ment of data. ACM, pp 981–992 119. NuoDB Team [EB/OL] (2016) NuoDB. http://www.nuodb.​ com/.
104. Larson PÅ, Blanas S, Diaconu C et al (2011) High-performance Accessed 22 Jan 2018
concurrency control mechanisms for main-memory databases. 120. Brantner M, Florescu D, Graf D et al (2008) Building a database
Proc VLDB Endow 5(4):298–309 on S3. In: Proceedings of the 2008 ACM SIGMOD international
105. Johnson R, Pandis I, Ailamaki A (2009) Improving OLTP scal- conference on management of data. ACM, pp 251–264
ability using speculative lock inheritance. Proc VLDB Endow 121. Stonebraker M (2010) SQL databases v. NoSQL databases. Com-
2(1):479–489 mun ACM 53(4):10–11
106. Pandis I, Johnson R, Hardavellas N et al (2010) Data-oriented 122. Özcan F, Tatbul N, Abadi DJ et al (2014) Are we experiencing
transaction execution. Proc VLDB Endow 3(1–2):928–939 a big data bubble? In: Proceedings of the 2014 ACM SIGMOD
107. Johnson R, Athanassoulis M, Stoica R et al (2009) A new look international conference on management of data. ACM, pp
at the roles of spinning and blocking. In: Proceedings of the fifth 1407–1408
international workshop on data management on new hardware. 123. Pavlo A, Aslett M (2016) What’s really new with NewSQL?
ACM, pp 21–26 ACM Sigmod Rec 45(2):45–55
108. Horikawa T (2013) Latch-free data structures for DBMS: design, 124. Krueger J, Kim C, Grund M et al (2011) Fast updates on read-
implementation, and evaluation. In: Proceedings of the 2013 optimized databases using multi-core CPUs. Proc VLDB Endow
ACM SIGMOD international conference on management of data. 5(1):61–72
ACM, pp 409–420 125. Barshai V, Chan Y, Lu H et al (2012) Delivering continuity and
109. Jung H, Han H, Fekete A et al (2014) A scalable lock manager extreme capacity with the IBM DB2 pureScale feature. IBM
for multicores. ACM Trans Database Syst (TODS) 39(4):29 Redbooks, New York
110. Ren K, Thomson A, Abadi DJ (2012) Lightweight locking for 126. Ailamaki A, Liarou E, Tözün P et al (2015) How to stop under-
main memory database systems. In: Proceedings of the VLDB utilization and love multicores. In: 2015 IEEE 31st international
endowment, vol 6, no 2. VLDB Endowment, pp 145–156 conference on data engineering (ICDE). IEEE, pp 1530–1533

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