Data Sheet, Rev. 0.5, Mar.

2005

HYS64D32000HDL–[5/6]–C
HYS64D64020HDL–[5/6]–C

200-Pin Small Outline Dual-In-Line Memory Modules

SO-DIMM
DDR SDRAM
RoHS Compliant Products

Memory Products

N e v e r s t o p t h i n k i n g .
Edition 2005-03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.

Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.

Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).

Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
 Data Sheet, Rev. 0.5, Mar. 2005

HYS64D32000HDL–[5/6]–C
HYS64D64020HDL–[5/6]–C

200-Pin Small Outline Dual-In-Line Memory Modules

SO-DIMM
DDR SDRAM
RoHS Compliant Products

Memory Products

N e v e r s t o p t h i n k i n g .
HYS64D32000HDL–[5/6]–C, HYS64D64020HDL–[5/6]–C
Preliminary
Revision History: Rev. 0.5 2005-03
Previous Version:
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Template: mp_a4_v2.0_2003-06-06.fm
 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary

Table of Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Data Sheet 5 Rev. 0.5, 2005-03

Preliminary

200-Pin Small Outline Dual-In-Line Memory Modules HYS64D32000HDL–[5/6]–C

SO-DIMM HYS64D64020HDL–[5/6]–C

1 Overview

1.1 Features
• Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules
• One rank 32M ×64 and two ranks 64M ×64 organization
• Standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
• Single +2.5 V (± 0.2 V) power supply and +2.6 V (± 0.1 V) for DDR400
• Built with 512 Mbit DDR SDRAMs organized as ×16 in P–TSOPII–66 packages
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Serial Presence Detect with E2PROM
• Standard form factor: 67.60 mm × 31.75 mm × 3.80 mm
• Standard reference layout Raw Cards A and C
• Gold plated contacts
• RoHS Compliant Products1)

Table 1 Performance
Part Number Speed Code –5 –6 Unit
Speed Grade Component DDR400B DDR333B —
Module PC3200–3033 PC2700–2533 —
max. Clock @CL3 fCK3 200 166 MHz
Frequency @CL2.5 fCK2.5 166 166 MHz
@CL2 fCK2 133 133 MHz

1.2 Description
The HYS64D32000HDL–[5/6]–C and HYS64D64020HDL–[5/6]–C are industry standard 200-Pin Small Outline
Dual-In-Line Memory Modules (SO-DIMMs) organized as 64M ×64. The memory array is designed with Double
Data Rate Synchronous DRAMs (DDR SDRAM). A variety of de coupling capacitors are mounted on the PC
board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol.
The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the
customer.

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.

Data Sheet 1 Rev. 0.5, 2005-03

07122004-E7F5-5R65
 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Overview

Table 2 Ordering Information for Lead-Free(RoHS Compliant Products)

Product Type1) Compliance Code2) Description SDRAM Technology
PC3200 (CL=3.0)
HYS64D32000HDL–5–C PC3200S-3033–1–C0 One rank 256MB SO-DIMM 512 MBit (×16)
HYS64D64020HDL–5–C PC3200S-3033–1–A0 Two ranks 512MB SO-DIMM 512 MBit (×16)
PC2700 (CL=2.5)
HYS64D32000HDL–6–C PC2700S–2533–1–C0 One rank 256MB SO-DIMM 512 MBit (×16)
HYS64D64020HDL–6–C PC2700S-2533–1–A0 Two ranks 512MB SO-DIMM 512 MBit (×16)
1) All product types end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS64D64020GDL–5–B, indicating Rev.B die are used for SDRAM components.
2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC3200”), the latencies
(for example “30330” means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Pre-charge
latency of 3 clocks), JEDEC SPD code definition version 1, and the Raw Card used for this module.

Data Sheet 2 Rev. 0.5, 2005-03

07122004-E7F5-5R65
 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Pin Configuration

2 Pin Configuration
The pin configuration of the Unbuffered Small Outline Table 3 Pin Configuration of SO-DIMM (cont’d)
DDR SDRAM DIMM is listed by function in Table 3 Pin# Name Pin Buffer Function
(200 pins). The abbreviations used in columns Pin and Type Type
Buffer Type are explained in Table 4 and Table 5
respectively. The pin numbering is depicted in 112 A0 I SSTL Address Bus 11:0
Figure 1. 111 A1 I SSTL
110 A2 I SSTL
Table 3 Pin Configuration of SO-DIMM 109 A3 I SSTL
Pin# Name Pin Buffer Function 108 A4 I SSTL
Type Type
107 A5 I SSTL
Clock Signals
106 A6 I SSTL
35 CK0 I SSTL Clock Signal
105 A7 I SSTL
160 CK1 I SSTL Clock Signal
102 A8 I SSTL
89 CK2 I SSTL Clock Signal
101 A9 I SSTL
Note: ECC type
115 A10 I SSTL
module
AP I SSTL
NC NC – Note: non-ECC type
module 100 A11 I SSTL
37 CK0 I SSTL Complement Clock 99 A12 I SSTL Address Signal 12
158 CK1 I SSTL Complement Clock Note: Module based
on 256 Mbit or
91 CK2 I SSTL Complement Clock
larger dies
Note: ECC type
NC NC – Note: 128 Mbit based
module
module
NC NC – Note: non-ECC type
123 A13 I SSTL Address Signal 13
module
Note: 1 Gbit based
96 CKE0 I SSTL Clock Enable Rank 0
module
95 CKE1 I SSTL Clock Enable Rank 1
NC NC – Note: Module based
Note: 2-rank module on 512 Mbit or
NC NC – Note: 1-rank module smaller dies
Control Signals Data Signals
121 S0 I SSTL Chip Select Rank 0 5 DQ0 I/O SSTL Data Bus 63:0
122 S1 I SSTL Chip Select Rank 1 7 DQ1 I/O SSTL
Note: 2-ranks module 13 DQ2 I/O SSTL
NC NC – Note: 1-rank module 17 DQ3 I/O SSTL
118 RAS I SSTL Row Address 6 DQ4 I/O SSTL
Strobe 8 DQ5 I/O SSTL
120 CAS I SSTL Column Address 14 DQ6 I/O SSTL
Strobe
18 DQ7 I/O SSTL
119 WE I SSTL Write Enable
19 DQ8 I/O SSTL
Address Signals
23 DQ9 I/O SSTL
117 BA0 I SSTL Bank Address Bus
29 DQ10 I/O SSTL
116 BA1 I SSTL 1:0
31 DQ11 I/O SSTL
20 DQ12 I/O SSTL
24 DQ13 I/O SSTL

Data Sheet 8 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Pin Configuration

Table 3 Pin Configuration of SO-DIMM (cont’d) Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin Buffer Function Pin# Name Pin Buffer Function
Type Type Type Type
30 DQ14 I/O SSTL Data Bus 63:0 172 DQ54 I/O SSTL Data Bus 63:0
32 DQ15 I/O SSTL 176 DQ55 I/O SSTL
41 DQ16 I/O SSTL 177 DQ56 I/O SSTL
43 DQ17 I/O SSTL 181 DQ57 I/O SSTL
49 DQ18 I/O SSTL 187 DQ58 I/O SSTL
53 DQ19 I/O SSTL 189 DQ59 I/O SSTL
42 DQ20 I/O SSTL 178 DQ60 I/O SSTL
44 DQ21 I/O SSTL 182 DQ61 I/O SSTL
50 DQ22 I/O SSTL 188 DQ62 I/O SSTL
54 DQ23 I/O SSTL 190 DQ63 I/O SSTL
55 DQ24 I/O SSTL 71 CB0 I/O SSTL Check Bit 0
59 DQ25 I/O SSTL Note: ECC type
65 DQ26 I/O SSTL module
67 DQ27 I/O SSTL NC NC – Note: Non-ECC
module
56 DQ28 I/O SSTL
73 CB1 I/O SSTL Check Bit 1
60 DQ29 I/O SSTL
Note: ECC type
66 DQ30 I/O SSTL module
68 DQ31 I/O SSTL NC NC – Note: Non-ECC
127 DQ32 I/O SSTL module
129 DQ33 I/O SSTL 79 CB2 I/O SSTL Check Bit 2
135 DQ34 I/O SSTL Note: ECC type
139 DQ35 I/O SSTL module
128 DQ36 I/O SSTL NC NC – Note: Non-ECC
module
130 DQ37 I/O SSTL
83 CB3 I/O SSTL Check Bit 3
136 DQ38 I/O SSTL
Note: ECC type
140 DQ39 I/O SSTL module
141 DQ40 I/O SSTL NC NC – Note: Non-ECC
145 DQ41 I/O SSTL module
151 DQ42 I/O SSTL 72 CB4 I/O SSTL Check Bit 4
153 DQ43 I/O SSTL Note: ECC type
142 DQ44 I/O SSTL module
146 DQ45 I/O SSTL NC NC – Note: Non-ECC
module
152 DQ46 I/O SSTL
74 CB5 I/O SSTL Check Bit 5
154 DQ47 I/O SSTL
Note: ECC type
163 DQ48 I/O SSTL
module
165 DQ49 I/O SSTL NC NC – Note: Non-ECC
171 DQ50 I/O SSTL module
175 DQ51 I/O SSTL
164 DQ52 I/O SSTL
166 DQ53 I/O SSTL

Data Sheet 9 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Pin Configuration

Table 3 Pin Configuration of SO-DIMM (cont’d) Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin Buffer Function Pin# Name Pin Buffer Function
Type Type Type Type
80 CB6 I/O SSTL Check Bit 6 Power Supplies
Note: ECC type 1,2 VREF AI – I/O Reference
module Voltage
NC NC – Note: Non-ECC 197 VDDSPD PWR – EEPROM Power
module Supply
84 CB7 I/O SSTL Check Bit 7 9,10, VDD PWR – Power Supply
Note: ECC type 21,
module 22,
33,
NC NC – Note: Non-ECC
34,
module
36,
11 DQS0 I/O SSTL Data Strobes 7:0 45,
25 DQS1 I/O SSTL Note: See block 46,
47 DQS2 I/O SSTL diagram for 57,
corresponding 58,
61 DQS3 I/O SSTL DQ signals 69,
133 DQS4 I/O SSTL 70,
147 DQS5 I/O SSTL 81,
82,
169 DQS6 I/O SSTL
92,
183 DQS7 I/O SSTL 93,
77 DQS8 I/O SSTL Data Strobe 8 94,
Note: ECC type 113,
module 114,
131,
NC NC – Note: Non-ECC 132,
module 143,
12 DM0 I SSTL Data Mask 7:0 144,
26 DM1 I SSTL 155,
156,
48 DM2 I SSTL
157,
62 DM3 I SSTL 167,
134 DM4 I SSTL 168,
148 DM5 I SSTL 179,
180,
170 DM6 I SSTL 191,
184 DM7 I SSTL 192
78 DM8 I SSTL Data Mask 8
Note: ECC type
module
NC NC – Note: Non-ECC
module
EEPROM
195 SCL I CMOS Serial Bus Clock
193 SDA I/O OD Serial Bus Data
194 SA0 I CMOS Slave Address
196 SA1 I CMOS Select Bus 2:0
198 SA2 I CMOS

Data Sheet 10 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Pin Configuration

Table 3 Pin Configuration of SO-DIMM (cont’d) Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin Buffer Function Pin# Name Pin Buffer Function
Type Type Type Type
3,4, VSS GND – Ground Plane 85, NC NC – Not connected
15, 86, Note: Pins not
16, 97, connected on
27, 98, Infineon SO
28, 124, DIMMs
38, 200
39,
40,
51, Table 4 Abbreviations for Pin Type
52,
63, Abbreviation Description
64, I Standard input-only pin. Digital levels.
75, O Output. Digital levels.
76, I/O I/O is a bidirectional input/output signal.
87,
AI Input. Analog levels.
88,
90, PWR Power
103, GND Ground
104, NC Not Connected
125,
126,
137, Table 5 Abbreviations for Buffer Type
138, Abbreviation Description
149, SSTL Serial Stub Terminated Logic (SSTL2)
150,
LV-CMOS Low Voltage CMOS
159,
161, CMOS CMOS Levels
162, OD Open Drain. The corresponding pin has 2
173, operational states, active low and tristate,
174, and allows multiple devices to share as a
185, wire-OR.
186
Other Pins
199 VDDID O OD VDD Identification
Note: Pin in tristate,
indicating VDD
and VDDQ nets
connected on
PCB

Data Sheet 11 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Pin Configuration

VREF - Pin 001 Pin 002 - VREF

VSS - Pin 003 Pin 004 - VSS
DQ0 - Pin 005 Pin 006 - DQ4
DQ1 - Pin 007 Pin 008 - DQ6
VDD - Pin 009 Pin 010 - VDD
DQS0 - Pin 011 Pin 012 - DM0
DQ2 - Pin 013 Pin 014 - DQ6
VSS - Pin 015 Pin 016 - VSS
DQ3 - Pin 017 Pin 018 - DQ7
DQ8 - Pin 019 Pin 020 - DQ12
VDD - Pin 021 Pin 022 - VDD
DQ09 - Pin 023 Pin 024 - DQ13
DQS1 - Pin 025 Pin 026 - DM1
VSS - Pin 027 Pin 028 - VSS
DQ10 - Pin 029 Pin 030 - DQ14
DQ11 - Pin 031 Pin 032 - DQ15
VDD - Pin 033 Pin 034 - VDD
CK0 - Pin 035 Pin 036 - VDD
CK0 - Pin 037 Pin 038 - VSS
VSS - Pin 039 Pin 040 - VSS

DQ16 - Pin 041 Pin 042 - DQ20

DQ17 - Pin 043 Pin 044 - DQ21
VDD - Pin 045 Pin 046 - VDD

FRONTSIDE
DQS2 - Pin 047 Pin 048 - DM2

BACKSIDE
DQ18 - Pin 049 VSS - Pin 051 Pin 050 - DQ22
Pin 052 - VSS
DQ19 - Pin 053 Pin 054 - DQ23
DQ33 - Pin 055 Pin 056 - DQ28
VDD - Pin 057 Pin 058 - VDD
DQ25 - Pin 059 Pin 060 - DQ29
DQS3 - Pin 061 VSS - Pin 063 Pin 062 - DM3
Pin 064 - VSS
DQ26 - Pin 065 Pin 066 - DQ30
DQ27 - Pin 067 Pin 068 - DQ31
VDD - Pin 069 Pin 070 - VDD
CB0/NC - Pin 071 Pin 072 - CB4/NC
CB1/NC - Pin 073 VSS - Pin 075 Pin 074 - CB5/NC
Pin 076 - VSS
DQS8/NC - Pin 077 Pin 078 - DM8/NC
CB2/NC - Pin 079 Pin 080 - CB6/NC
VDD - Pin 081 Pin 082 - VDD
CB3/NC - Pin 083 Pin 084 - CB7/NC
NC - Pin 085 VSS - Pin 087 Pin 086 - NC
Pin 088 - VSS
CK2/NC - Pin 089 Pin 090 - VSS
CK2/NC - Pin 091 Pin 092 - VDD
VDD - Pin 093 Pin 094 - VDD
CKE1/NC - Pin 095 Pin 096 - CKE0
NC - Pin 097 Pin 098 - NC
A12/NC - Pin 099 Pin 100 - A11
A9 - Pin 101 VSS - Pin 103 Pin 102 - A8
Pin 104 - VSS
A7 - Pin 105 Pin 106 - A6
A5 - Pin 107 Pin 108 - A4
A3 - Pin 109 Pin 110 - A2
A1 - Pin 111 Pin 112 - A0
VDD - Pin 113 Pin 114 - VDD
A10/AP - Pin 115 Pin 116 - BA1
BA0 - Pin 117 Pin 118 - RAS
WE - Pin 119 Pin 120 - CAS
S0 - Pin 121 Pin 122 - S1/NC
A13/NC - Pin 123 Pin 124 - NC
VSS - Pin 125 Pin 126 - VSS
DQ32 - Pin 127 Pin 128 - DQ36
DQ33 - Pin 129 VDD - Pin 131 Pin 130 - DQ37
Pin 132 - VDD
DQS4 - Pin 133 Pin 134 - DM4
DQ34 - Pin 135 Pin 136 - DQ38
VSS - Pin 137 Pin 138 - VSS
DQ35 - Pin 139 Pin 140 - DQ39
DQ40 - Pin 141 VDD - Pin 143 Pin 142 - DQ44
Pin 144 - VDD
DQ41 - Pin 145 Pin 146 - DQ45
VSS - DQS5 - Pin 147 Pin 148 - DM5 VSS
Pin 149 Pin 150 -
DQ42 - Pin 151 Pin 152 - DQ46
DQ43 - Pin 153 VDD - Pin 155 Pin 154 - DQ47
Pin 156 - VDD
VDD - Pin 157 VSS - Pin 159 Pin 158 - CK1
Pin 160 - CK1
VSS - Pin 161 Pin 162 - VSS
DQ48 - Pin 163 Pin 164 - DQ52
DQ49 - Pin 165 VDD - Pin 167 Pin 166 - DQ53
Pin 168 - VDD
DQS6 - Pin 169 Pin 170 - DM6
DQ50 - Pin 171 Pin 172 - DQ54
VSS - Pin 173 Pin 174 - VSS
DQ51 - Pin 175 Pin 176 - DQ55
DQ56 - Pin 177 VDD - Pin 179 Pin 178 - DQ60
Pin 180 - VDD
DQ57 - Pin 181 Pin 182 - DQ61
DQS7 - Pin 183 Pin 184 - DM7
VSS - Pin 185 Pin 186 - VSS
DQ58 - Pin 187 Pin 188 - DQ62
DQ59 - Pin 189 VDD - Pin 191 VDD Pin 190 - DQ63
Pin 192 -
SDA - Pin 193 Pin 194 - SA0
SCL - Pin 195 Pin 196 - SA1
VDDSPD - Pin 197 Pin 198 - SA2
VDDID - Pin 199 Pin 200 - NC

MPPD0040
Figure 1 Pin Configuration Diagram 200-Pin SO-DIMM

Table 6 Address Format

Density Organization Memory SDRAMs # of # of row/bank/ Refresh Period Interval
Ranks SDRAMs columns bits
256MB 32M ×64 1 32M ×16 4 13/2/10 8K 64 ms 7.8 µs
512MB 64M ×64 2 32M ×16 8 13/2/10 8K 64 ms 7.8 µs

Data Sheet 12 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Pin Configuration

9''63'
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6$ $ '4 ,2
6$ $ '4 ,2
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'4 ,2
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'4 ,2
'4 ,2
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'46 8'46
'4 ,2
'4 ,2
'4 ,2
'4 ,2
'4 ,2
'4 ,2
'4 ,2
'4 ,2
03%'

Figure 2 Block Diagram SO-DIMM Raw Card C ×64 1 Rank ×16

Notes
1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 Ω ±5 %

Data Sheet 13 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Pin Configuration

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#3 #3 #3 #3
$- ,$- ,$- $- ,$- ,$-
$13 ,$1 3 ,$1 3 $13 ,$1 3 ,$1 3
$1  )/ )/ $1  )/ )/
$1  )/ )/ $1  )/ )/
$1  )/ )/ $1  )/ )/
$1  )/ )/ $1  )/ )/
$1  )/ )/ $1  )/ )/
$1  )/ )/ $1  )/ )/
$1  )/ )/ $1  )/ )/
$1  )/ )/ $1  )/ )/
$- 5$ - 5$ - $- 5$ - 5$ -
$13 5$ 1 3 5$ 1 3 $13 5$ 1 3 5$ 1 3
$1  )/ )/ $1  )/ )/
$1  )/ )/ $1  )/ )/
$1  )/ )/ $1  )/  )/
$1  )/ )/ $1  )/  )/
$1  )/ )/ $1  )/  )/
$1  )/ )/ $1  )/  )/
$1  )/ )/ $1  )/  )/
$1  )/ )/ -0"$

$1  )/  )/

Figure 3 Block Diagram SO-DIMM Raw Card A ×64 2 Ranks ×16

Note:
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 Ω ±5%

Data Sheet 14 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Electrical Characteristics

3 Electrical Characteristics

3.1 Operating Conditions

Absolute Maximum Ratings

Parameter Symbol Values Unit Note/ Test Condition
min. typ. max.
Voltage on I/O pins relative to VSS VIN, VOUT –0.5 – VDDQ +0.5 V –
Voltage on inputs relative to VSS VIN –1 – +3.6 V –
Voltage on VDD supply relative to VSS VDD –1 – +3.6 V –
Voltage on VDDQ supply relative to VSS VDDQ –1 – +3.6 V –
Operating temperature (ambient) TA 0 – +70 °C –
Storage temperature (plastic) TSTG -55 – +150 °C –
Power dissipation (per SDRAM component) PD – 1 – W –
Short circuit output current IOUT – 50 – mA –

Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.

Electrical Characteristics and DC Operating Conditions

Parameter Symbol Values Unit Note/Test Condition 1)
Min. Typ. Max.
Device Supply Voltage VDD 2.3 2.5 2.7 V fCK ≤ 166 MHz
Device Supply Voltage VDD 2.5 2.6 2.7 V fCK > 166 MHz 2)
Output Supply Voltage VDDQ 2.3 2.5 2.7 V fCK ≤ 166 MHz 3)
Output Supply Voltage VDDQ 2.5 2.6 2.7 V fCK > 166 MHz 2)3)
EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V —
Supply Voltage, I/O Supply VSS, 0 0 V —
Voltage VSSQ
Input Reference Voltage VREF 0.49 × 0.5 × 0.51 × V 4)
VDDQ VDDQ VDDQ
5)
I/O Termination Voltage VTT VREF – 0.04 VREF + 0.04 V
(System)
6)
Input High (Logic1) Voltage VIH(DC) VREF + 0.15 VDDQ + 0.3 V
Input Low (Logic0) Voltage VIL(DC) –0.3 VREF – 0.15 V 6)
6)
Input Voltage Level, VIN(DC) –0.3 VDDQ + 0.3 V
CK and CK Inputs
6)7)
Input Differential Voltage, VID(DC) 0.36 VDDQ + 0.6 V
CK and CK Inputs
VI-Matching Pull-up VIRatio 0.71 1.4 — 8)
Current to Pull-down
Current

Data Sheet 15 Rev. 0.5, 2005-03

07122004-E7F5-5R65
 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Electrical Characteristics

Electrical Characteristics and DC Operating Conditions (cont’d)

Parameter Symbol Values Unit Note/Test Condition 1)
Min. Typ. Max.
Input Leakage Current II –2 2 µA Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 9)
Output Leakage Current IOZ –5 5 µA DQs are disabled;
0 V ≤ VOUT ≤ VDDQ 9)
Output High Current, IOH — –16.2 mA VOUT = 1.95 V
Normal Strength Driver
Output Low IOL 16.2 — mA VOUT = 0.35 V
Current, Normal Strength
Driver
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V; VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400);
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD.
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
6) Inputs are not recognized as valid until VREF stabilizes.
7) VID is the magnitude of the difference between the input level on CK and the input level on CK.
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
9) Values are shown per pin.

Data Sheet 16 Rev. 0.5, 2005-03

07122004-E7F5-5R65
 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Electrical Characteristics

3.2 Current Specification and Conditions

Table 7 IDD Conditions

Parameter Symbol
Operating Current 0 IDD0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1 IDD1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current IDD2P
all banks idle; power-down mode; CKE ≤ VIL,MAX
Precharge Floating Standby Current IDD2F
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
Active Power-Down Standby Current IDD3P
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
Active Standby Current IDD3N
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
Operating Current Read IDD4R
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
Operating Current Write IDD4W
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current IDD5
tRC = tRFCMIN, burst refresh
Self-Refresh Current IDD6
CKE ≤ 0.2 V; external clock on
Operating Current 7 IDD7
four bank interleaving with Burst Length = 4; see component data sheet.

Data Sheet 17 Rev. 0.5, 2005-03

07122004-E7F5-5R65
 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Electrical Characteristics

Table 8 IDD Specification for HYS64D[32/64]0x0HDL–5–C

Product Type HYS64D32000HDL–5–C HYS64D64020HDL–5–C Unit Note 1)2)
Organization 256MB 512MB
×64 ×64
1 Rank 2 Ranks
–5 –5
Symbol Typ. Max. Typ. Max.
3)
IDD0 300 360 450 540 mA
IDD1 360 440 510 620 mA 3)4)
5)
IDD2P 5 19 9 37 mA
5)
IDD2F 100 120 200 240 mA
IDD2Q 70 90 140 190 mA 5)
5)
IDD3P 50 60 90 120 mA
5)
IDD3N 150 180 300 360 mA
3)4)
IDD4R 440 540 590 720 mA
3)
IDD4W 460 540 610 720 mA
IDD5 580 760 730 940 mA 3)
5)
IDD6 – 12 – 24 mA
3)4)
IDD7 840 1000 990 1180 mA
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]

Data Sheet 18 Rev. 0.5, 2005-03

07122004-E7F5-5R65
 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Electrical Characteristics

Table 9 IDD Specification HYS64D[32/64]0x0HDL–6–C

Product Type HYS64D32000HDL–6–C HYS64D64020HDL–6–C Unit Note 1)2)
Organization 256MB 512MB
×64 ×64
1 Rank 2 Ranks
–6 –6
Symbol Typ. Max. Typ. Max.
3)
IDD0 280 340 410 500 mA
IDD1 320 380 450 540 mA 3)4)
5)
IDD2P 5 18 9 37 mA
5)
IDD2F 80 100 170 200 mA
IDD2Q 60 90 120 170 mA 5)
5)
IDD3P 40 60 90 120 mA
5)
IDD3N 130 160 270 320 mA
IDD4R 380 460 510 620 mA 3)4)
3)
IDD4W 400 480 530 640 mA
IDD5 520 700 650 860 mA 3)
5)
IDD6 – 12 – 24 mA
3)4)
IDD7 760 920 890 1080 mA
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]

Data Sheet 19 Rev. 0.5, 2005-03

07122004-E7F5-5R65
 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Electrical Characteristics

3.3 AC Characteristics

AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter Symbol –5 –6 Unit Note/ Test
DDR400B DDR333 Condition 1)
Min. Max. Min. Max.
2)3)4)5)
DQ output access time from tAC –0.7 +0.5 –0.7 +0.7 ns
CK/CK
2)3)4)5)
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK
Clock cycle time tCK 5 8 6 12 ns CL = 3.0
2)3)4)5)

6 12 6 12 ns CL = 2.5
2)3)4)5)

7.5 12 7.5 12 ns CL = 2.0

2)3)4)5)

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 2)3)4)5)

2)3)4)5)6)
Auto precharge write recovery tDAL (tWR/tCK) + (tRP/tCK) tCK
+ precharge time
DQ and DM input hold time tDH 0.4 — 0.45 — ns 2)3)4)5)
2)3)4)5)6)
DQ and DM input pulse width tDIPW 1.75 — 1.75 — ns
(each input)
2)3)4)5)
DQS output access time from tDQSCK –0.5 +0.5 –0.6 +0.6 ns
CK/CK
DQS input low (high) pulse tDQSL,H 0.35 — 0.35 — tCK 2)3)4)5)
width (write cycle)
DQS-DQ skew (DQS and tDQSQ — +0.40 — +0.45 ns TSOPII
2)3)4)5)
associated DQ signals)
Write command to 1st DQS tDQSS 0.72 1.25 0.75 1.25 tCK 2)3)4)5)

latching transition
DQ and DM input setup time tDS 0.4 — 0.45 — ns 2)3)4)5)
2)3)4)5)
DQS falling edge hold time tDSH 0.2 — 0.2 — tCK
from CK (write cycle)
2)3)4)5)
DQS falling edge to CK setup tDSS 0.2 — 0.2 — tCK
time (write cycle)
Clock Half Period tHP min. (tCL, tCH) — min. (tCL, tCH) — ns 2)3)4)5)
2)3)4)5)7)
Data-out high-impedance time tHZ +0.7 –0.7 +0.7 ns
from CK/CK
Address and control input hold tIH 0.6 — 0.75 — ns fast slew rate
3)4)5)6)8)
time
0.7 — 0.8 — ns slow slew
rate
3)4)5)6)8)
2)3)4)5)9)
Control and Addr. input pulse tIPW 2.2 — 2.2 — ns
width (each input)

Data Sheet 20 Rev. 0.5, 2005-03

07122004-E7F5-5R65
 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Electrical Characteristics

AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter Symbol –5 –6 Unit Note/ Test
DDR400B DDR333 Condition 1)
Min. Max. Min. Max.
Address and control input tIS 0.6 — 0.75 — ns fast slew rate
setup time 3)4)5)6)10)

0.7 — 0.8 — ns slow slew

rate
3)4)5)6)10)
2)3)4)5)7)
Data-out low-impedance time tLZ –0.7 +0.7 –0.7 +0.7 ns
from CK/CK
Mode register set command tMRD 2 — 2 — tCK 2)3)4)5)
cycle time
2)3)4)5)
DQ/DQS output hold time tQH tHP – tQHS — tHP – tQHS — ns
Data hold skew factor tQHS — +0.50 — +0.55 ns TSOPII
2)3)4)5)

Active to Autoprecharge delay tRAP tRCD or tRASmin — tRCD or tRASmin — ns 2)3)4)5)

2)3)4)5)
Active to Precharge command tRAS 40 70E+3 42 70E+3 ns
Active to Active/Auto-refresh tRC 55 — 60 — ns 2)3)4)5)
command period
2)3)4)5)
Active to Read or Write delay tRCD 15 — 18 — ns
2)3)4)5)8)
Average Periodic Refresh tREFI — 7.8 — 7.8 µs
Interval
Auto-refresh to Active/Auto- tRFC 70 — 72 — ns 2)3)4)5)
refresh command period
2)3)4)5)
Precharge command period tRP 15 — 18 — ns
2)3)4)5)
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK
Read postamble tRPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5)
2)3)4)5)
Active bank A to Active bank B tRRD 10 — 12 — ns
command
2)3)4)5)
Write preamble tWPRE 0.25 — 0.25 — tCK
Write preamble setup time tWPRES 0 — 0 — ns 2)3)4)5)11)
2)3)4)5)12)
Write postamble tWPST 0.40 0.60 0.40 0.60 tCK
2)3)4)5)
Write recovery time tWR 15 — 15 — ns
Internal write to read tWTR 2 — 1 — tCK 2)3)4)5)
command delay
2)3)4)5)
Exit self-refresh to non-read tXSNR 75 — 75 — ns
command
2)3)4)5)
Exit self-refresh to read tXSRD 200 — 200 — tCK
command
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.

Data Sheet 21 Rev. 0.5, 2005-03

07122004-E7F5-5R65
 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Electrical Characteristics

6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between VOH(ac) and VOL(ac).
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.

Data Sheet 22 Rev. 0.5, 2005-03

07122004-E7F5-5R65
 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary SPD Contents

4 SPD Contents

Table 10 SPD Codes for HYS64D[32/64][000/020]HDL–5–C

Product Type HYS64D32000HDL–5–C HYS64D64020HDL–5–C
Organization 256 MB 512 MB
×64 ×64
1 Rank (×16) 2 Ranks (×16)
Label Code PC3200S–3033–1 PC3200S–3033–1
JEDEC SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80
1 Total number of Bytes in E2PROM 08 08
2 Memory Type (DDR = 07h) 07 07
3 Number of Row Addresses 0D 0D
4 Number of Column Addresses 0A 0A
5 Number of DIMM Ranks 01 02
6 Data Width (LSB) 40 40
7 Data Width (MSB) 00 00
8 Interface Voltage Levels 04 04
9 tCK @ CLmax (Byte 18) [ns] 50 50
10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70
11 Error Correction Support 00 00
12 Refresh Rate 82 82
13 Primary SDRAM Width 10 10
14 Error Checking SDRAM Width 00 00
15 tCCD [cycles] 01 01
16 Burst Length Supported 0E 0E
17 Number of Banks on SDRAM Device 04 04
18 CAS Latency 1C 1C
19 CS Latency 01 01
20 Write Latency 02 02
21 DIMM Attributes 20 20
22 Component Attributes C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60
24 tAC SDRAM @ CLmax -0.5 [ns] 70 70
25 tCK @ CLmax -1 (Byte 18) [ns] 75 75
26 tAC SDRAM @ CLmax -1 [ns] 70 70
27 tRPmin [ns] 3C 3C
28 tRRDmin [ns] 28 28
29 tRCDmin [ns] 3C 3C
30 tRASmin [ns] 28 28
31 Module Density per Rank 40 40
32 tAS, tCS [ns] 60 60

Data Sheet 23 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary SPD Contents

Table 10 SPD Codes for HYS64D[32/64][000/020]HDL–5–C (cont’d)

Product Type HYS64D32000HDL–5–C HYS64D64020HDL–5–C
Organization 256 MB 512 MB
×64 ×64
1 Rank (×16) 2 Ranks (×16)
Label Code PC3200S–3033–1 PC3200S–3033–1
JEDEC SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
33 tAH, tCH [ns] 60 60
34 tDS [ns] 40 40
35 tDH [ns] 40 40
36 - 40 not used 00 00
41 tRCmin [ns] 37 37
42 tRFCmin [ns] 41 41
43 tCKmax [ns] 28 28
44 tDQSQmax [ns] 28 28
45 tQHSmax [ns] 50 50
46 not used 00 00
47 DIMM PCB Height 01 01
48 - 61 not used 00 00
62 SPD Revision 10 10
63 Checksum of Byte 0-62 76 77
64 JEDEC ID Code of Infineon (1) C1 C1
65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00
72 Module Manufacturer Location xx xx
73 Part Number, Char 1 36 36
74 Part Number, Char 2 34 34
75 Part Number, Char 3 44 44
76 Part Number, Char 4 33 36
77 Part Number, Char 5 32 34
78 Part Number, Char 6 30 30
79 Part Number, Char 7 30 32
80 Part Number, Char 8 30 30
81 Part Number, Char 9 48 48
82 Part Number, Char 10 44 44
83 Part Number, Char 11 4C 4C
84 Part Number, Char 12 35 35
85 Part Number, Char 13 43 43
86 Part Number, Char 14 20 20
87 Part Number, Char 15 20 20
88 Part Number, Char 16 20 20
89 Part Number, Char 17 20 20
90 Part Number, Char 18 20 20

Data Sheet 24 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary SPD Contents

Table 10 SPD Codes for HYS64D[32/64][000/020]HDL–5–C (cont’d)

Product Type HYS64D32000HDL–5–C HYS64D64020HDL–5–C
Organization 256 MB 512 MB
×64 ×64
1 Rank (×16) 2 Ranks (×16)
Label Code PC3200S–3033–1 PC3200S–3033–1
JEDEC SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
91 Module Revision Code 0x 0x
92 Test Program Revision Code xx xx
93 Module Manufacturing Date Year xx xx
94 Module Manufacturing Date Week xx xx
95 - 98 Module Serial Number (1 - 4) xx xx
99 - 127 not used 00 00

Data Sheet 25 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary SPD Contents

Table 11 SPD Codes for HYS64D[32/64][000/020]HDL–6–C

Product Type HYS64D32000HDL–6–C HYS64D64020HDL–6–C
Organization 256 MB 512 MB
×64 ×64
1 Rank (×16) 2 Ranks (×16)
Label Code PC2700S–2533–1 PC2700S–2533–1
JEDEC SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80
1 Total number of Bytes in E2PROM 08 08
2 Memory Type (DDR = 07h) 07 07
3 Number of Row Addresses 0D 0D
4 Number of Column Addresses 0A 0A
5 Number of DIMM Ranks 01 02
6 Data Width (LSB) 40 40
7 Data Width (MSB) 00 00
8 Interface Voltage Levels 04 04
9 tCK @ CLmax (Byte 18) [ns] 60 60
10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70
11 Error Correction Support 00 00
12 Refresh Rate 82 82
13 Primary SDRAM Width 10 10
14 Error Checking SDRAM Width 00 00
15 tCCD [cycles] 01 01
16 Burst Length Supported 0E 0E
17 Number of Banks on SDRAM Device 04 04
18 CAS Latency 0C 0C
19 CS Latency 01 01
20 Write Latency 02 02
21 DIMM Attributes 20 20
22 Component Attributes C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 70 70
25 tCK @ CLmax -1 (Byte 18) [ns] 00 00
26 tAC SDRAM @ CLmax -1 [ns] 00 00
27 tRPmin [ns] 48 48
28 tRRDmin [ns] 30 30
29 tRCDmin [ns] 48 48
30 tRASmin [ns] 2A 2A
31 Module Density per Rank 40 40
32 tAS, tCS [ns] 75 75
33 tAH, tCH [ns] 75 75

Data Sheet 26 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary SPD Contents

Table 11 SPD Codes for HYS64D[32/64][000/020]HDL–6–C (cont’d)

Product Type HYS64D32000HDL–6–C HYS64D64020HDL–6–C
Organization 256 MB 512 MB
×64 ×64
1 Rank (×16) 2 Ranks (×16)
Label Code PC2700S–2533–1 PC2700S–2533–1
JEDEC SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
34 tDS [ns] 45 45
35 tDH [ns] 45 45
36 - 40 not used 00 00
41 tRCmin [ns] 3C 3C
42 tRFCmin [ns] 48 48
43 tCKmax [ns] 30 30
44 tDQSQmax [ns] 2D 2D
45 tQHSmax [ns] 55 55
46 not used 00 00
47 DIMM PCB Height 01 01
48 - 61 not used 00 00
62 SPD Revision 10 10
63 Checksum of Byte 0-62 1A 1B
64 JEDEC ID Code of Infineon (1) C1 C1
65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00
72 Module Manufacturer Location xx xx
73 Part Number, Char 1 36 36
74 Part Number, Char 2 34 34
75 Part Number, Char 3 44 44
76 Part Number, Char 4 33 36
77 Part Number, Char 5 32 34
78 Part Number, Char 6 30 30
79 Part Number, Char 7 30 32
80 Part Number, Char 8 30 30
81 Part Number, Char 9 48 48
82 Part Number, Char 10 44 44
83 Part Number, Char 11 4C 4C
84 Part Number, Char 12 36 36
85 Part Number, Char 13 43 43
86 Part Number, Char 14 20 20
87 Part Number, Char 15 20 20
88 Part Number, Char 16 20 20
89 Part Number, Char 17 20 20
90 Part Number, Char 18 20 20
91 Module Revision Code 0x 0x

Data Sheet 27 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary SPD Contents

Table 11 SPD Codes for HYS64D[32/64][000/020]HDL–6–C (cont’d)

Product Type HYS64D32000HDL–6–C HYS64D64020HDL–6–C
Organization 256 MB 512 MB
×64 ×64
1 Rank (×16) 2 Ranks (×16)
Label Code PC2700S–2533–1 PC2700S–2533–1
JEDEC SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
92 Test Program Revision Code xx xx
93 Module Manufacturing Date Year xx xx
94 Module Manufacturing Date Week xx xx
95 - 98 Module Serial Number (1 - 4) xx xx
99 - 127 not used 00 00

Data Sheet 28 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Package Outlines

5 Package Outlines

67.6
63.6 ±0.1 3.8 MAX.

31.75
1.8 ±0.05
4 ±0.1

(2.15) 1 18.45 ±0.1 (2.45) 199 1±0.1

0.15
1.8 ±0.1
(2.4)

11.4 ±0.1 47.4 ±0.1

(2.7)
(2.45) 1.5 ±0.1 (2.15)

1±0.1
4 ±0.1

6 ±0.1

2 200
20 ±0.1

2 MIN.

Detail of contacts
0.25 -0.18

2.55

0.45 ±0.03
0.6 ±0.1

Burnished, no burr allowed GLD09568

Figure 4 Package Outline SO-DIMM Raw Card A (L-DIM-200-6)

Data Sheet 29 Rev. 0.5, 2005-03

 HYS64D[32/64][000/020]HDL–[5/6]–C
Small Outline DDR SDRAM Modules

Preliminary Package Outlines

67.6
63.6 2.4 MAX.

31.75
1.8 ±0.05
4 ±0.1

(2.15) 1 18.45 ±0.1 (2.45) 199 1±0.1

0.15
1.8 ±0.1
(2.4)

11.4 ±0.1 47.4 ±0.1

(2.7)
(2.45) 1.5 ±0.1 (2.15)

1±0.1
6 ±0.1
4 ±0.1

2 200
20 ±0.1

2 MIN.

Detail of contacts
0.25 -0.18

2.55

0.45 ±0.03
0.6 ±0.1

Burnished, no burr allowed GLD09570

Figure 5 Package Outline SO-DIMM Raw Card C (L-DIM-200-11)

Data Sheet 30 Rev. 0.5, 2005-03

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Published by Infineon Technologies AG