32-Bit

Microcontroller

TC1784
32-Bit Single-Chip Microcontroller

Data Sheet
V 1.0 2012-03

Microcontrollers
Edition 2012-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.

Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.

Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).

Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
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be endangered.
32-Bit
Microcontroller

TC1784
32-Bit Single-Chip Microcontroller

Data Sheet
V 1.0 2012-03

Microcontrollers
 TC1784

Table of Contents
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2 System Overview of the TC1784 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 TC1784 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.1 TC1784 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
4 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
5 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
5.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
5.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
5.1.2 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . 5-44
5.1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.1.4 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
5.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
5.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
5.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
5.2.2 Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . 5-67
5.2.3 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . 5-72
5.2.4 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-76
5.2.5 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77
5.2.6 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78
5.2.6.1 Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . 5-80
5.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82
5.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-82
5.3.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
5.3.3 Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85
5.3.4 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-87
5.3.5 ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . 5-89
5.3.6 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90
5.3.7 DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92
5.3.8 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94
5.3.8.1 Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-94
5.3.8.2 Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . 5-96
5.3.8.3 SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98
5.3.8.4 ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-100
5.3.8.5 EBU Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-102
5.4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-111
5.4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-111
5.4.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-112

Data Sheet I-1 V 1.0, 2012-03

 TC1784

5.4.3 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-112

5.4.4 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-114
6 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-115

Data Sheet I-2 V 1.0, 2012-03

 TC1784

Data Sheet 3 V 1.0, 2012-03

 TC1784

Data Sheet 4 V 1.0, 2012-03

 TC1784

Summary of Features

1 Summary of Features
The SAK-TC1784F-320F180EL has the following features:
• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Single precision Floating Point Unit (FPU)
– 180 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 180 MHz operation at full temperature range
• Multiple on-chip memories
– 2.5 Mbyte Program Flash Memory (PFLASH) with ECC
– 64 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 128 Kbyte Data Memory (LDRAM)
– Instruction Cache: up to 16 Kbyte (ICACHE, configurable)
– 40 Kbyte Code Scratchpad Memory (SPRAM)
– Data Cache: up to 4 Kbyte (DCACHE, configurable)
– 8 Kbyte Overlay Memory (OVRAM)
– 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
• High performing on-chip bus structure
– 64-bit Local Memory Buses between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Three High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– One serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
– One High-Speed Micro Link interface (MLI) for serial inter-processor
communication
– One External Bus Interface (EBU) with
32-bit demultiplexed / 16-bit multiplexed external bus interface
Scalable external bus timing up to 75 MHz

Data Sheet 1 V 1.0, 2012-03

 TC1784

Summary of Features

– One MultiCAN Module with 3 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRayTM module with 2 channels (E-Ray).
– One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell
Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
• 32 analog input lines for ADC
– 2 independent kernels (ADC0 and ADC1)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
• 4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
• 91 digital general purpose I/O lines (GPIO), 4 input lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1784ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL
The SAK-TC1784N-320F180EL has the following features:
• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Single precision Floating Point Unit (FPU)
– 180 MHz operation at full temperature range
• 32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
– 180 MHz operation at full temperature range
• Multiple on-chip memories
– 2.5 Mbyte Program Flash Memory (PFLASH) with ECC
– 64 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 128 Kbyte Data Memory (LDRAM)
– Instruction Cache: up to 16 Kbyte (ICACHE, configurable)
– 40 Kbyte Code Scratchpad Memory (SPRAM)
– Data Cache: up to 4 Kbyte (DCACHE, configurable)
– 8 Kbyte Overlay Memory (OVRAM)

Data Sheet 2 V 1.0, 2012-03

 TC1784

Summary of Features

– 16 Kbyte BootROM (BROM)

• 16-Channel DMA Controller
• Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
• High performing on-chip bus structure
– 64-bit Local Memory Buses between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Three High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– One serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
– One High-Speed Micro Link interface (MLI) for serial inter-processor
communication
– One External Bus Interface (EBU) with
32-bit demultiplexed / 16-bit multiplexed external bus interface
Support for Burst Flash memory devices
Scalable external bus timing up to 75 MHz
– One MultiCAN Module with 3 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell
Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
• 32 analog input lines for ADC
– 2 independent kernels (ADC0 and ADC1)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
• 4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of fFADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
• 91 digital general purpose I/O lines (GPIO), 4 input lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1784ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL

Data Sheet 3 V 1.0, 2012-03

 TC1784

Summary of Features

Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
• The package and the type of delivery.
For the available ordering codes for the TC1784 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1 enumerates these
derivatives and summarizes the differences.

Table 1 TC1784 Derivative Synopsis

Derivative Ambient Temperature Range
SAK-TC1784F-320F180EL TA = -40oC to +125oC
SAK-TC1784N-320F180EL TA = -40oC to +125oC

Data Sheet 4 V 1.0, 2012-03

 TC1784

System Overview of the TC1784

2 System Overview of the TC1784

The TC1784 combines three powerful technologies within one silicon die, achieving new
levels of power, speed, and economy for embedded applications:
• Reduced Instruction Set Computing (RISC) processor architecture
• Digital Signal Processing (DSP) operations and addressing modes
• On-chip memories and peripherals
DSP operations and addressing modes provide the computational power necessary to
efficiently analyze complex real-world signals. The RISC load/store architecture
provides high computational bandwidth with low system cost. On-chip memory and
peripherals are designed to support even the most demanding high-bandwidth real-time
embedded control-systems tasks.
Additional high-level features of the TC1784 include:
• Efficient memory organization: instruction and data scratch memories, caches
• Serial communication interfaces – flexible synchronous and asynchronous modes
• Peripheral Control Processor – standalone data operations and interrupt servicing
• DMA Controller – DMA operations and interrupt servicing
• General-purpose timers
• High-performance on-chip buses
• On-chip debugging and emulation facilities
• Flexible interconnections to external components
• Flexible power-management
The TC1784 is a high-performance microcontroller with TriCore CPU, program and data
memories, buses, bus arbitration, an interrupt controller, a peripheral control processor
and a DMA controller and several on-chip peripherals. The TC1784 is designed to meet
the needs of the most demanding embedded control systems applications where the
competing issues of price/performance, real-time responsiveness, computational power,
data bandwidth, and power consumption are key design elements.
The TC1784 offers several versatile on-chip peripheral units such as serial controllers,
timer units, and Analog-to-Digital converters. Within the TC1784, all these peripheral
units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect
(FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1784 ports are
reserved for these peripheral units to communicate with the external world.

Data Sheet 1 V 1.0, 2012-03

 TC1784

System Overview of the TC1784TC1784 Block Diagram

2.1 TC1784 Block Diagram

Figure 1 shows the block diagram of the TC1784.

Abbreviations:
ICACHE: Instruction Cache
FPU DCACHE Data Cache
PMI DMI SPRAM: Scratch-Pad RAM
LDRAM: Local Data RAM
24 KB SPRAM TriCore 124 KB LDRAM OVRAM: Overlay RAM
CPU LDRAM BROM: Boot ROM
16 KB ICACHE 4 KB DCACHE
PFlash: Program Flash
(Configurable) (Configurable)
DCACHE DFlash: Data Flash
PRAM: Parameter RAM in PCP
CPS
PCODE: Code RAM in PCP

EBU BCU
Local Memory Bus (LMB)

PMU M

DMA

SMIF
2,5 MB PFlash Bridge OCDS L1 Debug
16 channels
128 KB DFlash Interface/JTAG
8 KB OVRAM M/ S
16 KB BROM

MLI0
System Peripheral Bus
(SPB)

MemCheck
16 KB PRAM
Interrupt
FPI-Bus Interface

ASC0 System
Interrupts

PCP2
Core

ASC1 STM
5V (3.3V supported as well)
Ext. ADC Supply
System Peripheral Bus

32 KB CMEM
SCU
E-Ray
(2 Channels) ADC0 28
( 5V max)

PLL Ports ADC1

E-RAY
GPTA 0 SBCU 4
PLL

SSC0 FADC ( 3.3V max)

LTCA2 4

3.3V
SSC1 Ext. FADC Supply

Ext. Multi
Request CAN MSC0
(3 Nodes, (LVDS) SSC2 BlockDiagram
Unit 128 MO) TC1784F
V1.1

Figure 1 TC1784F Block Diagram

Figure 1 shows the block diagram of the SAK-TC1784F-320F180EL.

Data Sheet 2 V 1.0, 2012-03

 TC1784

System Overview of the TC1784TC1784 Block Diagram

Abbreviations:
ICACHE: Instruction Cache
FPU DCACHE Data Cache
PMI DMI SPRAM: Scratch-Pad RAM
LDRAM: Local Data RAM
24 KB SPRAM TriCore 124 KB LDRAM OVRAM: Overlay RAM
CPU LDRAM BROM: Boot ROM
16 KB ICACHE 4 KB DCACHE
PFlash: Program Flash
(Configurable) (Configurable)
DCACHE DFlash: Data Flash
PRAM: Parameter RAM in PCP
CPS
PCODE: Code RAM in PCP

EBU BCU
Local Memory Bus (LMB)

PMU M

DMA

SMIF
2,5 MB PFlash Bridge OCDS L1 Debug
16 channels
128 KB DFlash Interface/JTAG
8 KB OVRAM M/S
16 KB BROM

MLI0
System Peripheral Bus
(SPB)

MemCheck
16 KB PRAM
Interrupt
FPI-Bus Interface

ASC0 System
Interrupts

PCP2
Core

STM
ASC1
5V (3.3V supported as well)
Ext. ADC Supply
System Peripheral Bus

32 KB CMEM
SCU
ADC0 28
(5V max)

PLL Ports ADC1

E-RAY
GPTA 0 SBCU 4
PLL

SSC0 FADC (3.3V max)

LTCA2 4

3.3V
SSC1 Ext. FADC Supply

Ext. Multi
Request CAN MSC0
(3 Nodes, (LVDS) SSC2 BlockDiagram
Unit 128 MO) TC1784N
V1.1

Figure 2 TC1784N Block Diagram

Figure 2 shows the block diagram of the SAK-TC1784N-320F180EL.

Data Sheet 3 V 1.0, 2012-03

 TC1784

System Overview of the TC1784TC1784 Block Diagram

Data Sheet 4 V 1.0, 2012-03

 TC1784

PinningTC1784 Pin Configuration

3 Pinning
Figure 3-1 is showing the TC1784 Logic Symbol.

PORST Alternate Functions

TESTMODE 16
General Control GPTA, SCU. E-RAY,
ESR0 Port 0 MSC0
ESR1 16 GPTA, SSC1,
Port 1
TRST ADC0, OCDS
14 GPTA, SSC0/1,
Port 2 MLI0, MSC0
TCK / DAP0
OCDS / 16 GPTA, ASC0/1, SSC 0/1,
JTAG Control TDI / BRKIN Port 3 SCU, CAN, MSC 0
TDO / DAP2 / 4
BRKOUT Port 4 GPTA, SCU, CAN
TMS / DAP1 16 GPTA, MLI0, E-RAY,
Port 5
Analog Inputs AN [35:0] SSC2
4
V DDM Port 6 GPTA, MSC 0
VSSM TC1784 16
VDDMF Port 7 GPTA, EBU
V SSMF 15
VDDAF Port 8 GPTA, EBU
Analog Power
Supply VAREF0 8
Port 9 GPTA, SCU, CAN
VAREF1
14
VAGND0 Port 10 GPTA, SSC 2
V FAREF
XTAL1
VFAGND
2 XTAL2
V DDFL3
12 VDDOSC
VDD VDDOSC3
11 Oscillator
Digital Circuitry VDDP
Power Supply VSSOSC
48
V SS
V DDPF
15
VSSP V DDPF3

TC1784_LogSym_292

Figure 3-1 TC1784 Logic Symbol

3.1 TC1784 Pin Configuration

This chapter shows the pin configuration of package variant PG-LFBGA-292.

Data Sheet 3-5 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A N.C.2 P10.9 P10.8 P10.6 P10.4 VSSP P2.12 P2.11 P6.2 P6.0 VSSP P0.12 P0.10 P0.8 P3.13 P3.15 P3.4 P3.2 P3.8 VSSP A

B VDDP VSSP P10.7 P10.5 P10.3 VDDP P0.15 P2.10 P6.3 P6.1 VDDP P0.13 P0.11 P0.9 P3.12 P3.14 P3.7 P3.3 VSSP VDDP B

C P10.10 VDDP Top-View VDDP P3.6 C

D P5.0 P10.11 VSSP P10.2 P10.0 P0.14 P0.6 P2.13 P2.9 P0.2 P0.1 VDDFL3 VDDFL3 P3.0 P3.1 VSSP P3.5 ESR0 D

E P5.5 P5.1 P10.12 VSSP P10.1 P0.7 P0.5 P0.4 P2.8 P0.3 P0.0 P3.11 P3.9 P3.10 VSSP P1.1 ESR1 PORST E

TEST
F P5.6 P5.7 P5.2 P10.13 P1.15 P1.0 TCK F
MODE

G VSSP VDDP P9.0 P5.3 VDD VSS VSS VSS VSS VDD P1.6 P1.7 TRST TDO G

H P5.15 P5.8 P9.1 P5.4 VDD VSS VSS VSS VSS VDD P1.5 TMS TDI VDDOSC3 H

J P5.10 P5.9 P9.3 P9.2 VSS VSS VSS VSS VSS VSS P1.4 VDDPF3 XTAL2 XTAL1 J

K P5.12 P5.11 P9.4 P9.5 VSS VSS VSS VSS VSS VSS VSS VSS P1.3 VDDPF VDDOSC VSSOSC K

L P5.14 P5.13 P9.6 P9.7 VSS VSS VSS VSS VSS VSS VSS VSS P1.10 P1.8 P1.9 P1.11 L

M VSSP VDDP N.C.3 N.C.4 VSS VSS VSS VSS VSS VSS P1.2 P8.14 VDDP VSSP M

N VDDMF VDDAF VFAREF VFAGND VDD VSS VSS VSS VSS VDD P8.13 P8.12 P8.11 P8.4 N

VSSAF
P AN35 AN34 AN33 VDD VSS VSS VSS VSS VDD P8.10 P8.9 P8.8 P8.7 P
VSSMF

R AN32 AN31 AN30 AN29 VDD P7.2 P8.6 P8.5 R

T AN28 AN7 AN25 AN24 VAGND0 VAREF1 AN6 AN2 P1.12 P2.3 P2.7 P4.0 P7.4 P7.7 VSS VDD P8.2 P8.3 T

U AN27 AN26 AN21 AN15 VAREF0 AN8 AN3 P1.14 P1.13 P2.2 P2.6 P4.1 P7.3 P7.8 P7.0 VSS P8.0 P8.1 U

V AN23 AN22 VDD P7.15 V

W AN20 AN14 AN16 AN18 AN17 AN19 VSSM AN5 AN1 VDDP P2.1 P2.5 P4.2 P7.6 P7.9 VDDP P7.11 P7.13 VSS VDD W

Y N.C.1 AN13 AN12 AN11 AN10 AN9 VDDM AN4 AN0 VSSP P2.0 P2.4 P4.3 P7.1 P7.5 VSSP P7.10 P7.12 P7.14 VSS Y

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Figure 3-2 TC1784 Pinning for PG-LFBGA-292 Package

Data Sheet 3-6 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292)

Pin Symbol Ctrl. Type Function
Port 0
E12 P0.0 I/O0 A1/ Port 0 General Purpose I/O Line 0
IN0 I PU GPTA0 Input 0
IN0 I LTCA2 Input 0
HWCFG0 I Hardware Configuration Input 0
OUT0 O1 GPTA0 Output 0
OUT56 O2 GPTA0 Output 56
OUT0 O3 LTCA2 Output 0
D12 P0.1 I/O0 A1/ Port 0 General Purpose I/O Line 1
IN1 I PU GPTA0 Input 1
IN1 I LTCA2 Input 1
SDI1 I MSC0 Serial Data Input 1
HWCFG1 I Hardware Configuration Input 1
OUT1 O1 GPTA0 Output 1
OUT57 O2 GPTA0 Output 57
OUT1 O3 LTCA2 Output 1
D11 P0.2 I/O0 A1/ Port 0 General Purpose I/O Line 2
IN2 I PU GPTA0 Input 2
IN2 I LTCA2 Input 2
HWCFG2 I Hardware Configuration Input 2
OUT2 O1 GPTA0 Output 2
OUT58 O2 GPTA0 Output 58
OUT2 O3 LTCA2 Output 2
E11 P0.3 I/O0 A1+/ Port 0 General Purpose I/O Line 3
IN3 I PU GPTA0 Input 3
IN3 I LTCA2 Input 3
HWCFG3 I Hardware Configuration Input 3
OUT3 O1 GPTA0 Output 3
OUT59 O2 GPTA0 Output 59
OUT3 O3 LTCA2 Output 3

Data Sheet 3-7 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
E9 P0.4 I/O0 A1/ Port 0 General Purpose I/O Line 4
IN4 I PU GPTA0 Input 4
IN4 I LTCA2 Input 4
HWCFG4 I Hardware Configuration Input 4
OUT4 O1 GPTA0 Output 4
OUT60 O2 GPTA0 Output 60
OUT4 O3 LTCA2 Output 4
E8 P0.5 I/O0 A1/ Port 0 General Purpose I/O Line 5
IN5 I PU GPTA0 Input 5
IN5 I LTCA2 Input 5
HWCFG5 I Hardware Configuration Input 5
OUT5 O1 GPTA0 Output 5
OUT61 O2 GPTA0 Output 61
OUT5 O3 LTCA2 Output 5
D8 P0.6 I/O0 A1/ Port 0 General Purpose I/O Line 6
IN6 I PU GPTA0 Input 6
IN6 I LTCA2 Input 6
HWCFG6 I Hardware Configuration Input 6
REQ2 I External Request Input 2
OUT6 O1 GPTA0 Output 6
OUT62 O2 GPTA0 Output 62
OUT6 O3 LTCA2 Output 6
E7 P0.7 I/O0 A1/ Port 0 General Purpose I/O Line 7
IN7 I PU GPTA0 Input 7
IN7 I LTCA2 Input 7
HWCFG7 I Hardware Configuration Input 7
REQ3 I External Request Input 3
OUT7 O1 GPTA0 Output 7
OUT63 O2 GPTA0 Output 63
OUT7 O3 LTCA2 Output 7

Data Sheet 3-8 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
A14 P0.8 I/O0 A1/ Port 0 General Purpose I/O Line 8
IN8 I PU GPTA0 Input 8
IN8 I LTCA2 Input 8
RXDA0 I E-Ray Channel A Receive Data Input 0
OUT8 O1 GPTA0 Output 8
OUT64 O2 GPTA0 Output 64
OUT8 O3 LTCA2 Output 8
B14 P0.9 I/O0 A1/ Port 0 General Purpose I/O Line 9
IN9 I PU GPTA0 Input 9
IN9 I LTCA2 Input 9
RXDB0 I E-Ray Channel B Receive Data Input 0
OUT9 O1 GPTA0 Output 9
OUT65 O2 GPTA0 Output 65
OUT9 O3 LTCA2 Output 9
A13 P0.10 I/O0 A2/ Port 0 General Purpose I/O Line 10
IN10 I PU GPTA0 Input 10
OUT10 O1 GPTA0 Output 10
TXDA0 O2 E-Ray Channel A transmit Data Output
OUT10 O3 LTCA2 Output 10
B13 P0.11 I/O0 A2/ Port 0 General Purpose I/O Line 11
IN11 I PU GPTA0 Input 11
OUT11 O1 GPTA0 Output 11
TXDB0 O2 E-Ray Channel B transmit Data Output
OUT11 O3 LTCA2 Output 11
A12 P0.12 I/O0 A2/ Port 0 General Purpose I/O Line 12
IN12 I PU GPTA0 Input 12
OUT12 O1 GPTA0 Output 12
TXENA O2 E-Ray Channel A transmit Data Output enable
OUT12 O3 LTCA2 Output 12

Data Sheet 3-9 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
B12 P0.13 I/O0 A2/ Port 0 General Purpose I/O Line 13
IN13 I PU GPTA0 Input 13
OUT13 O1 GPTA0 Output 13
TXENB O2 E-Ray Channel B transmit Data Output enable
OUT13 O3 LTCA2 Output 13
D7 P0.14 I/O0 A1+/ Port 0 General Purpose I/O Line 14
IN14 I PU GPTA0 Input 14
REQ4 I External Request Input 4
OUT14 O1 GPTA0 Output 14
FCLP0C O2 MSC0 Clock Output Positive C
OUT14 O3 LTCA2 Output 14
B7 P0.15 I/O0 A1+/ Port 0 General Purpose I/O Line 15
IN15 I PU GPTA0 Input 15
REQ5 I External Request Input 5
OUT15 O1 GPTA0 Output 15
SOP0C O2 MSC0 Serial Data Output Positive C
OUT15 O3 LTCA2 Output 15
Port 1
F17 P1.0 I/O0 A2/ Port 1 General Purpose I/O Line 0
IN16 I PU GPTA0 Input 16
BRKIN I Break Input
OUT16 O1 GPTA0 Output 16
OUT72 O2 GPTA0 Output 72
OUT16 O3 LTCA2 Output 16
BRKOUT O Break Output (controlled by OCDS module)
E17 P1.1 I/O0 A1/ Port 1 General Purpose I/O Line 1
IN17 I PU GPTA0 Input 17
OUT17 O1 GPTA0 Output 17
OUT73 O2 GPTA0 Output 73
OUT17 O3 LTCA2 Output 17

Data Sheet 3-10 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
M16 P1.2 I/O0 A1/ Port 1 General Purpose I/O Line 2
IN18 I PU GPTA0 Input 18
OUT18 O1 GPTA0 Output 18
OUT74 O2 GPTA0 Output 74
OUT18 O3 LTCA2 Output 18
K16 P1.3 I/O0 A1/ Port 1 General Purpose I/O Line 3
IN19 I PU GPTA0 Input 19
IN19 I LTCA2 Input 19
OUT19 O1 GPTA0 Output 19
OUT75 O2 GPTA0 Output 75
OUT19 O3 LTCA2 Output 19
J16 P1.4 I/O0 A1/ Port 1 General Purpose I/O Line 4
IN20 I PU GPTA0 Input 20
IN20 I LTCA2 Input 20
EMGSTOP I Emergency Stop Input
OUT20 O1 GPTA0 Output 20
OUT76 O2 GPTA0 Output 76
OUT20 O3 LTCA2 Output 20
H16 P1.5 I/O0 A1/ Port 1 General Purpose I/O Line 35
IN21 I PU GPTA0 Input 21
IN21 I LTCA2 Input 21
OUT21 O1 GPTA0 Output 21
OUT77 O2 GPTA0 Output 77
OUT21 O3 LTCA2 Output 21
G16 P1.6 I/O0 A1/ Port 1 General Purpose I/O Line 6
IN22 I PU GPTA0 Input 22
IN22 I LTCA2 Input 22
OUT22 O1 GPTA0 Output 22
OUT78 O2 GPTA0 Output 78
OUT22 O3 LTCA2 Output 22

Data Sheet 3-11 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
G17 P1.7 I/O0 A1/ Port 1 General Purpose I/O Line 7
IN23 I PU GPTA0 Input 23
IN23 I LTCA2 Input 23
OUT23 O1 GPTA0 Output 23
OUT79 O2 GPTA0 Output 79
OUT23 O3 LTCA2 Output 23
L17 P1.8 I/O0 A1+/ Port 1 General Purpose I/O Line 8
IN24 I PU GPTA0 Input 24
IN48 I GPTA0 Input 48
MTSR1B I SSC1 Slave Receive Input B (Slave Mode)
OUT24 O1 GPTA0 Output 24
OUT48 O2 GPTA0 Output 48
MTSR1B O3 SSC1 Master Transmit Output B (Master Mode)
L19 P1.9 I/O0 A1+/ Port 1 General Purpose I/O Line 9
IN25 I PU GPTA0 Input 25
IN49 I GPTA0 Input 49
MRST1B I SSC1 Master Receive Input B (Master Mode)
OUT25 O1 GPTA0 Output 25
OUT49 O2 GPTA0 Output 49
MRST1B O3 SSC1 Slave Transmit Output B (Slave Mode)
L16 P1.10 I/O0 A1+/ Port 1 General Purpose I/O Line 10
IN26 I PU GPTA0 Input 26
IN50 I GPTA0 Input 50
OUT26 O1 GPTA0 Output 26
OUT50 O2 GPTA0 Output 50
SLSO17 O3 SSC1 Slave Select Output 7

Data Sheet 3-12 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
L20 P1.11 I/O0 A1+/ Port 1 General Purpose I/O Line 11
IN27 I PU GPTA0 Input 27
IN51 I GPTA0 Input 51
SCLK1B I SSC1 Clock Input B
OUT27 O1 GPTA0 Output 27
OUT51 O2 GPTA0 Output 51
SCLK1B O3 SSC1 Clock Output B
T10 P1.12 I/O0 A1/ Port 1 General Purpose I/O Line 12
IN16 I PU LTCA2 Input 16
AD0EMUX0 O1 ADC0 External Multiplexer Control Output 0
AD0EMUX0 O2 ADC0 External Multiplexer Control Output 0
OUT16 O3 LTCA2 Output 16
U10 P1.13 I/O0 A1/ Port 1 General Purpose I/O Line 13
IN17 I PU LTCA2 Input 17
AD0EMUX1 O1 ADC0 External Multiplexer Control Output 1
AD0EMUX1 O2 ADC0 External Multiplexer Control Output 1
OUT17 O3 LTCA2 Output 17
U9 P1.14 I/O0 A1/ Port 1 General Purpose I/O Line 14
IN18 I PU LTCA2 Input 18
AD0EMUX2 O1 ADC0 External Multiplexer Control Output 2
AD0EMUX2 O2 ADC0 External Multiplexer Control Output 2
OUT18 O3 LTCA2 Output 18
F16 P1.15 I/O0 A2/ Port 1 General Purpose I/O Line 15
BRKIN I PU OCDS Break Input
Reserved O1 -
Reserved O2 -
Reserved O3 -
BRKOUT O OCDS Break Output
Port 2

Data Sheet 3-13 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
Y11 P2.0 I/O0 A2/ Port 2 General Purpose I/O Line 0
IN32 I PU GPTA0 Input 32
OUT32 O1 GPTA0 Output 32
TCLK0 O2 MLI0 Transmitter Clock Output 0
OUT28 O3 LTCA2 Output 28
W11 P2.1 I/O0 A2/ Port 2 General Purpose I/O Line 1
IN33 I PU GPTA0 Input 33
TREADY0A I MLI0 Transmitter Ready Input A
OUT33 O1 GPTA0 Output 33
SLSO03 O2 SSC0 Slave Select Output Line 3
SLSO13 O3 SSC1 Slave Select Output Line 3
U11 P2.2 I/O0 A2/ Port 2 General Purpose I/O Line 2
IN34 I PU GPTA0 Input 34
OUT34 O1 GPTA0 Output 34
TVALID0 O2 MLI0 Transmitter Valid Output
OUT29 O3 LTCA2 Output 29
T11 P2.3 I/O0 A2/ Port 2 General Purpose I/O Line 3
IN35 I PU GPTA0 Input 35
OUT35 O1 GPTA0 Output 35
TDATA0 O2 MLI0 Transmitter Data Output
OUT30 O3 LTCA2 Output 30
Y12 P2.4 I/O0 A2/ Port 2 General Purpose I/O Line 4
IN36 I PU GPTA0 Input 36
RCLK0A I MLI Receiver Clock Input A
OUT36 O1 GPTA0 Output 36
OUT36 O2 GPTA0 Output 36
OUT31 O3 LTCA2 Output 31

Data Sheet 3-14 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
W12 P2.5 I/O0 A2/ Port 2 General Purpose I/O Line 5
IN37 I PU GPTA0 Input 37
OUT37 O1 GPTA0 Output 37
RREADY0A O2 MLI0 Receiver Ready Output A
OUT110 O3 LTCA2 Output 110
U12 P2.6 I/O0 A2/ Port 2 General Purpose I/O Line 6
IN38 I PU GPTA0 Input 38
RVALID0A I MLI Receiver Valid Input A
OUT38 O1 GPTA0 Output 38
OUT38 O2 GPTA0 Output 38
OUT111 O3 LTCA2 Output 111
T12 P2.7 I/O0 A2/ Port 2 General Purpose I/O Line 7
IN39 I PU GPTA0 Input 39
RDATA0A I MLI Receiver Data Input A
OUT39 O1 GPTA0 Output 39
OUT39 O2 GPTA0 Output 39
Reserved O3 -
E10 P2.8 I/O0 A2/ Port 2 General Purpose I/O Line 8
SLSO04 O1 PU SSC0 Slave Select Output 4
SLSO14 O2 SSC1 Slave Select Output 4
EN00 O3 MSC0 Enable Output 0
D10 P2.9 I/O0 A2/ Port 2 General Purpose I/O Line 9
SLSO05 O1 PU SSC0 Slave Select Output 5
SLSO15 O2 SSC1 Slave Select Output 5
EN01 O3 MSC0 Enable Output 1

Data Sheet 3-15 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
B8 P2.10 I/O0 A1+/ Port 2 General Purpose I/O Line 10
MRST1A I PU SSC1 Master Receive Input A
IN10 I LTCA2 Input 10
MRST1A O1 SSC1 Slave Transmit Output
OUT0 O2 LTCA2 Output 0
Reserved O3 -
A8 P2.11 I/O0 A1+/ Port 2 General Purpose I/O Line 11
SCLK1A I PU SSC1 Clock Input A
IN11 I LTCA2 Input 11
SCLK1A O1 SSC1 Clock Output A
OUT1 O2 LTCA2 Output 1
FCLP0B O3 MSC0 Clock Output Positive B
A7 P2.12 I/O0 A1+/ Port 2 General Purpose I/O Line 12
MTSR1A I PU SSC1 Slave Receive Input A
IN12 I LTCA2 Input 12
MTSR1A O1 SSC1 Master Transmit Output A
OUT2 O2 LTCA2 Output 2
SOP0B O3 MSC0 Serial Data Output Positive B
D9 P2.13 I/O0 A1/ Port 2 General Purpose I/O Line 13
SLSI11 I PU SSC1 Slave Select Input 1
SDI0 I MSC0 Serial Data Input 0
IN13 I LTCA2 Input 13
OUT3 O1 LTCA2 Output 3
Reserved O2 -
Reserved O3 -
Port 3

Data Sheet 3-16 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
D15 P3.0 I/O0 A1+/ Port 3 General Purpose I/O Line 0
RXD0A I PU ASC0 Receiver Input A (Async. & Sync. Mode)
RXD0A O1 ASC0 Clock Output (Sync. Mode)
RXD0A O2 ASC0 Clock Output (Sync. Mode)
OUT84 O3 GPTA0 Output 84
D16 P3.1 I/O0 A1+/ Port 3 General Purpose I/O Line 1
TXD0 O1 PU ASC0 Transmit
TXD0 O2 ASC0 Transmit
OUT85 O3 GPTA0 Output 85
A18 P3.2 I/O0 A1+/ Port 3 General Purpose I/O Line 2
SCLK0 I PU SSC0 Clock Input (Slave Mode)
SCLK0 O1 SSC0 Clock Output (Master Mode)
SCLK0 O2 SSC0 Clock Input (Master Mode)
OUT86 O3 GPTA0 Output 86
B18 P3.3 I/O0 A1+/ Port 3 General Purpose I/O Line 3
MRST0 I PU SSC0 Master Receive Input (Master Mode)
MRST0 O1 SSC0 Slave Transmit Output (Slave Mode)
MRST0 O2 SSC0 Slave Transmit Output (Slave Mode)
OUT87 O3 GPTA0 Output 87
A17 P3.4 I/O0 A2/ Port 3 General Purpose I/O Line 4
MTSR0 I PU SSC0 Slave Receive Input (Slave Mode)
MTSR0 O1 SSC0 Master Transmit Output (Master Mode)
MTSR0 O2 SSC0 Master Transmit Output (Master Mode)
OUT88 O3 GPTA0 Output 88
D19 P3.5 I/O0 A1+/ Port 3 General Purpose I/O Line 5
SLSO00 O1 PU SSC0 Slave Select Output 0
SLSO10 O2 SSC1 Slave Select Output 0
SLSOANDO0 O3 SSC0 AND SSC1 Slave Select Output 0

Data Sheet 3-17 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
C20 P3.6 I/O0 A1+/ Port 3 General Purpose I/O Line 6
SLSO01 O1 PU SSC0 Slave Select Output 1
SLSO11 O2 SSC1 Slave Select Output 1
SLSOANDO1 O3 SSC0 AND SSC1 Slave Select Output 1
B17 P3.7 I/O0 A2/ Port 3 General Purpose I/O Line 7
SLSI0 I PU SSC0 Slave Select Input 1
SLSO02 O1 SSC0 Slave Select Output 2
SLSO12 O2 SSC1 Slave Select Output 2
OUT89 O3 GPTA0 Output 89
A19 P3.8 I/O0 A2/ Port 3 General Purpose I/O Line 8
SLSO06 O1 PU SSC0 Slave Select Output 6
TXD1 O2 ASC1 Transmit Output
OUT90 O3 GPTA0 Output 90
E14 P3.9 I/O0 A1/ Port 3 General Purpose I/O Line 9
RXD1A I PU ASC1 Receiver Input A
RXD1A O1 ASC1 Receiver Output A (Synchronous Mode)
RXD1A O2 ASC1 Receiver Output A (Synchronous Mode)
OUT91 O3 GPTA0 Output 91
E15 P3.10 I/O0 A1/ Port 3 General Purpose I/O Line 10
REQ0 I PU External Request Input 0
Reserved O1 -
Reserved O2 -
OUT92 O3 GPTA0 Output 92
E13 P3.11 I/O0 A1/ Port 3 General Purpose I/O Line 11
REQ1 I PU External Request Input 1
Reserved O1 -
Reserved O2 -
OUT93 O3 GPTA0 Output 93

Data Sheet 3-18 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
B15 P3.12 I/O0 A1/ Port 3 General Purpose I/O Line 12
RXDCAN0 I PU CAN Node 0 Receiver Input
RXD0B I ASC0 Receiver Input B
RXD0B O1 ASC0 Receiver Output B (Synchronous Mode)
RXD0B O2 ASC0 Receiver Output B (Synchronous Mode)
OUT94 O3 GPTA0 Output 94
A15 P3.13 I/O0 A2/ Port 3 General Purpose I/O Line 13
TXDCAN0 O1 PU CAN Node 0 Transmitter Output
TXD0 O2 ASC0 Transmit Output
OUT95 O3 GPTA0 Output 95
B16 P3.14 I/O0 A1/ Port 3 General Purpose I/O Line 14
RXDCAN1 I PU CAN Node 1 Receiver Input
RXD1B I ASC1 Receiver Input B
SDI2 I MSC0 Serial Data Input 2
RXD1B O1 ASC1 Receiver Output B (Synchronous Mode)
RXD1B O2 ASC1 Receiver Output B (Synchronous Mode)
OUT96 O3 GPTA0 Output 96
A16 P3.15 I/O0 A2/ Port 3 General Purpose I/O Line 15
TXDCAN1 O1 PU CAN Node 1 Transmitter Output
TXD1 O2 ASC1 Transmit Output
OUT97 O3 GPTA0 Output 97
Port 4
T13 P4.0 I/O0 A1+/ Port 4 General Purpose I/O Line 0
IN28 I PU GPTA0 Input 28
IN52 I GPTA0 Input 52
RXDCAN2 I CAN Node 2 Receiver Input
OUT28 O1 GPTA0 Output 28
OUT28 O1 GPTA0 Output 28
OUT52 O2 GPTA0 Output 52

Data Sheet 3-19 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
U13 P4.1 I/O0 A1+/ Port 4 General Purpose I/O Line 1
IN29 I PU GPTA0 Input 29
IN53 I GPTA0 Input 53
OUT29 O1 GPTA0 Output 29
OUT53 O2 GPTA0 Output 53
TXDCAN2 O3 CAN Node 2 Transmitter Output
W13 P4.2 I/O0 A2/ Port 4 General Purpose I/O Line 2
IN30 I PU GPTA0 Input 30
IN54 I GPTA0 Input 54
OUT30 O1 GPTA0 Output 30
OUT54 O2 GPTA0 Output 54
EXTCLK1 O3 External Clock 1 Output
Y13 P4.3 I/O0 A2/ Port 4 General Purpose I/O Line 3
IN31 I PU GPTA0 Input 31
IN55 I GPTA0 Input 55
OUT31 O1 GPTA0 Output 31
OUT55 O2 GPTA0 Output 55
EXTCLK0 O3 External Clock 0 Output
Port 5
D1 P5.0 I/O0 A1+/ Port 5 General Purpose I/O Line 0
IN40 I PU GPTA0 Input 40
IN26 I LTCA2 Input 26
OUT40 O1 GPTA0 Output 40
OUT8 O2 LTCA2 Output 8
SLSO20 O3 SSC2 Slave Select Output 0

Data Sheet 3-20 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
E2 P5.1 I/O0 A1+/ Port 5 General Purpose I/O Line 1
IN41 I PU GPTA0 Input 41
IN27 I LTCA2 Input 27
OUT41 O1 GPTA0 Output 41
OUT9 O2 LTCA2 Output 9
SLSO21 O3 SSC2 Slave Select Output 1
F4 P5.2 I/O0 A1+/ Port 5 General Purpose I/O Line 2
IN42 I PU GPTA0 Input 42
IN28 I LTCA2 Input 28
OUT42 O1 GPTA0 Output 42
OUT10 O2 LTCA2 Output 10
SLSO22 O3 SSC2 Slave Select Output 2
G5 P5.3 I/O0 A1+/ Port 5 General Purpose I/O Line 3
IN43 I PU GPTA0 Input 43
OUT43 O1 GPTA0 Output 43
OUT11 O2 LTCA2 Output 11
SLSO23 O3 SSC2 Slave Select Output 3
H5 P5.4 I/O0 A1+/ Port 5 General Purpose I/O Line 4
IN44 I PU GPTA0 Input 44
IN29 I LTCA2 Input 29
SLSI2A I SSC2 Slave Select Input A
OUT44 O1 GPTA0 Output 44
OUT12 O2 LTCA2 Output 12
SLSO24 O3 SSC2 Slave Select Output 4

Data Sheet 3-21 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
E1 P5.5 I/O0 A1+/ Port 5 General Purpose I/O Line 5
IN45 I PU GPTA0 Input 45
IN30 I LTCA2 Input 30
MRST2A I SSC2 Master Receive Input (Master Mode)
OUT45 O1 GPTA0 Output 45
OUT13 O2 LTCA2 Output 13
MRST2 O3 SSC2 Slave Transmit Output (Slave Mode)
F1 P5.6 I/O0 A1+/ Port 5 General Purpose I/O Line 6
IN46 I PU GPTA0 Input 46
IN31 I LTCA2 Input 31
MTSR2A I SSC2 Slave Receive Input (Slave Mode)
OUT46 O1 GPTA0 Output 46
OUT14 O2 LTCA2 Output 14
MTSR2 O3 SSC2 Master Transmit Output (Master Mode)
F2 P5.7 I/O0 A1+/ Port 5 General Purpose I/O Line 7
IN47 I PU GPTA0 Input 47
SCLK2A I SSC0 Clock Input (Slave Mode)
OUT47 O1 GPTA0 Output 47
OUT15 O2 LTCA2 Output 15
SCLK2 O3 SSC0 Clock Output (Master Mode)
H2 P5.8 I/O0 A2/ Port 5 General Purpose I/O Line 8
RDATA0B I PU MLI0 Receiver Data Input B
Reserved O1 -
TXDA1 O2 E-Ray Channel A transmit Data Output
OUT89 O3 LTCA2 Output 89
J2 P5.9 I/O0 A2/ Port 5 General Purpose I/O Line 9
RVALID0B I PU MLI0 Receiver Data Valid Input B
Reserved O1 -
TXDB1 O2 E-Ray Channel B transmit Data Output
OUT90 O3 LTCA2 Output 90

Data Sheet 3-22 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
J1 P5.10 I/O0 A2/ Port 5 General Purpose I/O Line 10
RREADY0B O1 PU MLI0 Receiver Ready Input B
TXENA O2 E-Ray Channel A transmit Data Output enable
OUT91 O3 LTCA2 Output 91
K2 P5.11 I/O0 A2/ Port 5 General Purpose I/O Line 11
RCLK0B I PU MLI0 Receiver Clock Input B
Reserved O1 -
TXENB O2 E-Ray Channel B transmit Data Output enable
OUT92 O3 LTCA2 Output 92
K1 P5.12 I/O0 A1+/ Port 5 General Purpose I/O Line 12
TDATA0 O1 PU MLI0 Transmitter Data Output
SLSO07 O2 SSC0 Slave Select Output 7
OUT93 O3 LTCA2 Output 93
L2 P5.13 I/O0 A1+/ Port 5 General Purpose I/O Line 13
TVALID0B O1 PU MLI0 Transmitter Valid Input B
SLSO16 O2 SSC1 Slave Select Output 6
Reserved O3 -
L1 P5.14 I/O0 A1+/ Port 5 General Purpose I/O Line 14
TREADY0B I PU MLI0 Transmitter Ready Input B
RXDA1 I E-Ray Channel A Receive Data Input 1
Reserved O1 -
Reserved O2 -
OUT94 O3 LTCA2 Output 94
H1 P5.15 I/O0 A1+/ Port 5 General Purpose I/O Line 15
RXDB1 I PU E-Ray Channel B Receive Data Input 1
TCLK0 O1 MLI0 Transmitter Clock Output
Reserved O2 -
OUT95 O3 LTCA2 Output 95
Port 6

Data Sheet 3-23 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
A10 P6.0 I/O0 F/ Port 6 General Purpose I/O Line 0
IN14 I PU LTCA2 Input 14
FCLN0 O1 MSC0 Clock Output Negative
OUT80 O2 GPTA0 Output 80
OUT4 O3 LTCA2 Output 4
B10 P6.1 I/O0 F/ Port 6 General Purpose I/O Line 1
IN15 I PU LTCA2 Input 15
FCLP0A O1 MSC0 Clock Output Positive A
OUT81 O2 GPTA0 Output 81
OUT5 O3 LTCA2 Output 5
A9 P6.2 I/O0 F/ Port 6 General Purpose I/O Line 2
IN24 I PU LTCA2 Input 24
SON0 O1 MSC0 Serial Data Output Negative
OUT82 O2 GPTA0 Output 82
OUT6 O3 LTCA2 Output 6
B9 P6.3 I/O0 F/ Port 6 General Purpose I/O Line 3
IN25 I PU LTCA2 Input 25
SOP0A O1 MSC0 Serial Data Output Positive A
OUT83 O2 GPTA0 Output 83
OUT7 O3 LTCA2 Output 7
Port 7
U16 P7.0 I/O0 A2/ Port 7 General Purpose I/O Line 0
AD0 I/O PU EBU Address/Data Bus Line 0
OUT32 O1 GPTA0 Output 32
Reserved O2 -
Reserved O3 -

Data Sheet 3-24 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
Y14 P7.1 I/O0 A2/ Port 7 General Purpose I/O Line 1
AD1 I/O PU EBU Address/Data Bus Line 1
OUT33 O1 GPTA0 Output 33
Reserved O2 -
Reserved O3 -
R17 P7.2 I/O0 A2/ Port 7 General Purpose I/O Line 2
AD2 I/O PU EBU Address/Data Bus Line 2
OUT34 O1 GPTA0 Output 34
Reserved O2 -
Reserved O3 -
U14 P7.3 I/O0 A2/ Port 7 General Purpose I/O Line 3
AD3 I/O PU EBU Address/Data Bus Line 3
OUT35 O1 GPTA0 Output 35
Reserved O2 -
Reserved O3 -
T14 P7.4 I/O0 A2/ Port 7 General Purpose I/O Line 4
AD4 I/O PU EBU Address/Data Bus Line 4
OUT36 O1 GPTA0 Output 36
Reserved O2 -
Reserved O3 -
Y15 P7.5 I/O0 A2/ Port 7 General Purpose I/O Line 5
AD5 I/O PU EBU Address/Data Bus Line 5
OUT37 O1 GPTA0 Output 37
Reserved O2 -
Reserved O3 -
W14 P7.6 I/O0 A2/ Port 7 General Purpose I/O Line 6
AD6 I/O PU EBU Address/Data Bus Line 6
OUT38 O1 GPTA0 Output 38
Reserved O2 -
Reserved O3 -

Data Sheet 3-25 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
T15 P7.7 I/O0 A2/ Port 7 General Purpose I/O Line 7
AD7 I/O PU EBU Address/Data Bus Line 7
OUT39 O1 GPTA0 Output 39
Reserved O2 -
Reserved O3 -
U15 P7.8 I/O0 A2/ Port 7 General Purpose I/O Line 8
AD8 I/O PU EBU Address/Data Bus Line 8
OUT40 O1 GPTA0 Output 40
Reserved O2 -
Reserved O3 -
W15 P7.9 I/O0 A2/ Port 7 General Purpose I/O Line 9
AD9 I/O PU EBU Address/Data Bus Line 9
OUT41 O1 GPTA0 Output 41
Reserved O2 -
Reserved O3 -
Y17 P7.10 I/O0 A2/ Port 7 General Purpose I/O Line 10
AD10 I/O PU EBU Address/Data Bus Line 10
OUT42 O1 GPTA0 Output 42
Reserved O2 -
Reserved O3 -
W17 P7.11 I/O0 A2/ Port 7 General Purpose I/O Line 11
AD11 I/O PU EBU Address/Data Bus Line 11
OUT43 O1 GPTA0 Output 43
Reserved O2 -
Reserved O3 -
Y18 P7.12 I/O0 A2/ Port 7 General Purpose I/O Line 12
AD12 I/O PU EBU Address/Data Bus Line 12
OUT44 O1 GPTA0 Output 44
Reserved O2 -
Reserved O3 -

Data Sheet 3-26 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
W18 P7.13 I/O0 A2/ Port 7 General Purpose I/O Line 13
AD13 I/O PU EBU Address/Data Bus Line 13
OUT45 O1 GPTA0 Output 45
Reserved O2 -
Reserved O3 -
Y19 P7.14 I/O0 A2/ Port 7 General Purpose I/O Line 14
AD14 I/O PU EBU Address/Data Bus Line 14
OUT46 O1 GPTA0 Output 46
Reserved O2 -
Reserved O3 -
V20 P7.15 I/O0 A2/ Port 7 General Purpose I/O Line 15
AD15 I/O PU EBU Address/Data Bus Line 15
OUT47 O1 GPTA0 Output 47
Reserved O2 -
Reserved O3 -
Port 8
U19 P8.0 I/O0 A2/ Port 8 General Purpose I/O Line 0
Reserved O1 PU -
OUT48 O2 GPTA0 Output 48
OUT95 O3 LTCA2 Output 95
A16 O EBU Address Bus Line Output 16
U20 P8.1 I/O0 A2/ Port 8 General Purpose I/O Line 1
Reserved O1 PU -
OUT49 O2 GPTA0 Output 49
OUT96 O3 LTCA2 Output 96
A17 O EBU Address Bus Line Output 17

Data Sheet 3-27 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
T19 P8.2 I/O0 A2/ Port 8 General Purpose I/O Line 2
Reserved O1 PU -
OUT50 O2 GPTA0 Output 50
OUT97 O3 LTCA2 Output 97
A18 O EBU Address Bus Line Output 18
T20 P8.3 I/O0 A2/ Port 8 General Purpose I/O Line 3
Reserved O1 PU -
OUT51 O2 GPTA0 Output 51
OUT98 O3 LTCA2 Output 98
A19 O EBU Address Bus Line Output 19
N20 P8.4 I/O0 A2/ Port 8 General Purpose I/O Line 4
Reserved O1 PU -
OUT52 O2 GPTA0 Output 52
OUT99 O3 LTCA2 Output 99
A20 O EBU Address Bus Line Output 20
R20 P8.5 I/O0 A2/ Port 8 General Purpose I/O Line 5
Reserved O1 PU -
OUT53 O2 GPTA0 Output 53
OUT100 O3 LTCA2 Output 100
CS0 O EBU Chip Select Output 0
R19 P8.6 I/O0 A2/ Port 8 General Purpose I/O Line 6
Reserved O1 PU -
OUT54 O2 GPTA0 Output 54
OUT101 O3 LTCA2 Output 101
CS1 O EBU Chip Select Output 1
P20 P8.7 I/O0 A2/ Port 8 General Purpose I/O Line 7
Reserved O1 PU -
OUT55 O2 GPTA0 Output 55
OUT102 O3 LTCA2 Output 102
CS2 O EBU Chip Select Output 2

Data Sheet 3-28 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
P19 P8.8 I/O0 A2/ Port 8 General Purpose I/O Line 8
Reserved O1 PU -
OUT56 O2 GPTA0 Output 56
OUT103 O3 LTCA2 Output 103
CS3 O EBU Chip Select Output 3
P17 P8.9 I/O0 A2/ Port 8 General Purpose I/O Line 9
Reserved O1 PU -
OUT57 O2 GPTA0 Output 57
OUT104 O3 LTCA2 Output 104
BC0 O EBU Byte Control Line Output 0
P16 P8.10 I/O0 A2/ Port 8 General Purpose I/O Line 10
Reserved O1 PU -
OUT58 O2 GPTA0 Output 58
OUT105 O3 LTCA2 Output 105
BC1 O EBU Byte Control Line Output 1
N19 P8.11 I/O0 A2/ Port 8 General Purpose I/O Line 11
Reserved O1 PU -
OUT59 O2 GPTA0 Output 59
OUT106 O3 LTCA2 Output 106
RD O EBU Read Control Line
N17 P8.12 I/O0 A2/ Port 8 General Purpose I/O Line 12
Reserved O1 PU -
OUT60 O2 GPTA0 Output 60
OUT107 O3 LTCA2 Output 107
RD/WR O EBU Write Control Line
N16 P8.13 I/O0 A2/ Port 8 General Purpose I/O Line 13
Reserved O1 PU -
OUT61 O2 GPTA0 Output 61
OUT108 O3 LTCA2 Output 108
ADV O EBU Address Valid Line

Data Sheet 3-29 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
M17 P8.14 I/O0 A1/ Port 8 General Purpose I/O Line 14
WAIT I PU EBU Wait Line
Reserved O1 -
OUT62 O2 GPTA0 Output 62
OUT109 O3 LTCA2 Output 109
Port 9
G4 P9.0 I/O0 A1/ Port 9 General Purpose I/O Line 0
RXDCAN2 I PU CAN Node 2 Receiver Input
Reserved O1 -
OUT80 O2 GPTA0 Output 80
OUT80 O3 LTCA2 Output 80
H4 P9.1 I/O0 A2/ Port 9 General Purpose I/O Line 1
Reserved I PU -
TXDCAN2 O1 CAN Node 2 Transmitter Output
OUT81 O2 GPTA0 Output 81
OUT81 O3 LTCA2 Output 81
J5 P9.2 I/O0 A1/ Port 9 General Purpose I/O Line 2
Reserved I PU -
Reserved O1 -
OUT82 O2 GPTA0 Output 82
OUT82 O3 LTCA2 Output 82
J4 P9.3 I/O0 A1/ Port 9 General Purpose I/O Line 3
Reserved I PU -
Reserved O1 -
OUT83 O2 GPTA0 Output 83
OUT83 O3 LTCA2 Output 83

Data Sheet 3-30 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
K4 P9.4 I/O0 A1/ Port 9 General Purpose I/O Line 4
Reserved I PU -
Reserved O1 -
OUT84 O2 GPTA0 Output 84
OUT84 O3 LTCA2 Output 84
K5 P9.5 I/O0 A1/ Port 9 General Purpose I/O Line 5
Reserved I PU -
Reserved O1 -
OUT85 O2 GPTA0 Output 85
OUT85 O3 LTCA2 Output 85
L4 P9.6 I/O0 A1/ Port 9 General Purpose I/O Line 6
Reserved I PU -
Reserved O1 -
OUT86 O2 GPTA0 Output 86
OUT86 O3 LTCA2 Output 86
L5 P9.7 I/O0 A1/ Port 9 General Purpose I/O Line 7
Reserved I PU -
Reserved O1 -
OUT87 O2 GPTA0 Output 87
OUT87 O3 LTCA2 Output 87
Port 10
D6 P10.0 I/O0 A1+/ Port 10 General Purpose I/O Line 0
MRST2B I PU SSC2 Master Receive Input (Master Mode)
MRST2 O1 SSC2 Master Transmit Input (Slave Mode)
EVTO0 O2 MCDS Event Output 0
Reserved O3 -

Data Sheet 3-31 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
E6 P10.1 I/O0 A1+/ Port 10 General Purpose I/O Line 1
Reserved I PU -
MTSR2 O1 SSC0 Slave Receive Input (Slave Mode)
EVTO1 O2 MCDS Event Output 1
Reserved O3 -
D5 P10.2 I/O0 A1+/ Port 10 General Purpose I/O Line 2
SCLK2B I PU SSC0 Clock Input (Slave Mode)
SCLK2 O1 SSC0 Clock Output (Master Mode)
EVTO2 O2 MCDS Event Output 2
Reserved O3 -
B5 P10.3 I/O0 A1+/ Port 10 General Purpose I/O Line 3
SLSI2B I PU SSC2 Slave Select Input B
SLSO20 O1 SSC2 Slave Select Output 0
EVTO3 O2 MCDS Event Output 3
Reserved O3 LTCA2 Output 83
A5 P10.4 I/O0 A1+/ Port 10 General Purpose I/O Line 4
Reserved I PU -
SLSO21 O1 SSC2 Slave Select Output 1
Reserved O2 GPTA0 Output 84
Reserved O3 -
B4 P10.5 I/O0 A1+/ Port 10 General Purpose I/O Line 5
Reserved I PU -
SLSO22 O1 SSC2 Slave Select Output 0
Reserved O2 GPTA0 Output 85
Reserved O3 -
A4 P10.6 I/O0 A1+/ Port 10 General Purpose I/O Line 6
Reserved I PU -
SLSO23 O1 SSC2 Slave Select Output 3
SLSOAND03 O2 SSC0 AND SSC2 Slave Select Output 3
Reserved O3 -

Data Sheet 3-32 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
B3 P10.7 I/O0 A1+/ Port 10 General Purpose I/O Line 7
Reserved I PU -
SLSO24 O1 SSC2 Slave Select Output 4
SLSOAND04 O2 SSC1 AND SSC2 Slave Select Output 4
Reserved O3 -
A3 P10.8 I/O0 A1/ Port 10 General Purpose I/O Line 8
Reserved I PU -
Reserved O1 -
Reserved O2 -
Reserved O3 -
A2 P10.9 I/O0 A1/ Port 10 General Purpose I/O Line 9
Reserved I PU -
Reserved O1 -
Reserved O2 -
Reserved O3 -
C1 P10.10 I/O0 A1/ Port 10 General Purpose I/O Line 10
RXDCAN2 I PU CAN Node 2 Receiver Input
Reserved O1 -
Reserved O2 -
Reserved O3 -
D2 P10.11 I/O0 A1/ Port 10 General Purpose I/O Line 11
Reserved I PU -
Reserved O1 -
Reserved O2 -
Reserved O3 -
E4 P10.12 I/O0 A1/ Port 10 General Purpose I/O Line 12
Reserved I PU -
Reserved O1 -
Reserved O2 -
Reserved O3 -

Data Sheet 3-33 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
F5 P10.13 I/O0 A1/ Port 10 General Purpose I/O Line 13
Reserved I PU -
Reserved O1 -
Reserved O2 -
Reserved O3 -
Analog Input Port
Y9 AN0 I D Analog Input 0
W9 AN1 I D Analog Input 1
T9 AN2 I D Analog Input 2
U8 AN3 I D Analog Input 3
Y8 AN4 I D Analog Input 4
W8 AN5 I D Analog Input 5
T8 AN6 I D Analog Input 6
T2 AN7 I D Analog Input 7
U7 AN8 I D Analog Input 8
Y6 AN9 I D Analog Input 9
Y5 AN10 I D Analog Input 10
Y4 AN11 I D Analog Input 11
Y3 AN12 I D Analog Input 12
Y2 AN13 I D Analog Input 13
W2 AN14 I D Analog Input 14
U5 AN15 I D Analog Input 15
W3 AN16 I D Analog Input 16
W5 AN17 I D Analog Input 17
W4 AN18 I D Analog Input 18
W6 AN19 I D Analog Input 19
W1 AN20 I D Analog Input 20
U4 AN21 I D Analog Input 21
V2 AN22 I D Analog Input 22
V1 AN23 I D Analog Input 23

Data Sheet 3-34 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
T5 AN24 I D Analog Input 24
T4 AN25 I D Analog Input 25
U2 AN26 I D Analog Input 26
U1 AN27 I D Analog Input 27
T1 AN28 I D Analog Input 28
R5 AN29 I D Analog Input 29
R4 AN30 I D Analog Input 30
R2 AN31 I D Analog Input 31
R1 AN32 I D Analog Input 32
P5 AN33 I D Analog Input 33
P4 AN34 I D Analog Input 34
P1 AN35 I D Analog Input 35
Y7 VDDM - - ADC Analog Part Power Supply (3.3V - 5V)
W7 VSSM - - ADC Analog Part Ground
U6 VAREF0 - - ADC0 Reference Voltage
T7 VAREF1 - - ADC1 Reference Voltage
T6 VAGND0 - - ADC Reference Ground
N1 VDDMF - - FADC Analog Part Power Supply (3.3V)
N2 VDDAF - - FADC Analog Part Logic Power Supply (1.3V)
P2 VSSMF - - FADC Analog Part Ground
P2 VSSAF - - FADC Analog Part Ground
N4 VFAREF - - FADC Reference Voltage
N5 VFAGND - - FADC Reference Ground

Data Sheet 3-35 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
G8, VDD - - Digital Core Power Supply (1.3V)
G13,
H7,
H14,
N7,
N14,
P8,
P13,
R16,
T17,
V19,
W20
B1, VDDP - - Port Power Supply (3.3V)
B6,
B11,
B20,
C2,
C19,
G2,
M2,
M19,
W10,
W16
M4, VDDE(SB) - - Emulation Stand-by SRAM Power Supply
M5 (1.3V) (Emulation device only)
Note: This pin is N.C. in a productive device.

Data Sheet 3-36 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
A6, VSSP - - Digital Ground
A11,
A20,
B2,
B19,
D4,
D17,
E5,
E16,
G1,
M1,
M20,
Y10,
Y16
G9, VSS - - Digital Ground
G10,
G11,
G12
H9, VSS - - Digital Ground
H10,
H11,
H12
J7, VSS - - Digital Ground
J8,
J10,
J11,
J13,
J14
K7, VSS - - Digital Ground
K8,
K9,
K10,
K11,
K12,
K13,
K14

Data Sheet 3-37 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
L7, VSS - - Digital Ground
L8,
L9,
L10,
L11,
L12,
L13,
L14
M7, VSS - - Digital Ground
M8,
M10,
M11,
M13,
M14
N9, VSS - - Digital Ground (cont´d)
N10,
N11,
N12
P9, VSS - - Digital Ground (cont´d)
P10,
P11,
P12
T16, VSS - - Digital Ground (cont´d)
U17,
W19,
Y20
K19 VDDOSC - - Main Oscillator and PLL Power Supply (1.3V)
H20 VDDOSC3 - - Main Oscillator Power Supply (3.3V)
K17 VDDPF - - Flexray Oscillator and PLL Power Supply
(1.3V)
J17 VDDPF3 - - Flexray Oscillator Power Supply (3.3V)
K20 VSSOSC - - Main Oscillator and PLL Ground
D13, VDDFL3 - - Power Supply for Flash (3.3V)
D14
J20 XTAL1 I Oscillator/PLL/Clock Generator Input
J19 XTAL2 O Oscillator/PLL/Clock Generator Output

Data Sheet 3-38 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

Table 3-1 Pin Definitions and Functions (PG-LFBGA-292) (cont’d)

Pin Symbol Ctrl. Type Function
H19 TDI I A2/ JTAG Serial Data Input
BRKIN I PU OCDS Break Input (Alternate Input)
BRKOUT O OCDS Break Output (Alternate Output)
H17 TMS I A2/ JTAG State Machine Control Input
DAP1 I/O PD Device Access Port Line 1
G20 TDO I/O A2/ JTAG Serial Data Output
DAP2 I/O PU Device Access Port Line 2
BRKIN I OCDS Break Input (Alternate Input)
BRKOUT O OCDS Break Output (Alternate Output)
G19 TRST I A1/ JTAG Reset Input
PD
F20 TCK I A1/ JTAG Clock Input
DAP0 I PD Device Access Port Line 0
F19 TESTMODE I PU Test Mode Select Input
E19 ESR1 I/O A2/ External System Request Reset Input 1
PD
E20 PORST I PD Power On Reset Input
D20 ESR0 I/O A2 External System Request Reset Input 0
Default configuration during and after reset is
open-drain driver. The driver drives low during
power-on reset.
A1, N.C. - - Not connected. These pins are reserved for
Y1 future extension and shall not be connected
externally

Legend for Table 3-1

Column “Ctrl.”:
I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X00B
O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2)
O3 = Output with IOCR bit field selection PCx = 1X11(ALT3)
Column “Type”:

Data Sheet 3-39 V 1.0, 2012-03

,
 TC1784

PinningTC1784 Pin Configuration

A1 = Pad class A1 (LVTTL)

A1+ = Pad class A1+ (LVTTL)
A2 = Pad class A2 (LVTTL)
F = Pad class F (LVDS/CMOS)
D = Pad class D (ADC)
I = Pad class I (LVTTL)
PU = with pull-up device connected during reset (PORST = 0)
PD = with pull-down device connected during reset (PORST = 0)
TR = tri-state during reset (PORST = 0)

Data Sheet 3-40 V 1.0, 2012-03

,
 TC1784

Identification Registers

4 Identification Registers
The Identification Registers uniquely identify the whole device.

Table 2 SAK-TC1784F-320F180EL Identification Registers

Short Name Value Address Stepping
CBS_JDPID 0000 6350H F000 0408H BA
CBS_JTAGID 1018 E083H F000 0464H BA
SCU_CHIPID 0500 9610H F000 0640H BA
SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA

Table 3 SAK-TC1784N-320F180EL Identification Registers

Short Name Value Address Stepping
CBS_JDPID 0000 6350H F000 0408H BA
CBS_JTAGID 1018 E083H F000 0464H BA
SCU_CHIPID 0500 A310H F000 0640H BA
SCU_MANID 0000 1820H F000 0644H BA
SCU_RTID 0000 0000H F000 0648H BA

Data Sheet 41 V 1.0, 2012-03

 TC1784

Identification Registers

Data Sheet 42 V 1.0, 2012-03

 TC1784

Electrical ParametersGeneral Parameters

5 Electrical Parameters
This specification provides all electrical parameters of the TC1784.

5.1 General Parameters

5.1.1 Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC1784
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with an two-letter abbreviation in
column “Symbol”:
• CC
Such parameters indicate Controller Characteristics which are a distinctive feature of
the TC1784 and must be regarded for a system design.
• SR
Such parameters indicate System Requirements which must provided by the
microcontroller system in which the TC1784 designed in.

Data Sheet 43 V 1.0, 2012-03

 TC1784

Electrical ParametersGeneral Parameters

5.1.2 Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.

Table 4 Pad Driver and Pad Classes Overview

Class Power Type Sub Class Speed Load Leakage Termination
Supply Grade 150oC
A 3.3 V LVTTL A1 6 MHz 100 pF 500 nA No
I/O, (e.g. GPIO)
LVTTL A1+ 25 50 pF 1 μA Series
outputs (e.g. serial MHz termination
I/Os) recommended
A2 40 50 pF 3 μA Series
(e.g. serial MHz termination
I/Os) recommended
F 3.3 V LVDS – 50 – – Parallel
MHz termination,
100 Ω ± 10% 1)
CMOS – 6 MHz 50 pF –
DE 5V ADC – – – –
I 3.3 V LVTTL – – – –
(input
only)
1) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or
properly terminated with the differential parallel termination of 100 Ω ± 10%.

Data Sheet 44 V 1.0, 2012-03

 TC1784

Electrical ParametersGeneral Parameters

5.1.3 Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.

Table 5 Absolute Maximum Rating Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Con
dition
Storage temperature TST SR -65 – 150 °C –
Voltage at 1.3 V power supply VDD SR – – 2.0 V –
pins with respect to VSS
Voltage at 3.3 V power supply VDDP – – 4.33 V –
pins with respect to VSS SR
Voltage at 5 V power supply VDDM SR – – 7.0 V –
pins with respect to VSS
Voltage on any Class A input VIN SR -0.7 – VDDP + 0.5 V Whatever
pin and dedicated input pins or max. 4.33 is lower
with respect to VSS
Voltage on any Class D VAIN -0.6 – 7.0 V –
analog input pin with respect VAREFx
to VAGND0 SR
Voltage on any shared Class VAINF -0.6 – 7.0 V –
D analog input pin with SR
respect to VSSAF, if the FADC
is switched through to the pin.
Input current on any pin IIN -10 – +10 mA –
during overload condition
Absolute maximum sum of all IIN -25 – +25 mA –
input circuit currents for one
port group during overload
condition1)
Absolute maximum sum of all ΣIIN -200 – 200 mA –
input circuit currents during
overload condition
1) The port groups are defined in Table 10.

Data Sheet 45 V 1.0, 2012-03

 TC1784

Electrical ParametersGeneral Parameters

5.1.4 Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 6 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
• full operation life-time (24000 h) is not exceeded
• Operating Conditions are met for
– pad supply levels (VDDP or VDDM)
– temperature
If a pin current is out of the Operating Conditions but within the overload parameters,
then the parameters functionality of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.

Table 6 Overload Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Con
dition
Input current on any digital pin IIN -5 – +5 mA –
during overload condition
except LVDS pins
Input current on LVDS pins IINLVDS -3 – +3 mA –
Absolute sum of all input IING -20 – +20 mA –
circuit currents for one port
group during overload
condition1)
Input current on analog pins IINANA -3 – +3 mA –
Absolute sum of all analog IINSAS -15 – +15 mA –
input currents for analog
inputs of a single ADC during
overload condition
Absolute sum of all input ΣIINS -100 – 100 mA –
circuit currents during
overload condition
1) The port groups are defined in Table 10.

Note: FADC input pins count as analog pin as they are overlayed with an ADC pins.

Data Sheet 46 V 1.0, 2012-03

 TC1784

Electrical ParametersGeneral Parameters

Table 7 PN-Junction Characterisitics for positive Overload

Pad Type IIN = 3 mA IIN = 5 mA
A1 / A1+ / F UIN = VDDP + 0.6 V UIN = VDDP + 0.7 V
A2 UIN = VDDP + 0.5 V UIN = VDDP + 0.6 V
LVDS UIN = VDDP + 0.7 V -
D UIN = VDDM + 0.6 V -

Table 8 PN-Junction Characterisitics for negative Overload

Pad Type IIN = -3 mA IIN = -5 mA
A1 / A1+ / F UIN = VSS - 0.6 V UIN = VSS - 0.7 V
A2 UIN = VSS - 0.5 V UIN = VSS - 0.6 V
LVDS UIN = VSS - 0.7 V -
D UIN = VSSM - 0.6 V -

Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery without having
any negative reliability impact on the operational life-time.

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5.1.5 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the TC1784. All parameters specified in the following tables
refer to these operating conditions, unless otherwise noticed.
Digital supply voltages applied to the TC1784 must be static regulated voltages which
allow a typical voltage swing of ± 5 %.
All parameters specified in the following tables (Table 11 and following) refer to these
operating conditions (Table 9), unless otherwise noticed in the Note / Test Condition
column.
The Extended Range Operating Conditions did not increase area of validity of the
parameters defined in table 9 and later.

Table 9 Operating Conditions Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Overload coupling factor KOVAN − − 0.0001 IOV≤ 0 mA;

for analog inputs, negative CC IOV≥ -1 mA;
analog
pad= 5.0 V
Overload coupling factor KOVAP − − 0.0000 IOV≤ 3 mA;
for analog inputs, positive CC 1 IOV≥ 0 mA;
analog
pad= 5.0 V
CPU Frequency fCPU SR − − 180 MHz
FPI bus frequency fFPI SR − − 90 MHz
LMB frequency fLMB CC − − 180 MHz
PCP Frequency fPCP SR − − 180 MHz
Inactive device pin current IID SR -1 − 1 mA All power
supply
voltagesVDDx =
0
Short circuit current of ISC SR -5 − 5 mA
digital outputs1)
Absolute sum of short ΣISC_D − − 100 mA
circuit currents of the CC
device

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Table 9 Operating Conditions Parameters (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
Absolute sum of short ΣISC_PG − − 20 mA
circuit currents per pin CC
group
Ambient Temperature TA SR -40 − 125 °C
Junction temperature TJ SR -40 − 150 °C
Core Supply Voltage VDD SR 1.235 1.3 1.3652) V
Flash supply voltage 3.3V VDDFL3 3.13 3.3 3.474) V
SR
ADC analog supply VDDM 3.13 3.3 5.53) V
voltage SR
Oscillator core supply VDDOSC 1.235 1.3 1.3652) V
voltage SR
Oscillator 3.3V supply VDDOSC3 3.05 3.3 3.474) V
voltage SR
E-Ray PLL core supply VDDPF 1.235 1.3 1.3652) V
voltage SR
E-Ray PLL 3.3V supply VDDPF3 3.05 3.3 3.474) V
voltage SR
Digital supply voltage for VDDP SR 3.13 3.3 3.47 4) V
IO pads
VDDP voltage to ensure VDDPPA 0.65 − − V
defined pad states5) CC
Digital ground voltage VSS SR 0 − − V
Analog ground voltage for VSSM SR -0.1 0 0.1 V
VDDM
Analog core supply VDDAF 1.235 1.3 1.3652) V
SR
FADC / ADC analog VDDMF 3.13 3.3 3.474) V
supply voltage SR
Analog ground voltage for VSSAF -0.1 0 0.1 V
VDDMF SR
1) Applicable for digital outputs.

Data Sheet 49 V 1.0, 2012-03

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2) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
3) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
4) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
5) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-
up/power-down of VDDP.

Extended Range Operating Conditions

The following extended operating conditions are defined:
• 1.3V + 5% < VDD / VDDPF / VDDOSC / VDDAF < 1.3V + 7.5% (overvoltage condition):
– limited to 10000 hour duration cumulative in lifetime, due to the reliability reduction
of the chip caused by the overvoltage stress.
• 1.3V + 7.5% < VDD / VDDOSC / VDDAF < 1.3V + 10% (overvoltage condition):
– limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction
of the chip caused by the overvoltage stress.
• VDDP / VDDOSC3 / VDDFL3 / VDDMF< 3.3 V ± 10%
– 3.3V + 5% < VDDP / VDDOSC3 / VDDFL3 / VDDMF< 3.3V + 10%
(overvoltage condition):
limited to 1000 hour duration cumulative in lifetime, due to the reliability reduction
of the chip caused by the overvoltage stress.
– 3.3V - 10% < VDDP / VDDOSC3 / VDDFL3 / VDDMF< 3.3 V − 5%
(undervoltage condition):
-reduces GPIO pads performance

Table 10 Pin Groups for Overload / Short-Circuit Current Sum Parameter

Group Pins
1 P5.[7:2], P5.15
2 P5.[9:8]
3 P5.[11:10]
4 P5.[14:12]
5 P1.[14:12], P2.0
6 P2.[4:1]
7 P2.[7:5]
8 P4.[2:0]

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Table 10 Pin Groups for Overload / Short-Circuit Current Sum Parameter

Group Pins
9 P4.3
10 P1.2, P1.8
11 P1.[10:9]
12 P1.3, P1.11
13 P1.[7:4]
14 P1.[1:0], P1.15
15 P3.[8:5], P3.[3:2]
16 P3.[1:0], P3.4, P3.[10:9], P3.[15:14]
17 P0.[1:0], P3.[13:11]
18 P0.[3:2], P0.[9:8]
19 P0.[11:10]
20 P6.[3:0]
21 P2.[13:8]
22 P0.[5:4], P0.[13:12]
23 P0.[7:6], P0.[15:14], P5.[1:0]

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5.2 DC Parameters

5.2.1 Input/Output Pins

Table 11 Standard_Pads Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Pin capacitance (digital CIO CC − − 10 pF TA= 25 °C;

inputs/outputs) f= 1 MHz
Pull-down current |IPDL| − − 150 μA Vi≥ 0.6 x VDDP V
CC 10 − − μA Vi≥ 0.36 x
VDDP V
Pull-Up current |IPUH| 10 − − μA Vi≤ 0.6 x VDDP V
CC − − 100 μA Vi≤ 0.36 x
VDDP V
Spike filter always blocked tSF1 CC − − 10 ns only PORST pin
pulse duration
Spike filter pass-through tSF2 CC 100 − − ns only PORST pin
pulse duration

Table 12 Standard_Pads Class_A1

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Input Hysteresis for A1 HYSA1 0.1 x − − V

pads 1) CC VDDP
Input Leakage Current IOZA1 -500 − 500 nA Vi≥ 0 V;
Class A1 CC Vi≤ VDDP V
Ratio Vil/Vih, A1 pads VILA1 / 0.6 − −
VIHA1
CC
On-Resistance of the RDSONW − 450 600 Ohm IOH> -0.5 mA;
class A1 pad, weak driver CC P_MOS
− 210 340 Ohm IOL< 0.5 mA;
N_MOS

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Table 12 Standard_Pads Class_A1 (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
On-Resistance of the RDSONM − − 155 Ohm IOH> -2 mA;
class A1 pad, medium CC P_MOS
driver − − 110 Ohm IOL< 2 mA;
N_MOS
Fall time, pad type A1 tFA1 CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 140 ns CL= 150 pF; pin
out
driver= medium
− − 550 ns CL= 150 pF; pin
out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak

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Table 12 Standard_Pads Class_A1 (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
Rise time, pad type A1 tRA1 CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 140 ns CL= 150 pF; pin
out
driver= medium
− − 550 ns CL= 150 pF; pin
out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak
Input high voltage class VIHA1 0.6 x − min(V V
A1 pads SR VDDP DDP+
0.3,3.6
)
Input low voltage class A1 VILA1 SR -0.3 − 0.36 x V
pads VDDP

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Table 12 Standard_Pads Class_A1 (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
Output voltage high class VOHA1 VDDP - − − V IOH≥ -1.4 mA;
A1 pads CC 0.4 pin out
driver= medium
2.4 − − V IOH≥ -2 mA; pin
out
driver= medium
VDDP - − − V IOH≥ -400 μA;
0.4 pin out
driver= weak
2.4 − − V IOH≥ -500 μA;
pin out
driver= weak
Output voltage low class VOLA1 − − 0.4 V IOL≤ 2 mA; pin
A1 pads CC out
driver= medium
− − 0.4 V IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.

Table 13 Standard_Pads Class_A1+

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Input Hysteresis for A1+ HYSA1 0.1 x − − V

pads 1) + CC VDDP
Input Leakage Current IOZA1+ -1000 − 1000 nA
Class A1+ CC
On-Resistance of the RDSONW − 450 600 Ohm IOH> -0.5 mA;
class A1+ pad, weak CC P_MOS
driver − 210 340 Ohm IOL< 0.5 mA;
N_MOS

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Table 13 Standard_Pads Class_A1+ (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
On-Resistance of the RDSONM − − 155 Ohm IOH> -2 mA;
class A1+ pad, medium CC P_MOS
driver − − 110 Ohm IOL< 2 mA;
N_MOS
On-Resistance of the RDSON1+ − − 100 Ohm IOH> -2 mA;
class A1+ pad, strong CC P_MOS
driver − − 80 Ohm IOL< 2 mA;
N_MOS
Fall time, pad type A1+ tFA1+ CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 28 ns CL= 50 pF;
edge= slow ;
pin out
driver= strong
− − 16 ns CL= 50 pF;
edge= soft ; pin
out
driver= strong
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 140 ns CL= 150 pF; pin
out
driver= medium
− − 550 ns CL= 150 pF; pin
out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak

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Table 13 Standard_Pads Class_A1+ (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Rise time, pad type A1+ tRA1+ CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 28 ns CL= 50 pF;
edge= slow ;
pin out
driver= strong
− − 16 ns CL= 50 pF;
edge= soft ; pin
out
driver= strong
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 140 ns CL= 150 pF; pin
out
driver= medium
− − 550 ns CL= 150 pF; pin
out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak
Input high voltage, Class VIHA1+ 0.6 x − min(V V
A1+ pads SR VDDP DDP+
0.3,3.6
)
Input low voltage Class VILA1+ -0.3 − 0.36 x V
A1+ pads SR VDDP
Ratio Vil/Vih, A1+ pads VILA1+ / 0.6 − −
VIHA1+
CC

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Table 13 Standard_Pads Class_A1+ (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
Output voltage high class VOHA1+ VDDP - − − V IOH≥ -1.4 mA;
A1+ pads CC 0.4 pin out
driver= medium
VDDP - − − V IOH≥ -1.4 mA;
0.4 pin out
driver= strong
2.4 − − V IOH≥ -2 mA; pin
out
driver= medium
2.4 − − V IOH≥ -2 mA; pin
out
driver= strong
VDDP - − − V IOH≥ -400 μA;
0.4 pin out
driver= weak
2.4 − − V IOH≥ -500 μA;
pin out
driver= weak
Output voltage low class VOLA1+ − − 0.4 V IOL≤ 2 mA; pin
A1+ pads CC out
driver= medium
− − 0.4 V IOL≤ 2 mA; pin
out
driver= strong
− − 0.4 V IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.

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Table 14 Standard_Pads Class_A2

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Input Hysteresis for A2 HYSA2 0.1 x − − V

pads 1) CC VDDP
Input Leakage current IOZA2 -6000 − 6000 nA Vi< VDDP / 2 -
Class A2 CC 1 V; Vi> VDDP / 2
+ 1 V; Vi≥ 0 V;
Vi≤ VDDP V
-3000 − 3000 nA Vi> VDDP / 2 -
1 V; Vi< VDDP / 2
+1V
Ratio Vil/Vih, A2 pads VILA2 / 0.6 − −
VIHA2
CC
On-Resistance of the RDSONW − 450 600 Ohm IOH> -0.5 mA;
class A2 pad, weak driver CC P_MOS
− 210 340 Ohm IOL< 0.5 mA;
N_MOS
On-Resistance of the RDSONM − − 155 Ohm IOH> -2 mA;
class A2 pad, medium CC P_MOS
driver − − 110 Ohm IOL< 2 mA;
N_MOS
On-Resistance of the RDSON2 − − 28 Ohm IOH> -2 mA;
class A2 pad, strong driver CC P_MOS
− − 22 Ohm IOL< 2 mA;
N_MOS

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Table 14 Standard_Pads Class_A2 (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
Fall time, pad type A2 tFA2 CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 7 ns CL= 50 pF;
edge= medium
; pin out
driver= strong
− − 10 ns CL= 50 pF;
edge= medium-
minus ; pin out
driver= strong
− − 3.7 ns CL= 50 pF;
edge= sharp ;
pin out
driver= strong
− − 5 ns CL= 50 pF;
edge= sharp-
minus ; pin out
driver= strong
− − 16 ns CL= 50 pF;
edge= soft ; pin
out
driver= strong
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 7.5 ns CL= 100 pF;
edge= sharp ;
pin out
driver= strong
− − 140 ns CL= 150 pF; pin
out
driver= medium

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Table 14 Standard_Pads Class_A2 (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
− − 550 ns CL= 150 pF; pin
out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak

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Table 14 Standard_Pads Class_A2 (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
Rise time, pad type A2 tRA2 CC − − 150 ns CL= 20 pF; pin
out
driver= weak
− − 7.0 ns CL= 50 pF;
edge= medium
; pin out
driver= strong
− − 10 ns CL= 50 pF;
edge= medium-
minus ; pin out
driver= strong
− − 3.7 ns CL= 50 pF;
edge= sharp ;
pin out
driver= strong
− − 5 ns CL= 50 pF;
edge= sharp-
minus ; pin out
driver= strong
− − 16 ns CL= 50 pF;
edge= soft ; pin
out
driver= strong
− − 50 ns CL= 50 pF; pin
out
driver= medium
− − 7.5 ns CL= 100 pF;
edge= sharp ;
pin out
driver= strong
− − 140 ns CL= 150 pF; pin
out
driver= medium

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Table 14 Standard_Pads Class_A2 (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
− − 550 ns CL= 150 pF; pin
out
driver= weak
− − 18000 ns CL= 20000 pF;
pin out
driver= medium
− − 65000 ns CL= 20000 pF;
pin out
driver= weak
Input high voltage, class VIHA2 0.6 x − min(V V
A2 pads SR VDDP DDP +
0.3,
3.6)
Input low voltage Class A2 VILA2 SR -0.3 − 0.36 x V
pads VDDP
Output voltage high class VOHA2 VDDP - − − V IOH≥ -1.4 mA;
A2 pads CC 0.4 pin out
driver= medium
VDDP - − − V IOH≥ -1.4 mA;
0.4 pin out
driver= strong
2.4 − − V IOH≥ -2 mA; pin
out
driver= medium
2.4 − − V IOH≥ -2 mA; pin
out
driver= strong
VDDP - − − V IOH≥ -400 μA;
0.4 pin out
driver= weak
2.4 − − V IOH≥ -500 μA;
pin out
driver= weak

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Table 14 Standard_Pads Class_A2 (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Output voltage low class VOLA2 − − 0.4 V IOL≤ 2 mA; pin

A2 pads CC out
driver= medium
− − 0.4 V IOL≤ 2 mA; pin
out
driver= strong
− − 0.4 V IOL≤ 500 μA;
pin out
driver= weak
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.

Table 15 Standard_Pads Class_F

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Input Hysteresis F1) HYSF 0.05 x − − V

CC VDDP
Input Leakage Current IOZF CC -6000 − 6000 nA Vi< VDDP / 2 -
Class F 1 V; Vi> VDDP / 2
+ 1 V; Vi≥ 0 V;
Vi≤ VDDP V
-3000 − 3000 nA Vi> VDDP / 2 -
1 V; Vi< VDDP / 2
+1V
Ratio Vil/ Vih, F pads VILF / 0.6 − −
VIHF CC
On-Resistance of the RDSONM − − 170 Ohm IOH> -2 mA;
class F pad, medium CC P_MOS
driver − − 145 Ohm IOL< 2 mA;
N_MOS
Fall time, pad type F, tFF CC − − 60 ns CL= 50 pF
CMOS mode
Rise time, pad type F, tRF CC − − 60 ns CL= 50 pF
CMOS mode

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Table 15 Standard_Pads Class_F (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
Input high voltage, pad VIHF SR 0.6 x − min(V V
class F, CMOS mode VDDP DDP+
0.3,
3.6)
Input low voltage, Class F VILF SR -0.3 − 0.36 x V
pads, CMOS mode VDDP
Output high voltage, class VOHF VDDP- − − V IOH≥ -1.4 mA
F pads, CMOS mode CC 0.4

2.4 − − V IOH≥ -2 mA
Output low voltage, class VOLF CC − − 0.4 V IOL≤ 2 mA
F pads, CMOS mode
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.

Table 16 Standard_Pads Class_I

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Input Hysteresis Class I1) HYSI 0.1 x − − V

CC VDDP
Input Leakage Current IOZI CC -1000 − 1000 nA
Ratio between low and VILI / VIHI 0.6 − −
high input threshold CC
Input high voltage, class I VIHI SR 0.6 x − min(V V
pins VDDP DDP+
0.3,
3.6)
Input low voltage, Class I VILI SR -0.3 − 0.36 x V
pads VDDP
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.

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Table 17 LVDS_Pads Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Output impedance, pad RO CC 40 − 140 Ohm

class F, LVDS mode
Fall time, pad type LVDS tFL CC − − 2 ns termination
100 Ω ± 1 %;
differential
capacitance = 10
pF; input
capacitance = 20
pF
Rise time, pad type LVDS tRL CC − − 2 ns termination
100 Ω ± 1 %;
differential
capacitance = 10
pF; input
capacitance = 20
pF
Pad set-up time tSET_LVD − − 13 μs termination
S CC 100 Ω ± 1 %
Output Differential Voltage VOD CC 150 − 400 mV termination
100 Ω ± 1 %
Output voltage high, pad VOH CC − − 1525 mV termination
class F, LVDS mode 100 Ω ± 1 %
Output voltage low, pad VOL CC 875 − − mV termination
class F, LVDS mode 100 Ω ± 1 %
Output Offset Voltage VOS CC 1075 − 1325 mV termination
100 Ω ± 1 %

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5.2.2 Analog to Digital Converters (ADCx)

ADC parameter are valid for VDDM = 4.75 V to 5.25 V.

Table 18 ADC Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Switched capacitance at CAINSW − 9 20 pF

the analog voltage inputs1) CC
Total capacitance of an CAINTOT − 20 30 pF
analog input CC
Switched capacitance at CAREFSW − 15 30 pF
the positive reference CC
voltage input2)3)
Total capacitance of the CAREFTO − 20 40 pF
voltage reference inputs2) T CC
Differential Non-Linearity EADNL -3 − 3 LSB ADC
Error4)5)6)7) CC resolution= 12-
bit 8) 9)
Gain Error4)6)5)7) EAGAIN -3.5 − 3.5 LSB ADC
CC resolution= 12-
bit 8) 9)
Integral Non- EAINL -3 − 3 LSB ADC
Linearity4)6)5)7) CC resolution= 12-
bit 8) 9)
Offset Error4)6)5)7) EAOFF -4 − 4 LSB ADC
CC resolution= 12-
bit 8) 9)
Converter clock fADC SC 4 − 90 MHz fADC= fFPI
Internal ADC clock fADCI CC 1 − 18 MHz
10)
Charge consumption per QCONV 70 85 100 pC charge needs to
conversion CC be provided via
VAREFx

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Table 18 ADC Parameters (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
Input leakage at analog IOZ1 CC -100 − 500 nA Vi≤ VDDM V;
inputs11) Vi≥ 0.97 x
VDDM V;
overlayed= No
-100 − 600 nA Vi≥ 0.97 x
VDDM V;
Vi≤ VDDM V;
overlayed= Yes
-500 − 100 nA Vi≤ 0.03 x
VDDM V;
Vi≥ 0 V;
overlayed= No
-600 − 100 nA Vi≤ 0.03 x
VDDM V;
Vi≥ 0 V;
overlayed= Yes
-100 − 200 nA Vi> 0.03 x
VDDM V;
Vi< 0.97 x
VDDM V;
overlayed= No
-100 − 300 nA Vi< 0.97 x
VDDM V;
Vi> 0.03 x
VDDM V;
overlayed= Yes
Input leakage current at IOZ2 CC -1 − 1 μA VAREF0≤ VDDM V
Varef0
Input leakage current at -1 − 1 μA VAREF1≤ VDDM V
Varef1
Input leakage current at IOZ3 CC -2 − 2 μA VAGND0≤ VDDM V
Vagnd0
ON resistance of the RAIN CC − 900 1500 Ohm
transmission gates in the
analog voltage path

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Table 18 ADC Parameters (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
ON resistance for the ADC RAIN7T 180 550 900 Ohm
test (pull down for AIN7) CC
Resistance of the RAREF − 500 1000 Ohm
reference voltage input CC
path
Sample time tS CC 2 − 257 TADCI
Calibration time after bit tCAL CC − − 4352 cycle
ADC_GLOBCFG.SUCAL s
is set
Total Unadjusted TUE CC -4 − 413) LSB ADC
Error6)5)12) resolution= 12-
bit
Analog reference ground2) VAGND0 VSSM - − VAREFx V
SR 0.05 -1
Analog input voltage VAIN SR VAGND0 − VAREFx V
Analog reference voltage2) VAREFx VAGND0 − VDDM + V
SR +1 0.0514)
15)

Analog reference voltage VAREFx - VDDM/2 − VDDM + V

range6)5)2) VAGND0 0.05
SR
1) The sampling capacity of the conversion C-network is pre-charged to VAREFx/2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx can deviate from VAREFx/2.
2) Applies to AINx, when used as auxiliary reference input.
3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead smaller capacitances are successively switched to the reference voltage.
4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
5) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additional decrease in
the ADC speed and accuracy.
6) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used,
then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),
TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.
7) If the analog reference voltage is > VDDM, then the ADC converter errors increase.
8) For 10-bit conversions the error value must be multiplied with a factor 0.25.
9) For 8-bit conversions the error value must be multiplied with a factor 0.0625.
10) For a conversion time of 1 µs a rms value of 85µA result for IAREFx.

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11) The leakage current definition is a continuos function, as shown in figure ADCx Analoge Input Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation -
they do not define step function.
12) Measured without noise.
13) For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB
14) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).
15) If the reference voltage VAREFx increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V),
then the accuracy of the ADC decrease by 4LSB12.

Table 19 Conversion Time (Operating Conditions apply)

Parameter Symbol Values Unit Note
Conversion tC CC 2 × TADC + (4 + STC + n) × TADCI μs n = 8, 10, 12 for
time with n - bit conversion
post-calibration TADC = 1 / fFPI
Conversion 2 × TADC + (2 + STC + n) × TADCI TADCI = 1 / fADCI
time without
post-calibration

The power-up calibration of the ADC requires a maximum number of 4352 fADCI cycles.

Analog Input Circuitry

REXT RAIN, On
ANx

VAIN = CEXT CAINSW

CAINTOT - CAINSW
VAGNDx RAIN7T

Reference Voltage Input Circuitry

VAREFx RAREF, On

VAREF CAREFTOT - CAREFSW CAREFSW

VAGNDx

Analog_InpRefDiag

Figure 3 ADCx Input Circuits

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Ioz1
Single ADC Input
500nA

200nA VIN[VDDM%]
100nA
-100nA
3% 97% 100%

-500nA

Ioz1
Overlayed ADC/FADC Input
600nA

300nA VIN[VDDM%]
100nA
-100nA
3% 97% 100%

-600nA

Figure 4 ADCx Analog Inputs Leakage

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5.2.3 Fast Analog to Digital Converter (FADC)

Table 20 FADC Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Input current at VFAREF IFAREF − − 120 μA

CC
Input leakage current at IFOZ2 -500 − 500 nA VFAREF≤ VDDMF
VFAREF1) CC V; VFAREF≥ 0 V
Input leakage current at IFOZ3 -500 − 500 nA
VFAGND CC
DNL error EFDNL -1 − 1 LSB VIN mode=
CC differential;
Gain = 1 or 2
-2 − 2 LSB VIN mode=
differential;
Gain = 4 or 82)
-1 − 1 LSB VIN mode=
single ended;
Gain = 1 or 2
-2 − 2 LSB VIN mode=
single ended;
Gain = 4 or 82)
GRADient error EFGRAD -5 − 5 % VIN mode=
CC differential ;
Gain≤ 4
-5 − 5 % VIN mode=
single ended ;
Gain≤ 4
-6 − 6 % VIN mode=
differential ;
Gain= 8
-6 − 6 % VIN mode=
single ended ;
Gain= 8

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Table 20 FADC Parameters (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

INL error EFINL -4 − 4 LSB VIN mode=

CC differential
-4 − 4 LSB VIN mode=
single ended
Offset error EFOFF -90 − 90 mV VIN mode=
CC differential ;
Calibration= No
-90 − 90 mV VIN mode=
single ended ;
Calibration= No
-20 − 20 mV VIN mode=
differential ;
Calibration= Ye
s 3)4)
-20 − 20 mV VIN mode=
single ended ;
Calibration= Ye
s 3)4)
Error of commen mode EFREF -60 − 60 mV
voltage VFAREF/2 CC
Channel amplifier cutoff fCOFF 2 − − MHz
frequency CC
Converter clock fFADC 1 − 90 MHz fFADC= fFPI
SC
Conversion time tC CC − − 21 1/ For 10-bit
fFADC conversion
Input resistance of the RFAIN 100 − 200 kOh
analog voltage path (Rn, CC m
Rp)
Settling time of a channel tSET CC − − 5 μs
amplifier after changing
ENN or ENP
Analog input voltage VAINF VFAGND − VDDMF V
range SR

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Table 20 FADC Parameters (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Analog reference ground VFAGND VSSAF - − VSSAF V

SR 0.05 + 0.05
Analog reference voltage VFAREF 3.0 − 3.635) V
6)
SR
1) This value applies in power-down mode.
2) No missing codes.
3) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed
minimium once per week.
4) The offser error voltage drifts over the whole temperature range maximum +-3LSB.
5) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 μs and the cumulated sum
of the pulses does not exceed 1 h.
6) A running conversion may become inexact in case of violating the nomal operating conditions (voltage
overshoots).

The calibration procedure should run after each power-up, when all power supply
voltages and the reference voltage have stabilized.

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FADC Analog Input Stage

RN
FAINxN -

+
VFAGND VFAREF /2

=
+
RP
FAINxP -

FADC Reference Voltage

Input Circuitry
VFAREF

IFAREF
VFAREF

VFAGND

FADC_InpRefDiag

Figure 5 FADC Input Circuits

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5.2.4 Oscillator Pins

Table 21 OSC_XTAL Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Input current at XTAL1 IIX1 CC -25 − 25 μA VIN<VDDOSC3 ;

VIN>0 V
Input frequency fOSC SR 4 − 40 MHz Direct Input
Mode selected
8 − 25 MHz External Crystal
Mode selected
Oscillator start-up time1) tOSCS − − 10 ms
CC
Input high voltage at VIHX SR 0.7 x − VDDOS V
XTAL12) VDDOS C3 +
C3 0.5
Input low voltage at VILX SR -0.5 − 0.3 x V
XTAL1 VDDOS
C3
Input Hysteresis for HYSAX − − 200 mV
XTAL1 pad 3) CC
1) tOSCS is defined from the moment when VDDOSC3 = 3.13V until the oscillations reach an amplitude at XTAL1 of
0.3 * VDDOSC3. The external oscillator circuitry must be optimized by the customer and checked for negative
resistance as recommended and specified by crystral suppliers.
2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.4 * VDDOSC3 is
necessary.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can´t be
guaranteed that it suppresses switching due to external system noise.

Note: It is strongly recommended to measure the oscillation allowance (negative

resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.

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5.2.5 Temperature Sensor

Table 22 DTS Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Measurement time tM CC − − 100 μs

Temperature sensor TSR SR -40 − 150 °C
range
Sensor Accuracy TTSA CC -6 − 6 °C
(calibrated)
Start-up time after resets tTSST SR − − 20 μs
inactive

The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
(1)

DTSSTAT RESULT – 596

Tj = -------------------------------------------------------------------
2, 03

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5.2.6 Power Supply Current

The total power supply current defined below consists of leakage and switching
component.
Application relevant values are typically lower than those given in the following
two tables and depend on the customer's system operating conditions (e.g.
thermal connection or used application configurations).
The operating conditions for the parameters in the following table are:
VDD=1.365 V, VDDP=3.47 V, VDDM=5.1 V, fLMB=180, TJ=150 oC
The realisic power pattern defines the following conditions:
• TJ=150 oC
• fLMB = fPCP = fCPU = 180 MHz
• fFPI = 90 MHz
• VDD = VDDOSC = VDDAF = 1.326 V
• VDDP = VDDOSC3 = VDDFL3 = VDDMF = 3.366 V
• VDDM = 5.1 V
The max power pattern defines the following conditions:
• TJ=150 oC
• fLMB = fPCP = fCPU = 180 MHz
• fFPI = 90 MHz
• VDD = VDDOSC = VDDAF = 1.365 V
• VDDP = VDDOSC3 = VDDFL3 = VDDMF = 3.47 V
• VDDM = 5.5 V

Table 23 Power Supply Parameters

Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Core active IDD CC − − 5853) mA power pattern= max
mode supply − − 433 4)
mA power pattern= realistic
current1)2)
IDD current at IDD_PORS − − 300 mA
PORST Low T CC − − 291 mA VDD=1.326 V
Analog core IDDAF − − 23 mA
supply current CC
Oscillator core IDDOSC − − 2 mA
supply current CC
E-Ray PLL core IDDPF − − 2 mA
supply current CC

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Table 23 Power Supply Parameters (cont’d)

Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
IDDP current at IDDP_POR − − 2.5 mA
PORST Low ST CC
IDDP current no IDDP CC − − IDDP_P mA including flash read current
pad activity, ORST +
LVDS off 5) 12
− − IDDP_P mA including flash programming
ORST + current 6)
27
− − IDDP_P mA including flash erase current
6)
ORST +
20 7)
Flash memory IDDFL3 − − 56 mA flash read current
current 5) CC − − 21 mA flash programming current 6)
− − 56 mA flash erase current 6)
Oscillator IDDOSC3 − − 11.5 mA
power supply CC
current, 3.3V
E-Ray PLL IDDPF3 − − 3.5 mA
supply current, CC
3.3V
FADC analog IDDMF − − 15 mA
supply current, CC
3.3V
Current ILVDS − − 24 mA for all LVDS pads in total
Consumption of CC
LVDS Pad
Pairs
ADC 5V power IDDM CC − − 2 mA
supply current
Maximum PD CC − − 1277 mW power pattern= max
power − − 1042 mW power pattern= realistic
dissipation
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer
application will most probably be lower than this value, but must be evaluated seperately.
2) This current includes the E-Ray module power consumption, including the PCP operation component.

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3) The IDD decreases typically by 79mA if the fCPU decreases by 50MHz, at constant TJ
4) The IDD decreases typically by 38mA if the fCPU decreases by 50MHz, at constant TJ
5) For operations including the D-Flash the required currents are always lower than the currents for non D-Flash
operation.
6) Relevant for the power supply dimensioning, not for thermal considerations.
7) In case of erase of Program Flash PF, internal flash array loading effects may generate transient current spikes
of up to 15 mA for maximum 5 ms per flash module.

5.2.6.1 Calculating the 1.3 V Current Consumption

The current consumption of the 1.3 V rail compose out of two parts:
• Static current consumption
• Dynamic current consumption
The static current consumption is related to the device temperature TJ and the dynamic
current consumption depends of the configured clocking frequencies and the software
application executed. These two parts needs to be added in order to get the rail current
consumption.
(2)

= 2, 20897 --------- × e 0, 02696 × T J [ C ]

mA
I
0 C

(3)

I 0 = 10, 68 --------- × e 0, 02203 × T J [ C ]

mA
C

Function 2 defines the typical static current consumption and Function 3 defines the
maximum static current consumption. Both functions are valid for VDD = 1.326 V.
For the dynamic current consumption using the application pattern and fLMB = 2 * fFPI the
function 4 applies:
(4)
mA
I D y m = 0, 77 ------------- × f CPU [ MHz ]
MHz

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and this finally results in

(5)

I DD = I 0 + I DYM

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5.3 AC Parameters
That means, keeping the pads constantly at maximum strength.

5.3.1 Testing Waveforms

VD D P
90% 90%

10% 10%
VSS
tR tF
rise_fall

Figure 6 Rise/Fall Time Parameters

VD D P

VD D E / 2 Test Points VD D E / 2
VSS
mct04881_a.vsd

Figure 7 Testing Waveform, Output Delay

VLoad+ 0.1 V Timing VOH - 0.1 V

Reference
VLoad- 0.1 V Points VOL - 0.1 V

MCT04880_new

Figure 8 Testing Waveform, Output High Impedance

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5.3.2 Power Sequencing

V
5.25V
5V
4.75V
3.47V VAREF
3.3V
3.0V
-12%
1.365V
1.3V
1.235V -12%
0.5V 0.5V 0.5V

t
VDDP

PORST

power power t
down fail
Power-Up 10.vsd

Figure 9 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence

The following list of rules applies to the power-up/down sequence:
• All ground pins VSS must be externally connected to one single star point in the
system. Regarding the DC current component, all ground pins are internally directly
connected.
• At any moment in time to avoid increased latch-up risk,
each power supply must be higher then any lower_power_supply - 0.5 V, or:
VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.3 - 0.5 V;VDD3.3 > VDD1.3 - 0.5 V, see Figure 9.
– The latch-up risk is minimized if the I/O currents are limited to:
– 20 mA for one pin group
– AND 100 mA for the completed device I/Os
– AND additionally before power-up / after power-down:
1 mA for one pin in inactive mode (0 V on all power supplies)
• During power-up and power-down, the voltage difference between the power supply
pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names (for example
VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than 100 mV.
On the other hand, all power supply pins with the same name (for example all VDDP),

Data Sheet 83 V 1.0, 2012-03

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are internally directly connected. It is recommended that the power pins of the same
voltage are driven by a single power supply.
1. The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.3, and VAREF power-
supplies and the oscillator have reached stable operation, within the normal
operating conditions.
2. At normal power down the PORST signal should be activated within the normal
operating range, and then the power supplies may be switched off. Care must be
taken that all Flash write or delete sequences have been completed.
3. At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V
power supply voltage falls 12% below the nominal level. If, under these conditions,
the PORST is activated during a Flash write, only the memory row that was the target
of the write at the moment of the power loss will contain unreliable content. In order
to ensure clean power-down behavior, the PORST signal should be activated as
close as possible to the normal operating voltage range.
4. In case of a power-loss at any power-supply, all power supplies must be powered-
down, conforming at the same time to the rules number 2 and 4.
5. Although not necessary, it is additionally recommended that all power supplies are
powered-up/down together in a controlled way, as tight to each other as possible.
6. Additionally, regarding the ADC reference voltage VAREF:
– VAREF must power-up at the same time or later then VDDM, and
– VAREF must power-down either earlier or at latest to satisfy the condition
VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF filter
capacitance through the ESD diodes through the VDDM power supply. In case of
discharging the reference capacitance through the ESD diodes, the current must
be lower than 5 mA.

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5.3.3 Power, Pad and Reset Timing

Table 24 Reset Timings Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Application Reset Boot tB CC 150 − 665 μs fCPU = 180 MHz

Time1)2)
Power on Reset Boot tBP CC − − 2.5 ms
Time3)4)
HWCFG pins hold time tHDH SR 16 / − − ns
from ESR0 rising edge fFPI
HWCFG pins setup time to tHDS CC 0 − − ns
ESR0 rising edge
Ports inactive after ESR0 tPI CC − − 8 / fFPI ns
reset active
Ports inactive after tPIP CC − − 150 ns
PORST reset active5)
Minimum PORST active tPOA CC 10 − − ms
time after power supplies
are stable at operating
levels
TESTMODE / TRST hold tPOH SR 100 − − ns
time from PORST rising
edge
PORST rise time tPOR SR − − 50 ms
TESTMODE / TRST tPOS SR 0 − − ns
setup time to PORST
rising edge
Application Reset inactive tPOR_APP − − 40 6) μs
after PORST deassertion SR
1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
2) The given time includes the time of the internal reset extension for a configured value of
SCU_RSTCNTCON.RELSA = 0x05BE.
3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the
first user instruction has entered the CPU pipeline and its processing starts.

Data Sheet 85 V 1.0, 2012-03

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4) The given time includes the internal reset extension time for the System and Application Reset which is visible
through ESR0.
5) This parameter includes the delay of the analog spike filter in the PORST pad.
6) Application Reset is assumed not to be extended from external, otherwise the time extends by the time the
Application Reset is extended.

VDD P -12%
VD D PPA
V D DPPA
VDDP

VDD
tPOA VD D -12%
tPOA
PORST
tPOH tPOH
TRST
TESTMODE
t hd t hd
ESR0
tHDH tHDH tHDH
HWCFG
t PIP t PIP
tPI tPI
Pads
tPI tPI tPI
t PIP
Pad-state undefined

Tri-state or pull device active

reset_beh2
As programmed

Figure 10 Power, Pad and Reset Timing

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5.3.4 Phase Locked Loop (PLL)

Table 25 PLL_SysClk Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Accumulated Jitter DP CC -7 − 7 ns
PLL base frequency fPLLBASE 50 200 320 MHz
CC
VCO input frequency fREF CC 8 − 16 MHz
VCO frequency range fVCO CC 400 − 720 MHz
PLL lock-in time tL CC 14 − 200 μs N > 32
14 − 400 μs N ≤ 32

Phase Locked Loop Operation

When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMB-
Bus clock fLMB) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using wait states and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in
[ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the
number m of consecutive fLMB clock periods.

for ( K2 ≤ 100 ) and ( m ≤ ( f LMB [ MHz ] ) ⁄ 2 )

( 1 – 0, 01 × K2 ) × ( m – 1 )
D m [ ns ] = ⎛⎝ --------------------------------------------- + 5⎞⎠ × ⎛⎝ ---------------------------------------------------------------- + 0, 01 × K2⎞⎠
740 (6)
K2 × f LMB [ MHz ] 0, 5 × f LMB [ MHz ] – 1

740 (7)
else D m [ ns ] = --------------------------------------------- + 5
K2 × f LMB [ MHz ]

With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum

Data Sheet 87 V 1.0, 2012-03

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accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock

frequency fLMB results in a higher absolute maximum jitter value.
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
The maximum peak-to peak noise on the pad supply voltage, measured between
VDDOSC and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.

Oscillator Watchdog (OSC_WDT)

The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The
OSC_WDT checks for too low frequencies and for too high frequencies.
The frequency that is monitored is fOSCREF which is derived for fOSC.
(8)
fO S C
f O S C R EF = ----------------------------------
-
OSCVAL + 1

The divider value SCU_OSCCON.OSCVAL has to be selected in a way that fOSCREF is

2.5 MHz.
Note: fOSCREF has to be within the range of 2 MHz to 3 MHz and should be as close as
possible to 2.5 MHz.
The monitored frequency is too low if it is below 1.25 MHz and too high if it is above
7.5 MHz. This leads to the following two conditions:
• Too low: fOSC < 1.25 MHz × (SCU_OSCCON.OSCVAL+1)
• Too high: fOSC > 7.5 MHz × (SCU_OSCCON.OSCVAL+1)
Note: The accuracy is 30% for these boundaries.

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5.3.5 ERAY Phase Locked Loop (ERAY_PLL)

Table 26 PLL_ERAY Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Accumulated jitter at DPP CC -0.8 − 0.8 ns

SYSCLK pin
Accumulated_Jitter DP CC -0.5 − 0.5 ns
PLL Base Frequency of fPLLBASE_ 50 250 360 MHz
the ERAY PLL ERAY CC
VCO input frequency of fREF CC 20 − 40 MHz
the ERAY PLL
VCO frequency range of fVCO_ERA 450 − 500 MHz
the ERAY PLL Y CC
PLL lock-in time tL CC 5.6 − 200 μs

Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDPF3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.

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5.3.6 JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.

Table 27 JTAG Interface Timing Parameters

(Operating Conditions apply)
Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

TCK clock period t1 SR 25 – – ns –

TCK high time t2 SR 10 – – ns –
TCK low time t3 SR 10 – – ns –
TCK clock rise time t4 SR – – 4 ns –
TCK clock fall time t5 SR – – 4 ns –
TDI/TMS setup t6 SR 6 – – ns –
to TCK rising edge
TDI/TMS hold t7 SR 6 – – ns –
after TCK rising edge
TDO valid after TCK falling t8 CC – – 13 ns CL = 50 pF
edge1) (propagation delay) t CC 3 – – ns CL = 20 pF
8
TDO hold after TCK falling t18 CC 2 – – ns
edge1)
TDO high imped. to valid t9 CC – – 14 ns CL = 50 pF
from TCK falling edge1)2)
TDO valid to high imped. t10 CC – – 13.5 ns CL = 50 pF
from TCK falling edge1)
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.

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t1
0.9 VD D P
0.5 VD D P
0.1 VD D P
t5 t4
t2 t3

MC_ JTAG_ TCK

Figure 11 Test Clock Timing (TCK)

TCK

t6 t7

TMS

t6 t7

TDI

t9 t8 t1 0

TDO

t18
MC_JTAG

Figure 12 JTAG Timing

Data Sheet 91 V 1.0, 2012-03

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Electrical ParametersAC Parameters

5.3.7 DAP Interface Timing

The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.

Table 28 DAP Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

DAP0 clock period1) tTCK SR 12.5 − − ns

DAP0 high time t12 SR 4 − − ns
DAP0 low time 1)
t13 SR 4 − − ns
DAP0 clock rise time t14 SR − − 2 ns
DAP0 clock fall time t15 SR − − 2 ns
DAP1 setup to DAP0 t16 SR 6.0 − − ns
rising edge
DAP1 hold after DAP0 t17 SR 6.0 − − ns
rising edge
DAP1 valid per DAP0 t19 CC 8 − − ns CL= 20 pF;
clock period2) f= 80 MHz
10 − − ns CL= 50 pF;
f= 40 MHz
1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.

t11
0.9 VD D P
0.5 VD D P
0.1 VD D P
t1 5 t14
t1 2 t1 3

MC_DAP0

Figure 13 Test Clock Timing (DAP0)

Data Sheet 92 V 1.0, 2012-03

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Electrical ParametersAC Parameters

DAP0

t1 6 t1 7

DAP1

MC_ DAP1_RX

Figure 14 DAP Timing Host to Device

t1 1

DAP1

t1 9
MC_ DAP1_TX

Figure 15 DAP Timing Device to Host

Data Sheet 93 V 1.0, 2012-03

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Electrical ParametersAC Parameters

5.3.8 Peripheral Timings

Note: Peripheral timing parameters are not subject to production test. They are verified
by design/characterization.

5.3.8.1 Micro Link Interface (MLI) Timing

MLI Transmitter Timing

t13 t14
t10
t12
TCLKx
t11
t15 t15
TDATAx
TVALIDx
t16
t17
TREADYx

MLI Receiver Timing

t23 t24
t20
t22
RCLKx
t21
t25
t26
RDATAx
RVALIDx

t27 t27
RREADYx

MLI_Tmg_2.vsd

Figure 16 MLI Interface Timing

Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.

Data Sheet 94 V 1.0, 2012-03

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Electrical ParametersAC Parameters

The MLI parameters are vaild for CL = 50 pF and strong driver medium edge.

Table 29 MLI Receiver

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

RCLK clock period t20 SR 1 / fFPI − − ns

RCLK high time1)2) t21 SR − 0.5 x − ns
t20
RCLK low time1)2) t22 SR − 0.5 x − ns
t20
RCLK rise time3) t23 SR − − 4 ns
RCLK fall time 3)
t24 SR − − 4 ns
RDATA/RVALID setup t25 SR 4.2 − − ns
time before RCLK falling
edge
RDATA/RVALID hold time t26 CC 2.2 − − ns
after RCLK falling edge
RREADY output delay t27 CC 0 − 16 ns
time
1) The following formula is valid: t21 + t22 = t20.
2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver
timing parameters.
3) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower
input signal rise/fall times can be used for longer RCLK clock periods.

Table 30 MLI Transmitter

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

TCLK clock period t10 CC 2x1/ − − ns

fFPI
TCLK high time1)2) t11 CC 0.45 x 0.5 x 0.55 x ns
t10 t10 t10
TCLK low time1)2) t12 CC 0.45 x 0.5 x 0.55 x ns
t10 t10 t10
TCLK rise time t13 CC − − 0.3 x ns
t103)

Data Sheet 95 V 1.0, 2012-03

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Electrical ParametersAC Parameters

Table 30 MLI Transmitter (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
TCLK fall time t14 CC − − 0.3 x ns
t103)
TDATA/TVALID output t15 CC -3 − 4.4 ns
delay time
TREADY setup time t16 SR 18 − − ns
before TCLK rising edge
TREADY hold time after t17 SR -2 − − ns
TCLK rising edge
1) The following formula is valid: t11 + t12 = t10.
2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be
regarded additionally to t11 / t12.
3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended
for TCLK.

5.3.8.2 Micro Second Channel (MSC) Interface Timing

The MSC parameters are vaild for CL = 50 pF.

Table 31 MSC Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

FCLP clock period1)2) t40 CC 2x − − ns

TMSC3)
SOP4)/ENx outputs delay t45 CC -2 − 5 ns ENx with strong
from FCLP4) rising edge driver and
sharp (minus )
edge
-2 − 10 ns ENx with strong
driver and
medium
(minus) edge
0 − 21 ns ENx with strong
driver and soft
edge

Data Sheet 96 V 1.0, 2012-03

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Electrical ParametersAC Parameters

Table 31 MSC Parameters (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
SDI bit time t46 CC 8x − − ns
TMSC
SDI rise time t48 SR − − 100 ns
SDI fall time t49 SR − − 100 ns
1) FCLP signal rise/fall times are only defined by the pad rise/fall times.
2) FCLP signal high and low can be minimum 1xTMSC
3) TMSC = TSYS = 1 / fSYS.
4) SOP / FCLP either propagated by LVDS or by CMOS strong driver and non soft edge.

t40
0.9 VDDP
FCLP
0.1 VDDP
t45 t45
SOP
EN

t48 t49

0.9 VDDP
SDI
0.1 VDDP

t46 t46
MSC_Tmg_1.vsd

Figure 17 MSC Interface Timing

Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.

Data Sheet 97 V 1.0, 2012-03

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Electrical ParametersAC Parameters

5.3.8.3 SSC Master/Slave Mode Timing

The SSC parameters are vaild for CL = 50 pF and strong driver medium edge.

Table 32 SSC Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

SCLK clock period1)2)3) t50 CC 2x1/ − − ns

fFPI
MTSR/SLSOx delay form t51 CC 0 − 8 ns
SCLK rising edge
MRST setup to SCLK t52 SR 16.5 − − ns
latching edge3)
MRST hold from SCLK t53 SR 0 − − ns
latching edge3)
SCLK input clock t54 SR 4x1/ − − ns
period1)3) fFPI
SCLK input clock duty t55_t54 45 − 55 %
cycle SR
MTSR setup to SCLK t56 SR 1 / fFPI − − ns
latching edge3)4)
MTSR hold from SCLK t57 SR 1 / fFPI − − ns
latching edge +5
SLSI setup to first SCLK t58 SR 1 / fFPI − − ns
latching edge +5
SLSI hold from last SCLK t59 SR 7 − − ns
latching edge 5)
MRST delay from SCLK t60 CC 0 − 16.5 ns
shift edge
SLSI to valid data on t61 CC − − 16.5 ns
MRST
1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.
2) SCLK signal high and low times can be minimum 1xTSSC.
3) TSSCmin = TSYS = 1/fSYS.
4) Fractional divider switched off, SSC internal baud rate generation used.
5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever
is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair
of shifting / latching edges.

Data Sheet 98 V 1.0, 2012-03

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Electrical ParametersAC Parameters

t50

SCLK1)2)
t51 t51
MTSR1)

t52
t53
1) Data
MRST
valid
t51
2)
SLSOn

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0

and the first SCLK high pulse is in the first one of a transmission.
SSC_TmgMM

Figure 18 SSC Master Mode Timing

t54
First shift First latching Last latching
SCLK1) SCLK edge SCLK edge SCLK edge

t55 t55
t56 t56
t57 t57
MTSR 1) Data Data
valid valid

t60 t60
1)
MRST

t61 t59
SLSI
t58

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

SSC_TmgSM

Figure 19 SSC Slave Mode Timing

Data Sheet 99 V 1.0, 2012-03

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Electrical ParametersAC Parameters

5.3.8.4 ERAY Interface Timing

The timings of this section are valid for the strong driver and either sharp edge or medium
edge settings of the output drivers with CL = 25 pF.
The ERAY interface is only available for the SAK-TC1782F-320F180HR / SAK-
TC1782F-320F180HL.

Table 33 ERAY Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Time span from last BSS t60 CC 997.75 − 1002.2 ns

to FES without the 5
influence of quartz
tolerancies (d10Bit_TX)1)
TxD data valid from t61-t62 − − 1.5 ns Asymmetrical
fsample flip flop txd_reg CC delay of rising
TxDA, TxDB and falling edge
(dTxAsym)2)3) (TxDA, TxDB)
Time span between last t63 SR 966 − 1046.1 ns
BSS and FES without
influence of quartz
tolerancies
(d10Bit_RX)1)4)5)
RxD capture by fsample t64-t65 − − 3.0 ns Asymmetrical
(RxDA/RxDB sampling CC delay of rising
flip-flop) (dRxAsym)5) and falling edge
(RxDA, RxDB)
TxD data delay from dTxdly − − 10.0 ns Px_PDR.PDy =
sampling flip-flop CC 000B
− − 15.0 ns Px_PDR.PDy =
001B
RxD capture delay by dRxdly − − 10.0 ns
sampling flip-flop CC
1) This includes the PLL_ERAY accumulated jitter.
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
Quarz tolerance and PLL_ERAY accumulated jitter are not included.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |tFA2 - tRA2| ≤ 1 ns.
4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * VDDP FlexRay standard input thresholds. For input
thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.

Data Sheet 100 V 1.0, 2012-03

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Electrical ParametersAC Parameters

5) Valid for output slopes of the bus driver of dRxSlope ≤ 5ns, 20% * VDDP to 80% * VDDP, according to the
FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming
signal have to satisfy the following inequality: -1.6ns ≤ tFA2 - tRA2 ≤ 1.3ns.

BSS Last CRC Byte FES

(Byte Start Sequence) (Frame End Sequence)

0.7 VDD
TXD 0.3 VDD

t60

tsample

TXD 0.9 VDD

0.1 VDD
t61 t62

BSS Last CRC Byte FES

(Byte Start Sequence) (Frame End Sequence)

0.7 VDD
RXD 0.3 VDD

t63

tsample

RXD 0.7 VDD

0.3 VDD
t64 t65
ERAY_TIMING

Figure 20 ERAY Timing

Data Sheet 101 V 1.0, 2012-03

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Electrical ParametersAC Parameters

5.3.8.5 EBU Timings

EBU Asynchronous Timings

VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class A2 pins;
CL = 35 pF for address/data; CL = 40pF for the control lines.
For each timing, the accumulated PLL jitter of the programed duration in number of clock
periods must be added separately. Operating conditions apply and CL = 35 pF.

Table 34 EBU Common Asynchronous Timings

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Pulse wdih deviation from ta CC -0.8 − 0.8 ns edge= medium

the ideal programmed -0.8 − 0.8 ns edge= sharp
width due to B pad
asymmetry, rise delay - fall
delay
AD(31:0) output delay to t13 CC -5.5 − 2 ns
ADV# rising edge,
multiplexed read / write
AD(31:0) output delay to t14 CC -5.5 − 2 ns
ADV# rising edge,
multiplexed read / write

Table 35 EBU Asynchronous Read Timings

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

A(23:0) output delay to RD t0 CC -2.5 − 2.5 ns

rising edge, deviation from
the ideal programmed
value
A(23:0) output delay to RD t1 CC -2.5 − 2.5 ns
rising edge, deviation from
the ideal programmed
value

Data Sheet 102 V 1.0, 2012-03

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Electrical ParametersAC Parameters

Table 35 EBU Asynchronous Read Timings (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
CS rising edge to RD t2 CC -2 − 2.5 ns
rising edge, deviation from
the ideal programmed
value
ADV rising edge to RD t3 CC -1.5 − 4.5 ns
rising edge, deviation from
the ideal programmed
value
BC rising edge to RD t4 CC -2.5 − 2.5 ns
rising edge, deviation from
the ideal programmed
value
WAIT input setup to RD t5 SR 12 − − ns
rising edge, deviation from
the ideal programmed
value
WAIT input hold to RD t6 SR 0 − − ns
rising edge, deviation from
the ideal programmed
value
Data input setup to RD t7 SR 12 − − ns
rising edge, deviation from
the ideal programmed
value
Data input hold to RD t8 SR 0 − − ns
rising edge, deviation from
the ideal programmed
value
MR / W output delay to t9 CC -2.5 − 1.5 ns
RD# rising edge, deviation
from the ideal
programmed value

Data Sheet 103 V 1.0, 2012-03

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Electrical ParametersAC Parameters

EBU Address Address Hold Command Command Recovery New Addr.

STATE Phase Phase (opt.) Delay Phase Phase Phase (opt.) Phase

Control Bitfield: ADDRC AHOLDC CMDDELAY RDWAIT RDRECOVC ADDRC

Duration Limits in 1...15 0...15 0...7 1...31 0...15 1...15

EBU_CLK Cycles

A[23:0] Valid Address Next

Addr.
pv + t0 pv + t1
pv + ta t2
CS[3:0]
CSCOMB

pv + ta pv + t3
ADV

pv + ta
RD

pv + ta
pv + ta t4
BC[3:0]

pv + t5 t6
WAIT

pv + t13 pv + t14 t7
t8

AD[31:0] Address Out Data In

MR/W
pv + t9
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values) new_MuxRD_Async_10.vsd

Figure 21 Multiplexed Read Access

Data Sheet 104 V 1.0, 2012-03

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Electrical ParametersAC Parameters

EBU Address Address Hold Command Recovery New Addr.

STATE Phase Phase (opt.) Phase Phase (opt.) Phase

Control Bitfield: ADDRC AHOLDC RDWAIT RDRECOVC ADDRC

Duration Limits in 1...15 0...15 1...31 0...15 1...15

EBU_CLK Cycles

A[23:0] Valid Address Next

Addr.
pv + t0 pv + t1
pv + ta t2
CS[3:0]
CSCOMB

pv + ta pv + t3

ADV

pv + ta
RD

pv + ta
pv + ta t4
BC[3:0]

pv + t5 t6
WAIT

t7
t8

AD[31:0] Data In

MR/W
pv + t9

pv = programmed value,
TEBU_CLK * sum (correponding bitfield values) new_DemuxRD_Async_10.vsd

Figure 22 Demultiplexed Read Access

Data Sheet 105 V 1.0, 2012-03

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Electrical ParametersAC Parameters

Table 36 EBU Asynchnronous Write Timings

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

A(23:0) output delay to t30 CC -2.5 − 2.5 ns

WR rising edge, deviation
from the ideal
programmed value
A(23:0) output delay to t31 CC -2.5 − 2.5 ns
WR rising edge, deviation
from the ideal
programmed value
CS rising edge to WR t32 CC -2 − 2 ns
rising edge, deviation from
the ideal programmed
value
ADV rising edge to WR t33 CC -2.5 − 2 ns
rising edge, deviation from
the ideal programmed
value
BC rising edge to WR t34 CC -2.5 − 2 ns
rising edge, deviation from
the ideal programmed
value
WAIT input setup to WR t35 SR 12 − − ns
rising edge, deviation from
the ideal programmed
value
WAIT input hold to WR t36 SR 0 − − ns
rising edge, deviation from
the ideal programmed
value
Data output delay to WR t37 CC -5.5 − 2 ns
rising edge, deviation from
the ideal programmed
value

Data Sheet 106 V 1.0, 2012-03

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Electrical ParametersAC Parameters

Table 36 EBU Asynchnronous Write Timings (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Data output delay to WR t38 CC -5.5 − 2 ns

rising edge, deviation from
the ideal programmed
value
MR / W output delay to t39 CC -2.5 − 1.5 ns
WR rising edge, deviation
from the ideal
programmed value

Data Sheet 107 V 1.0, 2012-03

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Electrical ParametersAC Parameters

EBU Address Address Hold Command Data Recovery New Addr.

STATE Phase Phase (opt.) Phase Hold Phase Phase (opt.) Phase

Control Bitfield: ADDRC AHOLDC RDWAIT DATAC RDRECOVC ADDRC

Duration Limits in 1...15 0...15 1...31 0...15 0...15 1...15

EBU_CLK Cycles

A[23:0] Valid Address Next

Addr.
pv + t30
pv + t31
pv + ta
CS[3:0] pv + t32
CSCOMB

pv + ta pv + t33

ADV

pv + ta
RD/WR

pv + ta
pv + ta
BC[3:0] t34

t35
WAIT
t36
pv + t37
t14
pv + t13 pv + t38

AD[31:0] Address Out Data Out

MR/W pv + t39

pv = programmed value,
TEBU_CLK * sum (correponding bitfield values) new_MuxWR_Async_10.vsd

Figure 23 Multiplexed Write Access

Data Sheet 108 V 1.0, 2012-03

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Electrical ParametersAC Parameters

EBU Address Address Hold Command Data Recovery New Addr.

STATE Phase Phase (opt.) Phase Hold Phase Phase (opt.) Phase

Control Bitfield: ADDRC AHOLDC RDWAIT DATAC RDRECOVC ADDRC

Duration Limits in 1...15 0...15 1...31 0...15 0...15 1...15

EBU_CLK Cycles

A[23:0] Valid Address Next

Addr.
pv + t30
pv + t31
pv + ta
CS[3:0] pv + t32
CSCOMB

pv + ta pv + t33

ADV

pv + ta
RD/WR

pv + ta
pv + ta
BC[3:0] t34

t35
WAIT
t36

pv + t37 pv + t38

AD[31:0] Data Out

pv + t39
MR/W

pv = programmed value,
TEBU_CLK * sum (correponding bitfield values) new_DemuxWR_Async_10.vsd

Figure 24 Demultiplexed Write Access

Data Sheet 109 V 1.0, 2012-03

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Electrical ParametersPackage and Reliability

5.4 Package and Reliability

5.4.1 Package Parameters

Table 37 Thermal Characteristics of the Package

Device Package RΘJCT1) RΘJCB1) RΘJLead Unit Note
TC1784 PG-LFBGA-292 6,8 4,8 17,0 K/W
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined
with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate
the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the
case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are
under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA × PD, where the RTJA
is the total thermal resistance between the junction and the ambient. This total junction ambient resistance
RTJA can be obtained from the upper four partial thermal resistances.
Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).

Data Sheet 110 V 1.0, 2012-03

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Electrical ParametersPackage and Reliability

5.4.2 Package Outline

Figure 25 Package Outlines PG-LFBGA-292

You can find all of our packages, sorts of packing and others in our Infineon Internet
Page “Products”: http://www.infineon.com/products.

5.4.3 Flash Memory Parameters

The data retention time of the TC1784’s Flash memory depends on the number of times
the Flash memory has been erased and programmed.

Table 38 FLASH32 Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition

Data Flash Erase Time tERD CC − − 31) s

per Sector
Program Flash Erase tERP CC − − 5 s
Time per 256 KByte
Sector

Data Sheet 111 V 1.0, 2012-03

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Electrical ParametersPackage and Reliability

Table 38 FLASH32 Parameters (cont’d)

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Condition
Program time data flash tPRD CC − − 5.3 ms without
per page2) reprogramming
− − 15.9 ms with two
reprogramming
cycles
Program time program tPRP CC − − 5.3 ms without
flash per page3) reprogramming
− − 10.6 ms with one
reprogramming
cycle
Data Flash Endurance NE CC 60000 − − cycle Min. data
4)
s retention time 5
years
Erase suspend delay tFL_ErSusp − − 15 ms
CC
Wait time after margin tFL_Margin 10 − − μs
change Del CC
Program Flash Retention tRET CC 20 − − year Max. 1000
Time, Physical Sector5)6) s erase/program
cycles
Program Flash Retention tRETL CC 20 − − year Max. 100
Time, Logical Sector5)6) s erase/program
cycles
UCB Retention Time5)6) tRTU CC 20 − − year Max. 4
s erase/program
cycles per UCB
Wake-Up time tWU CC − − 270 μs
DFlash wait state WSDF 50 ns x − −
configuration CC fFSI
PFlash wait state WSPF 26 ns x − −
configuration CC fFSI
1) In case of wordline oriented defects (see robust EEPROM emulation in the User's Manual) this erase time can
increase by up to 100%.
2) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each
reprogramming takes additional 5 ms.

Data Sheet 112 V 1.0, 2012-03

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Electrical ParametersPackage and Reliability

3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes additional 5 ms.
4) Only valid when a robust EEPROM emulation algorithm is used. For more details see the User´s Manual.
5) Storage and inactive time included.
6) At average weighted junction temperature Tj = 100°C, or the retention time at average weighted temperature
of Tj = 110°C is minimum 10 years, or the retention time at average weighted temperature of Tj = 150°C is
minimum 0.7 years.

5.4.4 Quality Declarations

Table 39 Quality Parameters

Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Operation tOP – – 24000 hours –2)
Lifetime1)
ESD susceptibility VHBM – – 2000 V Conforming to
according to JESD22-A114-B
Human Body
Model (HBM)
ESD susceptibility VHBM1 – – 500 V –
of the LVDS pins
ESD susceptibility VCDM – – 500 V Conforming to
according to JESD22-C101-C
Charged Device
Model (CDM)
Moisture MSL – – 3 – Conforming to Jedec
Sensitivity Level J-STD-020C for 240°C
1) This lifetime refers only to the time when the device is powered on.
2) For worst-case temperature profile equivalent to:
1200 hours at Tj = 125...150oC
3600 hours at Tj = 110...125oC
7200 hours at Tj = 100...110oC
11000 hours at Tj = 25...100oC
1000 hours at Tj = -40...25oC

Data Sheet 113 V 1.0, 2012-03

 TC1784

History

6 History
The Version 0.7 is the first version of this document:
The following changes where done between Version 0.7 and 0.71 of this document:
• update and coorect figure 3-2
• update and correct table 3-1
The following changes where done between Version 0.71 and 1.0 of this document:
• adapt Absolute Maximum Rating
• clarify pad supply levels in Pin Reliability in Overload section
• add note at the end of Pin Reliability in Overload section
• clarify wording for valid operating conditions
• split FADC DNL parameter into two conditions and change value for gain 4 and 8
• add footnote 5 to IDDP
• add footnote for D-Flash currents in power section
• rework first sentence for chapter 5.3
• reduce min value for tL for both PLLs
• add for MLI and SSC timing parameter: valid strong driver medium edge only
• change MLI parameter t17 min value
• update parameter description for SSC parameters t52, t53, t56, t57, t58, and t59
• change SSC parameters from CC to SR Symbol for t56, t57, t58 and t59
• add footnote to Flash parameter tERD

Data Sheet 115 V 1.0, 2012-03

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG