STM8AF6388

Automotive 8-bit MCU, with up to 128-Kbyte Flash memory, data

EEPROM, 10-bit ADC, timers, LIN, USART, SPI, I2C, 3 to 5.5 V
Datasheet - production data

Features
• AEC-Q10x qualified
• Core
– Max fCPU: 24 MHz LQFP80 14x14 mm LQFP64 10x10 mm LQFP48 7x7 mm
– Advanced STM8A core with Harvard
architecture and 3-stage pipeline
– Average 1.6 cycles/instruction resulting in
10 MIPS at 16 MHz fCPU for industry
standard benchmark LQFP32 7x7 mm VFQFP32 5x5 mm

• Memories – Highly robust I/O design, immune against

– Program memory: 32 to 128 Kbyte Flash current injection
program; data retention 20 years at 55 °C
• Communication interfaces
– Data memory: up to 2 Kbyte true data
– USART with clock output for synchronous
EEPROM; endurance 300 kcycle
operation - LIN master mode
– RAM: 6 Kbyte
– LINUART LIN 2.2 compliant, master/slave
• Clock management modes with automatic resynchronization
– Low-power crystal resonator oscillator with – SPI interface up to 10 Mbit/s or fMASTER/2
external clock input – I2C interface up to 400 Kbit/s
– Internal, user-trimmable 16 MHz RC and
• Analog to digital converter (ADC)
low-power 128 kHz RC oscillators
– 10-bit resolution, 2 LSB TUE, 1 LSB
– Clock security system with clock monitor
linearity and up to 16 multiplexed channels
• Reset and supply management
• Operating temperature up to 150 °C
– Wait/auto-wakeup/Halt low-power modes
with user definable clock gating • Qualification conforms to AEC-Q100 grade 0
– Low consumption power-on and power-
down reset
• Interrupt management
– Nested interrupt controller with 32 vectors
– Up to 37 external interrupts on 5 vectors
• Timers
– 2 general purpose 16-bit timers with up to 3
CAPCOM channels each (IC, OC, PWM)
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-
time insertion and flexible synchronization
– 8-bit AR basic timer with 8-bit prescaler
– Auto-wakeup timer
– Window and independent watchdog timers
• I/Os
– Up to 68 user pins (11 high sink I/Os)

October 2017 DocID031156 Rev 1 1/116

This is information on a product in full production. www.st.com
Contents STM8AF6388

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 STM8A central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1 Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.3 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 15
5.2.1 SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2.2 Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4 Flash program and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4.2 Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4.3 Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4.4 Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5.2 16 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . 17
5.5.3 128 kHz low-speed internal RC oscillator (LSI) . . . . . . . . . . . . . . . . . . . 18
5.5.4 24 MHz high-speed external crystal oscillator (HSE) . . . . . . . . . . . . . . 18
5.5.5 External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5.6 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.7.1 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.7.2 Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.7.3 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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5.7.4 Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . 20

5.7.5 Basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.8 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.9 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.9.1 Universal synchronous/asynchronous receiver transmitter (USART) . . 22
5.9.2 Universal asynchronous receiver/transmitter with LIN support
(LINUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.9.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.9.4 Inter integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.10 Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8 Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 68
10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 70
10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.8 TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 80
10.3.9 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.3.10 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.1 LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.4 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.5 VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.6.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.6.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 110

12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

13 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

13.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . .112
13.1.1 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
13.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

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STM8AF6388 List of tables

List of tables

Table 1. STM8AF6369/8x/Ax product line-up without CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. Peripheral clock gating bits (CLK_PCKENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3. Peripheral clock gating bits (CLK_PCKENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. TIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. ADC naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Legend/abbreviation for the pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. STM8AF6388 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. Memory model 128K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 11. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 12. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 13. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 14. Temporary memory unprotection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 15. STM8A interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 16. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 17. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 18. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 19. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 20. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 21. Operating lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 22. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 23. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 24. Total current consumption in Run, Wait and Slow mode. General conditions
for VDD apply, TA = -40 °C to 150 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 25. Total current consumption in Halt and Active-halt modes. General conditions for VDD
applied. TA = -40 °C to 55 °C unless otherwise stated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 26. Oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 27. Programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 28. Typical peripheral current consumption VDD = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 29. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 30. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 31. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 32. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 33. Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 34. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 35. Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 36. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 37. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 38. TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 39. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 40. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 41. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 42. ADC accuracy for VDDA = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 43. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 44. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 45. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 46. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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Table 47. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 49. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 50. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 51. VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 52. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 53. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

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STM8AF6388 List of figures

List of figures

Figure 1. STM8AF6388 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Flash memory organization of STM8A products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 4. LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5. LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6. STM8AF62xx LQFP/VFQFPN 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7. STM8AF52x6 VFQFPN32 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 11. fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 12. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 13. Typ. IDD(RUN)HSE vs. VDD @fCPU = 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 67
Figure 14. Typ. IDD(RUN)HSE vs. fCPU @ VDD = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 15. Typ. IDD(RUN)HSI vs. VDD @ fCPU = 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. Typ. IDD(WFI)HSE vs. VDD @ fCPU = 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 67
Figure 17. Typ. IDD(WFI)HSE vs. fCPU @ VDD = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 18. Typ. IDD(WFI)HSI vs. VDD @ fCPU = 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 67
Figure 19. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 20. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 21. Typical HSI frequency vs VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 22. Typical LSI frequency vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23. Typical VIL and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 24. Typical pull-up resistance RPU vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 25. Typical pull-up current Ipu vs VDD @ four temperatures(1) . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 26. Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 27. Typ. VOL @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 28. Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 29. Typ. VOL @ VDD = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 30. Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 31. Typ. VOL @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 33. Typ. VDD - VOH @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 34. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 35. Typ. VDD - VOH @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 36. Typical NRST VIL and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 37. Typical NRST pull-up resistance RPU vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 38. Typical NRST pull-up current Ipu vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 39. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 40. SPI timing diagram in slave mode and with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 41. SPI timing diagram in slave mode and with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 42. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 43. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 44. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 45. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 90
Figure 46. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 47. LQFP80 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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List of figures STM8AF6388

Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 94

Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 50. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 97
Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 53. LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 54. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 101
Figure 55. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 56. LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 57. VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 58. VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 59. VFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 60. STM8AF6388 ordering information scheme1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

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STM8AF6388 Introduction

1 Introduction

This datasheet refers to the STM8AF6388 products with 32 to 128 Kbytes of program
memory.
In the order code, the letter ‘F’ refers to product versions with Flash and data EEPROM and
‘P’ to product versions with FASTROM. The identifiers ‘F’ and ‘P’ do not coexist in a given
order code.
The datasheet contains the description of family features, pinout, electrical characteristics,
mechanical data and ordering information.
• For complete information on the STM8A microcontroller memory, registers and
peripherals, please refer to STM8S series and STM8AF series 8-bit microcontrollers
reference manual (RM0016).
• For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S and STM8A Flash programming manual (PM0051).
• For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
• For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).

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Description STM8AF6388

2 Description

The STM8AF6388 automotive 8-bit microcontrollers described in this datasheet offer from
32 Kbytes to 128 Kbytes of non volatile memory and integrated true data EEPROM. They
are referred to as high density STM8A devices in STM8S series and STM8AF series 8-bit
microcontrollers reference manual (RM0016).
All devices of the STM8A product line provide the following benefits: reduced system cost,
performance and robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k
write/erase cycles and a high system integration level with internal clock oscillators,
wtachdog, and brown-out reset.
Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to application scalability across a common
family product architecture with compatible pinout, memory map, and modular peripherals.
Full documentation is offered with a wide choice of development tools.
Product longevity is ensured in the STM8A family thanks to their advanced core which is
made in a state-of-the art technology for automotive applications with 3.3 V to 5.5 V
operating supply.
All STM8A and ST7 microcontrollers are supported by the same tools including
STVD/STVP development environment, the STice emulator and a low-cost, third party in-
circuit debugging tool.

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STM8AF6388 Product line-up

3 Product line-up

Table 1 presents the line-up of related products available upon request;

Table 1. STM8AF6369/8x/Ax product line-up without CAN

High
density
Data 10-bit I/0
Flash RAM Timers Serial
Order code Package EEPROM A/D wakeup
program (bytes) (IC/OC/PWM) interfaces
(bytes) chan. pins
memory
(bytes)

STM8AF/P63AA LQFP80 128 K

68/37
STM8AF/P638A (14x14) 64 K 2K
STM8AF/P63A9 128 K 16 1x8-bit: TIM4
LIN(UART),
LQFP64 3x16-bit: TIM1,
STM8AF/P6389 64 K 2K SPI, 52/36
(10x10) TIM2, TIM3
USART, I²C
STM8AF/P6369 32 K 1K (9/9/9)
6K
STM8AF/P63A8 LQFP48 128 K
10 38/35
STM8AF/P6388 (7x7)

LQFP32 64 K
STM8AF/P6386 2K 1x8-bit: TIM4
(7x7) 3x16-bit: TIM1, LIN(UART),
7 25/23
VFQFPN32 TIM2, TIM3 SPI, I²C
STM8AF/P63A6 128 K (8/8/8)
(5x5)

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Block diagram STM8AF6388

4 Block diagram

Figure 1. STM8AF6388 block diagram

Reset block XTAL 1- 24 MHz

Clock controller
Reset Reset
RC int. 16 MHz

Detector
POR BOR RC int. 128 kHz

Clock to peripherals and core

Window WDG
STM8A core

Independent WDG

Single wire Debug/SWIM Up to 128 Kbyte

debug interface high-density
program Flash

Master/slave
automatic USART Up to 2 Kbyte
resynchronization data EEPROM
Address and data bus

Up to 6 Kbyte RAM
400 Kbit/s I2C

Boot ROM
10 Mbit/s SPI

16-bit advanced control

LIN master timer (TIM1)
LINUART
SPI emul.

16-bit general purpose Up to

timers (TIM2, TIM3) 9 CAPCOM
channels

8-bit AR timer
(TIM4)
Up to 16 channels 10-bit ADC
AWU timer

MS38338V1

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STM8AF6388 Block diagram

1. Legend:
ADC: Analog-to-digital converter
BOR: Brownout reset
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent window watchdog
LINUART: Local interconnect network universal asynchronous receiver transmitter
POR: Power on reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
Window WDG: Window watchdog

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Product overview STM8AF6388

5 Product overview

This section is intended to describe the family features that are actually implemented in the
products covered by this datasheet.
For more detailed information on each feature please refer to STM8S series and STM8AF
series 8-bit microcontrollers reference manual (RM0016).

5.1 STM8A central processing unit (CPU)

The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency
and performance. It contains 21 internal registers (six directly addressable in each
execution context), 20 addressing modes including indexed indirect and relative addressing
and 80 instructions.

5.1.1 Architecture and registers

• Harvard architecture
• 3-stage pipeline
• 32-bit wide program memory bus with single cycle fetching for most instructions
• X and Y 16-bit index registers, enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
• 8-bit accumulator
• 24-bit program counter with 16-Mbyte linear memory space
• 16-bit stack pointer with access to a 64 Kbyte stack
• 8-bit condition code register with seven condition flags for the result of the last
instruction.

5.1.2 Addressing
• 20 addressing modes
• Indexed indirect addressing mode for look-up tables located anywhere in the address
space
• Stack pointer relative addressing mode for efficient implementation of local variables
and parameter passing

5.1.3 Instruction set

• 80 instructions with 2-byte average instruction size
• Standard data movement and logic/arithmetic functions
• 8-bit by 8-bit multiplication
• 16-bit by 8-bit and 16-bit by 16-bit division
• Bit manipulation
• Data transfer between stack and accumulator (push/pop) with direct stack access
• Data transfer using the X and Y registers or direct memory-to-memory transfers

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5.2 Single wire interface module (SWIM) and debug module (DM)

5.2.1 SWIM
The single wire interface module, SWIM, together with an integrated debug module, permits
non-intrusive, real-time in-circuit debugging and fast memory programming. The interface
can be activated in all device operation modes and can be connected to a running device
(hot plugging).The maximum data transmission speed is 145 bytes/ms.

5.2.2 Debug module

The non-intrusive debugging module features a performance close to a full-flavored
emulator. Besides memory and peripheral operation, CPU operation can also be monitored
in real-time by means of shadow registers.
• R/W of RAM and peripheral registers in real-time
• R/W for all resources when the application is stopped
• Breakpoints on all program-memory instructions (software breakpoints), except the
interrupt vector table
• Two advanced breakpoints and 23 predefined breakpoint configurations

5.3 Interrupt controller

• Nested interrupts with three software priority levels
• 24 interrupt vectors with hardware priority
• Five vectors for external interrupts (up to 37 depending on the package)
• Trap and reset interrupts

5.4 Flash program and data EEPROM

• 32 Kbytes to 128 Kbytes of high density single voltage Flash program memory
• Up to 2 Kbytes true (not emulated) data EEPROM
• Read while write: writing in the data memory is possible while executing code in the
Flash program memory.
The whole Flash program memory and data EEPROM are factory programmed with 0x00.

5.4.1 Architecture
• The memory is organized in blocks of 128 bytes each
• Read granularity: 1 word = 4 bytes
• Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel
• Writing, erasing, word and block management is handled automatically by the memory
interface.

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5.4.2 Write protection (WP)

Write protection in application mode is intended to avoid unintentional overwriting of the
memory. The write protection can be removed temporarily by executing a specific sequence
in the user software.

5.4.3 Protection of user boot code (UBC)

If the user chooses to update the Flash program memory using a specific boot code to
perform in application programming (IAP), this boot code needs to be protected against
unwanted modification.
In the STM8A a memory area of up to 128 Kbytes can be protected from overwriting at user
option level. Other than the standard write protection, the UBC protection can exclusively be
modified via the debug interface, the user software cannot modify the UBC protection
status.
The UBC memory area contains the reset and interrupt vectors and its size can be adjusted
in increments of 512 bytes by programming the UBC and NUBC option bytes
(see Section 9: Option bytes on page 54).

Figure 2. Flash memory organization of STM8A products

Data Data memory area

EEPROM
memory
Option bytes

Programmable
area from 1 Kbyte
UBC area
(first two pages) up to
Remains write protected during IAP
program memory end -
maximum 128 Kbyte

Flash program
memory
Flash program memory area
Write access possible for IAP

MS38339V1

5.4.4 Read-out protection (ROP)

The STM8A provides a read-out protection of the code and data memory which can be
activated by an option byte setting (see the ROP option byte in section 10).
The read-out protection prevents reading and writing Flash program memory, data memory
and option bytes via the debug module and SWIM interface. This protection is active in all
device operation modes. Any attempt to remove the protection by overwriting the ROP
option byte triggers a global erase of the program and data memory.

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The ROP circuit may provide a temporary access for debugging or failure analysis. The
temporary read access is protected by a user defined, 8-byte keyword stored in the option
byte area. This keyword must be entered via the SWIM interface to temporarily unlock the
device.
If desired, the temporary unlock mechanism can be permanently disabled by the user
through OPT6/NOPT6 option bytes.

5.5 Clock controller

The clock controller distributes the system clock coming from different oscillators to the core
and the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness.

5.5.1 Features
• Clock sources
– 16 MHz high-speed internal RC oscillator (HSI)
– 128 kHz low-speed internal RC (LSI)
– 1-24 MHz high-speed external crystal (HSE)
– Up to 24 MHz high-speed user-external clock (HSE user-ext)
• Reset: After reset the microcontroller restarts by default with an internal 2-MHz clock
(16 MHz/8). The clock source and speed can be changed by the application program
as soon as the code execution starts.
• Safe clock switching: Clock sources can be changed safely on the fly in Run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
• Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• Wakeup: In case the device wakes up from low-power modes, the internal RC
oscillator (16 MHz/8) is used for quick startup. After a stabilization time, the device
switches to the clock source that was selected before Halt mode was entered.
• Clock security system (CSS): The CSS permits monitoring of external clock sources
and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.
• Configurable main clock output (CCO): This feature permits to output a clock signal
for use by the application.

5.5.2 16 MHz high-speed internal RC oscillator (HSI)

• Default clock after reset 2 MHz (16 MHz/8)
• Fast wakeup time

User trimming
The register CLK_HSITRIMR with two trimming bits plus one additional bit for the sign
permits frequency tuning by the application program. The adjustment range covers all
possible frequency variations versus supply voltage and temperature. This trimming does
not change the initial production setting.

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5.5.3 128 kHz low-speed internal RC oscillator (LSI)

The frequency of this clock is 128 kHz and it is independent from the main clock. It drives
the independent watchdog or the AWU wakeup timer.
In systems which do not need independent clock sources for the watchdog counters, the
128 kHz signal can be used as the system clock. This configuration has to be enabled by
setting an option byte (OPT3/OPT3N, bit LSI_EN).

5.5.4 24 MHz high-speed external crystal oscillator (HSE)

The external high-speed crystal oscillator can be selected to deliver the main clock in
normal Run mode. It operates with quartz crystals and ceramic resonators.
• Frequency range: 1 MHz to 24 MHz
• Crystal oscillation mode: preferred fundamental
• I/Os: standard I/O pins multiplexed with OSCIN, OSCOUT

5.5.5 External clock input

An external clock signal can be applied to the OSCIN input pin of the crystal oscillator. The
frequency range is 0 to 24 MHz.

5.5.6 Clock security system (CSS)

The clock security system protects against a system stall in case of an external crystal clock
failure.
In case of a clock failure an interrupt is generated and the high-speed internal clock (HSI) is
automatically selected with a frequency of 2 MHz (16 MHz/8).

Table 2. Peripheral clock gating bits (CLK_PCKENR1)

Control bit Peripheral

PCKEN17 TIM1
PCKEN16 TIM3
PCKEN15 TIM2
PCKEN14 TIM4
PCKEN13 LINUART
PCKEN12 USART
PCKEN11 SPI
PCKEN10 I 2C

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Table 3. Peripheral clock gating bits (CLK_PCKENR2)

Control bit Peripheral

PCKEN27 -
PCKEN26 Reserved
PCKEN25 Reserved
PCKEN24 Reserved
PCKEN23 ADC
PCKEN22 AWU
PCKEN21 Reserved
PCKEN20 Reserved

5.6 Low-power operating modes

For efficient power management, the application can be put in one of four different low-
power modes. Users can configure each mode to obtain the best compromise between
lowest power consumption, fastest start-up time and available wakeup sources.
• Wait mode
In this mode, the CPU is stopped but peripherals are kept running. The wakeup is
performed by an internal or external interrupt or reset.
• Active-halt mode with regulator on
In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is
generated at programmable intervals by the auto wake up unit (AWU). The main
voltage regulator is kept powered on, so current consumption is higher than in Active-
halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the
internal AWU interrupt, external interrupt or reset.
• Active-halt mode with regulator off
This mode is the same as Active-halt with regulator on, except that the main voltage
regulator is powered off, so the wake up time is slower.
• Halt mode
CPU and peripheral clocks are stopped, the main voltage regulator is powered off.
Wakeup is triggered by external event or reset.
In all modes the CPU and peripherals remain permanently powered on, the system clock is
applied only to selected modules. The RAM content is preserved and the brown-out reset
circuit remains activated.

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5.7 Timers

5.7.1 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to
the applications. The watchdog timer activity is controlled by the application program or
option bytes. Once the watchdog is activated, it cannot be disabled by the user program
without going through reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
timing perfectly. The application software must refresh the counter before time-out and
during a limited time window. If the counter is refreshed outside this time window, a reset is
issued.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve malfunctions due to hardware
or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure. If the hardware watchdog feature is enabled through the device
option bits, the watchdog is automatically enabled at power-on, and generates a reset
unless the key register is written by software before the counter reaches the end of count.

5.7.2 Auto-wakeup counter

This counter is used to cyclically wakeup the device in Active-halt mode. It can be clocked
by the internal 128 kHz internal low-frequency RC oscillator or external clock.
LSI clock can be internally connected to TIM3 input capture channel 1 for calibration.

5.7.3 Beeper
This function generates a rectangular signal in the range of 1, 2 or 4 kHz which can be
output on a pin. This is useful when audible sounds without interference need to be
generated for use in the application.

5.7.4 Advanced control and general purpose timers

STM8A devices described in this datasheet, contain up to three 16-bit advanced control and
general purpose timers providing nine CAPCOM channels in total. A CAPCOM channel can
be used either as input compare, output compare or PWM channel. These timers are
named TIM1, TIM2 and TIM3.

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Table 4. Advanced control and general purpose timers

Counter Counter Prescaler Inverted Repetition trigger External Break
Timer Channels
width type factor outputs counter unit trigger input

TIM1 16-bit Up/down 1 to 65536 4 3 Yes Yes Yes Yes

2n
TIM2 16-bit Up 3 None No No No No
n = 0 to 15
2n
TIM3 16-bit Up 2 None No No No No
n = 0 to 15

TIM1 - advanced control timer

This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and bridge driver.
• 16-bit up, down and up/down AR (auto-reload) counter with 16-bit fractional prescaler.
• Four independent CAPCOM channels configurable as input capture, output compare,
PWM generation (edge and center aligned mode) and single pulse mode output
• Trigger module which allows the interaction of TIM1 with other on-chip peripherals. In
the present implementation it is possible to trigger the ADC upon a timer event.
• External trigger to change the timer behavior depending on external signals
• Break input to force the timer outputs into a defined state
• Three complementary outputs with adjustable dead time
• Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break

TIM2, TIM3 - 16-bit general purpose timers

• 16-bit auto-reload up-counter
• 15-bit prescaler adjustable to fixed power of two ratios 1…32768
• Timers with three or two individually configurable CAPCOM channels
• Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

5.7.5 Basic timer

The typical usage of this timer (TIM4) is the generation of a clock tick.

Table 5. TIM4
Counter Counter Prescaler Inverted Repetition trigger External Break
Timer Channels
width type factor outputs counter unit trigger input

2n
TIM4 8-bit Up 0 None No No No No
n = 0 to 7

• 8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128
• Clock source: master clock
• Interrupt source: 1 x overflow/update

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5.8 Analog to digital converter (ADC)

The STM8A products described in this datasheet contain a 10-bit successive approximation
ADC with up to 16 multiplexed input channels, depending on the package.
The ADC name differs between the datasheet and the STM8A/S reference manual (see
Table 6).

Table 6. ADC naming

Peripheral name in reference manual
Peripheral name in datasheet
(RM0016)

ADC ADC2

ADC features
• 10-bit resolution
• Single and continuous conversion modes
• Programmable prescaler: fMASTER divided by 2 to 18
• Conversion trigger on timer events, and external events
• Interrupt generation at end of conversion
• Selectable alignment of 10-bit data in 2 x 8 bit result registers
• Shadow registers for data consistency
• ADC input range: VSSA ≤VIN ≤VDDA
• Schmitt-trigger on analog inputs can be disabled to reduce power consumption

5.9 Communication interfaces

The following sections give a brief overview of the communication peripheral. Some
peripheral names differ between the datasheet and STM8S series and STM8AF series 8-bit
microcontrollers reference manual (see Table 7).

Table 7. Communication peripheral naming correspondence

Peripheral name in reference manual
Peripheral name in datasheet
(RM0016)

USART UART1
LINUART UART3

5.9.1 Universal synchronous/asynchronous receiver transmitter (USART)

The devices covered by this datasheet contain one USART interface. The USART can
operate in standard SCI mode (serial communication interface, asynchronous) or in SPI
emulation mode. It is equipped with a 16 bit fractional prescaler. It features LIN master
support.

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Detailed feature list:

• Full duplex, asynchronous communications
• NRZ standard format (mark/space)
• High-precision baud rate generator system
– Common programmable transmit and receive baud rates up to fMASTER/16
• Programmable data word length (8 or 9 bits)
• Configurable stop bits: Support for 1 or 2 stop bits
• LIN master mode:
– LIN break and delimiter generation
– LIN break and delimiter detection with separate flag and interrupt source for
readback checking.
• Transmitter clock output for synchronous communication
• Separate enable bits for transmitter and receiver
• Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
– End of transmission flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Four error detection flags:
– Overrun error
– Noise error
– Frame error
– Parity error
• Six interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Parity error
– LIN break and delimiter detection
• Two interrupt vectors:
– Transmitter interrupt
– Receiver interrupt
• Reduced power consumption mode
• Wakeup from mute mode (by idle line detection or address mark detection)
• Two receiver wakeup modes:
– Address bit (MSB)
– Idle line

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5.9.2 Universal asynchronous receiver/transmitter with LIN support

(LINUART)
The devices covered by this datasheet contain one LINUART interface. The interface is
available on all the supported packages. The LINUART is an asynchronous serial
communication interface which supports extensive LIN functions tailored for LIN slave
applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.2.
Detailed feature list:

LIN mode
Master mode
• LIN break and delimiter generation
• LIN break and delimiter detection with separate flag and interrupt source for read back
checking.
Slave mode
• Autonomous header handling – one single interrupt per valid header
• Mute mode to filter responses
• Identifier parity error checking
• LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI)
clock source
• Break detection at any time, even during a byte reception
• Header errors detection:
– Delimiter too short
– Synch field error
– Deviation error (if automatic resynchronization is enabled)
– Framing error in synch field or identifier field
– Header time-out

UART mode
• Full duplex, asynchronous communications - NRZ standard format (mark/space)
• High-precision baud rate generator
– A common programmable transmit and receive baud rates up to fMASTER/16
• Programmable data word length (8 or 9 bits) – 1 or 2 stop bits – parity control
• Separate enable bits for transmitter and receiver
• Error detection flags
• Reduced power consumption mode
• Multi-processor communication - enter mute mode if address match does not occur
• Wakeup from mute mode (by idle line detection or address mark detection)
• Two receiver wakeup modes:
– Address bit (MSB)
– Idle line

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5.9.3 Serial peripheral interface (SPI)

The devices covered by this datasheet contain one SPI. The SPI is available on all the
supported packages.
• Maximum speed: 10 Mbit/s or fMASTER/2 for master, 8 Mbit/s or fMASTER /2 for slave
• Full duplex synchronous transfers
• Simplex synchronous transfers on two lines with a possible bidirectional data line
• Master or slave operation - selectable by hardware or software
• CRC calculation
• 1 byte Tx and Rx buffer
• Slave mode/master mode management by hardware or software for both master and
slave
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Dedicated transmission and reception flags with interrupt capability
• SPI bus busy status flag
• Hardware CRC feature for reliable communication:
– CRC value can be transmitted as last byte in Tx mode
– CRC error checking for last received byte

5.9.4 Inter integrated circuit (I2C) interface

The devices covered by this datasheet contain one I2C interface. The interface is available
on all the supported packages.
• I2C master features:
– Clock generation
– Start and stop generation
2
• I C slave features:
– Programmable I2C address detection
– Stop bit detection
• Generation and detection of 7-bit/10-bit addressing and general call
• Supports different communication speeds:
– Standard speed (up to 100 kHz),
– Fast speed (up to 400 kHz)
• Status flags:
– Transmitter/receiver mode flag
– End-of-byte transmission flag
– I2C busy flag
• Error flags:
– Arbitration lost condition for master mode
– Acknowledgement failure after address/data transmission
– Detection of misplaced start or stop condition
– Overrun/underrun if clock stretching is disabled

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• Interrupt:
– Successful address/data communication
– Error condition
– Wakeup from Halt
• Wakeup from Halt on address detection in slave mode

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5.10 Input/output specifications

The product features four I/O types:
• Standard I/O 2 MHz
• Fast I/O up to 10 MHz
• High sink 8 mA, 2 MHz
• True open drain (I2C interface)
To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum
slew rate. The rise and fall times are similar to those of standard I/Os.
The analog inputs are equipped with a low leakage analog switch. Additionally, the schmitt-
trigger input stage on the analog I/Os can be disabled in order to reduce the device standby
consumption.
STM8A I/Os are designed to withstand current injection. For a negative injection current of
4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. Thanks to
this feature, external protection diodes against current injection are no longer required.

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6 Pinouts and pin description

6.1 Package pinouts

Figure 3. LQFP 80-pin pinout

PD4 (HS)/TIM2_CH1/BEEP
PD3 (HS)/TIM2_CH2
PD2 (HS)/TIM3_CH1

PD0 (HS)/TIM3_CH2
PD6/LINUART_RX
PD5/LINUART_TX

PE3/TIM1_BKIN
PD1 (HS)/SWIM

PE0/CLK_CCO

PE2/I 2C_SDA
PE1/I2C_SCL
PD7/TLI

PG7
PG6
PG5
PE4
PI7
PI6

PI5
PI4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
NRST 1 60 PI3
OSCIN/PA1 2 59 PI2
OSCOUT/PA2 3 58 PI1
VSSIO_1 4 57 PI0
VSS 5 56 PG4
VCAP 6 55 PG3
VDD 7 54 PG2
VDDIO_1 8 53 PG1
TIM2_CH3/PA3 9 52 PG0
USART_RX/PA4 10 51 PC7/SPI_MISO
USART_TX/PA5 11 50 PC6/SPI_MOSI
USART_CK/PA6 12 49 VDDIO_2
(HS) PH0 13 48 VSSIO_2
(HS) PH1 14 47 PC5/SPI_SCK
PH2 15 46 PC4 (HS)/TIM1_CH4
PH3 16 45 PC3 (HS)/TIM1_CH3
AIN15/PF7 17 44 PC2 (HS)/TIM1_CH2
AIN14/PF6 18 43 PC1 (HS)/TIM1_CH1
AIN13/PF5 19 42 PC0/ADC_ETR
AIN12/PF4 20 41 PE5/SPI_NSS
21
22
23
24
25
26
27
28
29
30

32

34
35
36
37
38
39
40
31

33
VREF+

VREF-
AIN11/PF3

AIN10/PF0
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4
AIN3/PB3
AIN2/PB2
AIN1/PB1
AIN0/PB0
TIM1_ETR/PH4
TIM1_CH3N/PH5
TIM1_CH2N/PH6
TIM1_CH1N/PH7
AIN8/PE7
AIN9/PE6
VDDA
VSSA

2. (HS) stands for high sink capability.

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Figure 4. LQFP 64-pin pinout

PD3 (HS)/TIM2_CH2/ADC_ETR
PD4 (HS)/TIM2_CH1/ BEEP

PD2 (HS)/TIM3_CH1

PD0 (HS)/TIM3_CH2
PD6/LINUART_RX
PD5/LINUART_TX

PE3/TIM1_BKIN
PD1 (HS)/SWIM

PE0/CLK_CCO

PE2/I2C_SDA
PE1/I2C_SCL
PD7/TLI

PG7
PG6
PG5
PE4
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NRST 1 48 PI0
OSCIN/PA1 2 47 PG4
OSCOUT/PA2 3 46 PG3
VSSIO_1 4 45 PG2
VSS 5 44 PG1
VCAP 6 43 PG0
VDD 7 42 PC7/SPI_MISO
VDDIO_1 8 41 PC6/SPI_MOSI
TIM2_CH3/PA3 9 40 VDDIO_2
USART_RX/PA4 10 39 VSSIO_2
USART_TX/PA5 11 38 PC5/SPI_SCK
USART_CK/PA6 12 37 PC4 (HS)/TIM1_CH4
AIN15/PF7 13 36 PC3 (HS)/TIM1_CH3
AIN14/PF6 14 35 PC2 (HS)/TIM1_CH2
AIN13/PF5 15 34 PC1 (HS)/TIM1_CH1
AIN12/PF4 16 33 PE5/SPI_NSS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AIN11/PF3
VREF+

AIN10/PF0
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4

TIM1_CH3N/AIN2/PB2
TIM1_CH2N/AIN1/PB1
TIM1_CH1N/AIN0/PB0
AIN8/PE7
AIN9/PE6
TIM1_ETR/AIN3/PB3
VDDA
VSSA
VREF-

3. HS stands for high sink capability.

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Figure 5. LQFP 48-pin pinout

PD3 (HS)/TIM2_CH2/ADC_ETR
PD4 (HS)/TIM2_CH1/BEEP

PD2 (HS)/TIM3_CH1

PD0 (HS)/TIM3_CH2
PD6/LINUART_RX
PD5/LINUART_TX

PE3/TIM1_BKIN
PD1 (HS)/SWIM

PE0/CLK_CCO

PE2/I2C_SDA
PE1/I2C_SCL
PD7/TLI
48 47 46 45 44 43 42 41 40 39 38 37
NRST 1 36 PG1
OSCIN/PA1 2 35 PG0
OSCOUT/PA2 3 34 PC7/SPI_MISO
VSSIO_1 4 33 PC6/SPI_MOSI
VSS 5 32 VDDIO_2
VCAP 6 31 VSSIO_2
VDD 7 30 PC5/SPI_SCK
VDDIO_1 8 29 PC4 (HS)/TIM1_CH4
TIM2_CH3/PA3 9 28 PC3 (HS)/TIM1_CH3
USART_RX/PA4 10 27 PC2 (HS)/TIM1_CH2
USART_TX/PA5 11 26 PC1 (HS)/TIM1_CH1
USART_CK/PA6 12 25 PE5/SPI_NSS
13 14 15 16 17 18 19 20 21 2223 24
VDDA
VSSA

TIM1_CH3N/AIN2/PB2
TIM1_CH2N/AIN1/PB1
TIM1_CH1N/AIN0/PB0
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4
TIM1_ETR/AIN3/PB3

AIN8/PE7
AIN9/PE6

4. HS stands for high sink capability.

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Figure 6. STM8AF62xx LQFP/VFQFPN 32-pin pinout

PD0 (HS)/TIM3_CH2/CLK_CCO/TIM1_BRK
PD2 (HS)/TIM3_CH1/TIM2_CH3
PD3 (HS)/TIM2_CH2/ADC_ETR
PD4 (HS)/TIM2_CH1/BEEP
PD6/LINUART_RX
PD5/LINUART_TX

PD1 (HS)/SWIM
PD7/TLI
32 31 30 29 28 27 26 25
NRST 1 24 PC7/SPI_MISO
OSCIN/PA1 2 23 PC6/SPI_MOSI
OSCOUT/PA2 3 22 PC5/SPI_SCK
VSS 4 21 PC4 (HS)/TIM1_CH4
VCAP 5 20 PC3 (HS)/TIM1_CH3
VDD 6 19 PC2 (HS)/TIM1_CH2
VDDIO 7 18 PC1 (HS)/TIM1_CH1
AIN12/PF4 8 17 PE5/SPI_NSS
9 10 11 12 13 14 1516
VDDA
VSSA
I2C_SDA/AIN5/PB5
I2C_SCL/AIN4/PB4
TIM1_ETR/AIN3/PB3
TIM1_CH3N/AIN2/PB2
TIM1_CH2N/AIN1/PB1
TIM1_CH1N/AIN0/PB0

1. HS stands for high sink capability.

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Figure 7. STM8AF52x6 VFQFPN32 32-pin pinout

PD0 (HS)/TIM3_CH2/CLK_CCO/TIM1_BRK
PD2 (HS)/TIM3_CH1/TIM2_CH3
PD3 (HS)/TIM2_CH2/ADC_ETR
PD4 (HS)/TIM2_CH1/BEEP
PD6/LINUART_RX

D5/LINUART_TX

PD1 (HS)/SWIM
PD7/TLI

32 31 30 29 28 27 26 25
NRST 1 24 PG1

OSCIN/PA1 2 23 PG0

OSCOUT/PA2 3 22 PC5

V SS 4 21 PC4 (HS)/TIM1_CH4

VCAP 5 20 PC3 (HS)/TIM1_CH3

V DD 6 19 PC2 (HS)/TIM1_CH2
V DDIO 7 18 PC1 (HS)/TIM1_CH1

PA6 8 17 PE5
9 10 11 12 13 14 15 16
V DDA

V SSA

TIM1_CH3N/AIN2/PB2

TIM1_CH2N/AIN1/PB1

TIM1_CH1N/AIN0/PB0
TIM1_ETR/AIN3/PB3
I2C_SDA/AIN5/PB5

I2C_SCL/AIN4/PB4

MSv47786V1

1. The following I/O ports are not automatically configured by hardware: PA3, PA4, PA5, PA6, PF4, PB6,
PB7, PE0, PE1, PE2, PE3, PE6, PE7. As a consequence, they must be put into one of the following
configurations by software:
- configured as input with internal pull-up/down resistor,
- configured as output push-pull low.
2. HS stands for high sink capability.

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Table 8. Legend/abbreviation for the pin description table

Type I= input, O = output, S = power supply
Input CM = CMOS (standard for all I/Os)
Level
Output HS = high sink (8 mA)
O1 = Standard (up to 2 MHz)
O2 = Fast (up to 10 MHz)
Output speed
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset

Port and control Input float = floating, wpu = weak pull-up

configuration Output T = true open drain, OD = open drain, PP = push pull
Bold X (pin state after reset release).
Reset state Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).

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Table 9. STM8AF6388 pin description

Pin number Input Output

LQFP32/VFQFPN32

Main Alternate

Ext. interrupt
STM8AF62xx

Default
function function

High sink
Type

Floating
LQFP80
LQFP64
LQFP48

Pin name alternate

Speed
(after after remap

Wpu

OD

PP
function
reset) [option bit]

1 1 1 1 NRST I/O - X - - - - - Reset -

Resonator/
2 2 2 2 PA1/OSCIN(1) I/O X X - - O1 X X Port A1 -
crystal in
Resonator/
3 3 3 3 PA2/OSCOUT I/O X X X - O1 X X Port A2 -
crystal out
4 4 4 - VSSIO_1 S - - - - - - - I/O ground -
5 5 5 4 VSS S - - - - - - - Digital ground -
1.8 V regulator
6 6 6 5 VCAP S - - - - - - - -
capacitor
7 7 7 6 VDD S - - - - - - - Digital power supply -
8 8 8 7 VDDIO_1 S - - - - - - - I/O power supply -
Timer 2 - TIM3_CH1
9 9 9 - PA3/TIM2_CH3 I/O X X X - O1 X X Port A3
channel 3 [AFR1]
USART
10 10 10 - PA4/USART_RX I/O X X X - O3 X X Port A4 -
receive
USART
11 11 11 - PA5/USART_TX I/O X X X - O3 X X Port A5 -
transmit
USART
12 12 12 - PA6/USART_CK I/O X X X - O3 X X Port A6 synchro -
nous clock
13 - - - PH0 I/O X X - HS O3 X X Port H0 - -
14 - - - PH1 I/O X X - HS O3 X X Port H1 - -
15 - - - PH2 I/O X X - - O1 X X Port H2 - -
16 - - - PH3 I/O X X - - O1 X X Port H3 - -
Analog
17 13 - - PF7/AIN15 I/O X X - - O1 X X Port F7 -
input 15
Analog
18 14 - - PF6/AIN14 I/O X X - - O1 X X Port F6 -
input 14
Analog
19 15 - - PF5/AIN13 I/O X X - - O1 X X Port F5 -
input 13
Analog
20 16 - 8 PF4/AIN12 I/O X X - - O1 X X Port F4 -
input 12
Analog
21 17 - - PF3/AIN11 I/O X X - - O1 X X Port F3 -
input 11

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Table 9. STM8AF6388 pin description (continued)

Pin number Input Output

LQFP32/VFQFPN32
Main Alternate

Ext. interrupt
STM8AF62xx

Default
function function

High sink
Type

Floating
LQFP80
LQFP64
LQFP48

Pin name alternate

Speed
(after after remap

Wpu

OD

PP
function
reset) [option bit]

ADC positive reference

22 18 - - VREF+ S - - - - - - - -
voltage
23 19 13 9 VDDA S - - - - - - - Analog power supply -
24 20 14 10 VSSA S - - - - - - - Analog ground -
ADC negative
25 21 - - VREF- S - - - - - - - -
reference voltage
Analog
26 22 - - PF0/AIN10 I/O X X - - O1 X X Port F0 -
input 10
Analog
27 23 15 - PB7/AIN7 I/O X X X - O1 X X Port B7 -
input 7
Analog
28 24 16 - PB6/AIN6 I/O X X X - O1 X X Port B6 -
input 6
Analog I2C_SDA
29 25 17 11 PB5/AIN5 I/O X X X - O1 X X Port B5
input 5 [AFR6]
Analog I2C_SCL
30 26 18 12 PB4/AIN4 I/O X X X - O1 X X Port B4
input 4 [AFR6]
Analog TIM1_ETR
31 27 19 13 PB3/AIN3 I/O X X X - O1 X X Port B3
input 3 [AFR5]
Analog TIM1_CH3N
32 28 20 14 PB2/AIN2 I/O X X X - O1 X X Port B2
input [AFR5]
Analog TIM1_CH2N
33 29 21 15 PB1/AIN1 I/O X X X - O1 X X Port B1
input 1 [AFR5]
Analog TIM1_CH1N
34 30 22 16 PB0/AIN0 I/O X X X - O1 X X Port B0
input 0 [AFR5]
Timer 1 -
35 - - - PH4/TIM1_ETR I/O X X - - O1 X X Port H4 trigger -
input
Timer 1 -
PH5/
36 - - - I/O X X - - O1 X X Port H5 inverted -
TIM1_CH3N
channel 3
Timer 1 -
PH6/
37 - - - I/O X X - - O1 X X Port H6 inverted -
TIM1_CH2N
channel 2
Timer 1 -
PH7/
38 - - - I/O X X - - O1 X X Port H7 inverted -
TIM1_CH1N
channel 2

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Table 9. STM8AF6388 pin description (continued)

Pin number Input Output

LQFP32/VFQFPN32
Main Alternate

Ext. interrupt
STM8AF62xx

Default
function function

High sink
Type

Floating
LQFP80
LQFP64
LQFP48

Pin name alternate

Speed
(after after remap

Wpu

OD

PP
function
reset) [option bit]

Analog
39 31 23 - PE7/AIN8 I/O X X - - O1 X X Port E7 -
input 8
Analog
40 32 24 PE6/AIN9 I/O X X X - O1 X X Port E6 -
input 9
SPI master/
41 33 25 17 PE5/SPI_NSS I/O X X X - O1 X X Port E5 -
slave select
ADC trigger
42 - - - PC0/ADC_ETR I/O X X X - O1 X X Port C0 -
input
Timer 1 -
43 34 26 18 PC1/TIM1_CH1 I/O X X X HS O3 X X Port C1 -
channel 1
Timer 1-
44 35 27 19 PC2/TIM1_CH2 I/O X X X HS O3 X X Port C2 -
channel 2
Timer 1 -
45 36 28 20 PC3/TIM1_CH3 I/O X X X HS O3 X X Port C3 -
channel 3
Timer 1 -
46 37 29 21 PC4/TIM1_CH4 I/O X X X HS O3 X X Port C4 -
channel 4
47 38 30 22 PC5/SPI_SCK I/O X X X - O3 X X Port C5 SPI clock -
48 39 31 - VSSIO_2 S - - - - - - - I/O ground -
49 40 32 - VDDIO_2 S - - - - - - - I/O power supply -
SPI master
50 41 33 23 PC6/SPI_MOSI I/O X X X - O3 X X Port C6 out/ -
slave in
SPI master
51 42 34 24 PC7/SPI_MISO I/O X X X - O3 X X Port C7 in/ slave -
out
52 43 35 - PG0 I/O X X - - O1 X X Port G0 - -
53 44 36 - PG1 I/O X X - - O1 X X Port G1 - -
54 45 - - PG2 I/O X X - - O1 X X Port G2 - -
55 46 - - PG3 I/O X X - - O1 X X Port G3 - -
56 47 - - PG4 I/O X X - - O1 X X Port G4 - -
57 48 - - PI0 I/O X X - - O1 X X Port I0 - -
58 - - - PI1 I/O X X - - O1 X X Port I1 - -
59 - - - PI2 I/O X X - - O1 X X Port I2 - -
60 - - - PI3 I/O X X - - O1 X X Port I3 - -

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Table 9. STM8AF6388 pin description (continued)

Pin number Input Output

LQFP32/VFQFPN32
Main Alternate

Ext. interrupt
STM8AF62xx

Default
function function

High sink
Type

Floating
LQFP80
LQFP64
LQFP48

Pin name alternate

Speed
(after after remap

Wpu

OD

PP
function
reset) [option bit]

61 - - - PI4 I/O X X - - O1 X X Port I4 - -

62 - - - PI5 I/O X X - - O1 X X Port I5 - -
63 49 - - PG5 I/O X X - - O1 X X Port G5 - -
64 50 - - PG6 I/O X X - - O1 X X Port G6 - -
65 51 - - PG7 I/O X X - - O1 X X Port G7 - -
66 52 - - PE4 I/O X X X - O1 X X Port E4 - -
Timer 1 -
67 53 37 - PE3/TIM1_BKIN I/O X X X - O1 X X Port E3 -
break input
68 54 38 - PE2/I2C_SDA I/O X - X - O1 T(2) - Port E2 I2C data -
2C_SCL
69 55 39 - PE1/I I/O X - X - O1 T(2) - Port E1 I2C clock -
Configurabl
70 56 40 - PE0/CLK_CCO I/O X X X - O3 X X Port E0 e clock -
output
71 - - - PI6 I/O X X - - O1 X X Port I6 - -
72 - - - PI7 I/O X X - - O1 X X Port I7 - -
TIM1_BKIN
Timer 3 - [AFR3]/
73 57 41 25 PD0/TIM3_CH2 I/O X X X HS O3 X X Port D0
channel 2 CLK_CCO
[AFR2]
SWIM data
74 58 42 26 PD1/SWIM(3) I/O X X X HS O4 X X Port D1 -
interface
Timer 3 - TIM2_CH3
75 59 43 27 PD2/TIM3_CH1 I/O X X X HS O3 X X Port D2
channel 1 [AFR1]
Timer 2 - ADC_ETR
76 60 44 28 PD3/TIM2_CH2 I/O X X X HS O3 X X Port D3
channel 2 [AFR0]
PD4/TIM2_CH1/ Timer 2 - BEEP output
77 61 45 29 I/O X X X HS O3 X X Port D4
BEEP channel 1 [AFR7]
LINUART
PD5/
78 62 46 30 I/O X X X - O1 X X Port D5 data -
LINUART_TX
transmit
LINUART
PD6/
79 63 47 31 I/O X X X - O1 X X Port D6 data -
LINUART_RX
receive
Top level
80 64 48 32 PD7/TLI(4) I/O X X X - O1 X X Port D7 -
interrupt

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Pinouts and pin description STM8AF6388

1. In Halt/Active-halt mode, this pin behaves as follows:

- The input/output path is disabled.
- If the HSE clock is used for wakeup, the internal weak pull-up is disabled.
- If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the
corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in
Halt/Active-halt mode.
2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up and protection diode to VDD are
not implemented)
3. The PD1 pin is in input pull-up during the reset phase and after reset release.
4. If this pin is configured as interrupt pin, it will trigger the TLI.

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6.2 Alternate function remapping

As shown in the rightmost column of Table 9, some alternate functions can be remapped at
different I/O ports by programming one of eight AFR (alternate function remap) option bits.
Refer to Section 9: Option bytes on page 54. When the remapping option is active, the
default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of STM8S series and STM8AF series 8-bit microcontrollers reference manual,
RM0016).

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7 Memory and register map

7.1 Memory map

Figure 8. Register and memory map
0x00 0000

6 Kbyte RAM

0x00 1400

0x00 17FF stack

Reserved

0x00 4000

up to 2 Kbyte data EEPROM

0x00 4800

Option bytes
0x00 4900
Reserved
0x00 5000

Hardware registers
0x00 5800
Reserved
0x00 6000

2 Kbyte of Boot ROM

0x00 6800

Reserved

0x00 7F00
CPU/SWIM/debug/ITC
registers
0x00 8000
Interrupt vectors
0x00 8080

Up to 128 Kbyte of Flash

program memory

Flash program memory end address

MS38340V1

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Table 10. Memory model 128K

Flash program
Flash program RAM end Stack roll-over
memory end RAM size
memory size address address
address

128 K 0x00 27FFF

64 K 0x00 17FFF 6K 0x00 17FF 0x00 1400
32 K 0x00 0FFFF

7.2 Register map

In this section the memory and register map of the devices covered by this datasheet is
described. For a detailed description of the functionality of the registers, refer to STM8S
series and STM8AF series 8-bit microcontrollers reference manual, RM0016.

Table 11. I/O port hardware register map

Reset
Address Block Register label Register name
status

0x00 5000 PA_ODR Port A data output latch register 0x00

0x00 5001 PA_IDR Port A input pin value register 0xXX(1)
0x00 5002 Port A PA_DDR Port A data direction register 0x00
0x00 5003 PA_CR1 Port A control register 1 0x00
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005 PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR Port B input pin value register 0xXX(1)
0x00 5007 Port B PB_DDR Port B data direction register 0x00
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A PC_ODR Port C data output latch register 0x00
0x00 500B PB_IDR Port C input pin value register 0xXX(1)
0x00 500C Port C PC_DDR Port C data direction register 0x00
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
0x00 500F PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0xXX(1)
0x00 5011 Port D PD_DDR Port D data direction register 0x00
0x00 5012 PD_CR1 Port D control register 1 0x02
0x00 5013 PD_CR2 Port D control register 2 0x00

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Table 11. I/O port hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5014 PE_ODR Port E data output latch register 0x00

0x00 5015 PE_IDR Port E input pin value register 0xXX(1)
0x00 5016 Port E PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
0x00 5018 PE_CR2 Port E control register 2 0x00
0x00 5019 PF_ODR Port F data output latch register 0x00
0x00 501A PF_IDR Port F input pin value register 0xXX(1)
0x00 501B Port F PF_DDR Port F data direction register 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00
0x00 501E PG_ODR Port G data output latch register 0x00
0x00 501F PG_IDR Port G input pin value register 0xXX(1)
0x00 5020 Port G PG_DDR Port G data direction register 0x00
0x00 5021 PG_CR1 Port G control register 1 0x00
0x00 5022 PG_CR2 Port G control register 2 0x00
0x00 5023 PH_ODR Port H data output latch register 0x00
0x00 5024 PH_IDR Port H input pin value register 0xXX(1)
0x00 5025 Port H PH_DDR Port H data direction register 0x00
0x00 5026 PH_CR1 Port H control register 1 0x00
0x00 5027 PH_CR2 Port H control register 2 0x00
0x00 5028 PI_ODR Port I data output latch register 0x00
0x00 5029 PI_IDR Port I input pin value register 0xXX(1)
0x00 502A Port I PI_DDR Port I data direction register 0x00
0x00 502B PI_CR1 Port I control register 1 0x00
0x00 502C PI_CR2 Port I control register 2 0x00
1. Depends on the external circuitry.

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Table 12. General hardware register map

Reset
Address Block Register label Register name
status

0x00 505A FLASH_CR1 Flash control register 1 0x00

0x00 505B FLASH_CR2 Flash control register 2 0x00
0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF
0x00 505D Flash FLASH_FPR Flash protection register 0x00
0x00 505E FLASH_NFPR Flash complementary protection register 0xFF

0x00 505F FLASH_IAPSR Flash in-application programming status 0x40

register
0x00 5060 to
Reserved area (2 bytes)
0x005061

0x00 5062 Flash FLASH_PUKR Flash Program memory unprotection 0x00

register
0x00 5063 Reserved area (1 byte)
0x00 5064 Flash FLASH_DUKR Data EEPROM unprotection register 0x00
0x00 5065 to
Reserved area (59 bytes)
0x00 509F
0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00
ITC
0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00
0x00 50A2 to
Reserved area (17 bytes)
0x00 50B2
0x00 50B3 RST RST_SR Reset status register 0xXX(1)
0x00 50B4 to
Reserved area (12 bytes)
0x00 50BF
0x00 50C0 CLK_ICKR Internal clock control register 0x01
CLK
0x00 50C1 CLK_ECKR External clock control register 0x00
0x00 50C2 Reserved area (1 byte)

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Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 50C3 CLK_CMSR Clock master status register 0xE1

0x00 50C4 CLK_SWR Clock master switch register 0xE1
0x00 50C5 CLK_SWCR Clock switch control register 0xXX
0x00 50C6 CLK_CKDIVR Clock divider register 0x18
0x00 50C7 CLK_PCKENR1 Peripheral clock gating register 1 0xFF
0x00 50C8 CLK_CSSR Clock security system register 0x00
CLK
0x00 50C9 CLK_CCOR Configurable clock control register 0x00
0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF
0x00 50CB Reserved area (1 byte)
0x00 50CC CLK_HSITRIMR HSI clock calibration trimming register 0x00
0bXXXX
0x00 50CD CLK_SWIMCCR SWIM clock control register
XXX0
0x00 50CE
Reserved area (3 bytes)
to 0x00 50D0
0x00 50D1 WWDG_CR WWDG control register 0x7F
WWDG
0x00 50D2 WWDG_WR WWDR window register 0x7F
0x00 50D3 to
Reserved area (13 bytes)
0x00 50DF
0x00 50E0 IWDG_KR IWDG key register 0xXX(2)
0x00 50E1 IWDG IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3 to
Reserved area (13 bytes)
0x00 50EF
0x00 50F0 AWU_CSR1 AWU control/status register 1 0x00
AWU asynchronous prescaler buffer
0x00 50F1 AWU AWU_APR 0x3F
register
0x00 50F2 AWU_TBR AWU timebase selection register 0x00
0x00 50F3 BEEP BEEP_CSR BEEP control/status register 0x1F
0x00 50F4 to
Reserved area (12 bytes)
0x00 50FF

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Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5200 SPI_CR1 SPI control register 1 0x00

0x00 5201 SPI_CR2 SPI control register 2 0x00
0x00 5202 SPI_ICR SPI interrupt control register 0x00
0x00 5203 SPI_SR SPI status register 0x02
SPI
0x00 5204 SPI_DR SPI data register 0x00
0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07
0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF
0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF
0x00 5208 to
Reserved area (8 bytes)
0x00 520F
0x00 5210 I2C_CR1 I2C control register 1 0x00
0x00 5211 I2C_CR2 I2C control register 2 0x00
0x00 5212 I2C_FREQR I2C frequency register 0x00
0x00 5213 I2C_OARL I2C own address register low 0x00
0x00 5214 I2C_OARH I2C own address register high 0x00
0x00 5215
0x00 5216 I2C_DR I2C data register 0x00
I2C
0x00 5217 I2C_SR1 I2C status register 1 0x00
0x00 5218 I2C_SR2 I2C status register 2 0x00
0x00 5219 I2C_SR3 I2C status register 3 0x00
0x00 521A I2C_ITR I2C interrupt control register 0x00
0x00 521B I2C_CCRL I2C clock control register low 0x00
0x00 521C I2C_CCRH I2C clock control register high 0x00
0x00 521D I2C_TRISER I2C TRISE register 0x02
0x00 521E to
Reserved area (18 bytes)
0x00 522F

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Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5230 UART1_SR USART status register 0xC0

0x00 5231 UART1_DR USART data register 0xXX
0x00 5232 UART1_BRR1 USART baud rate register 1 0x00
0x00 5233 UART1_BRR2 USART baud rate register 2 0x00
0x00 5234 UART1_CR1 USART control register 1 0x00
0x00 5235 USART UART1_CR2 USART control register 2 0x00
0x00 5236 UART1_CR3 USART control register 3 0x00
0x00 5237 UART1_CR4 USART control register 4 0x00
0x00 5238 UART1_CR5 USART control register 5 0x00
0x00 5239 UART1_GTR USART guard time register 0x00
0x00 523A UART1_PSCR USART prescaler register 0x00
0x00 523B to
Reserved area (5 bytes)
0x00 523F
0x00 5240 UART3_SR LINUART status register 0xC0
0x00 5241 UART3_DR LINUART data register 0xXX
0x00 5242 UART3_BRR1 LINUART baud rate register 1 0x00
0x00 5243 UART3_BRR2 LINUART baud rate register 2 0x00
0x00 5244 UART3_CR1 LINUART control register 1 0x00
LINUART
0x00 5245 UART3_CR2 LINUART control register 2 0x00
0x00 5246 UART3_CR3 LINUART control register 3 0x00
0x00 5247 UART3_CR4 LINUART control register 4 0x00
0x00 5248 Reserved
0x00 5249 UART3_CR6 LINUART control register 6 0x00
0x00 524A to
Reserved area (6 bytes)
0x00 524F

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Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5250 TIM1_CR1 TIM1 control register 1 0x00

0x00 5251 TIM1_CR2 TIM1 control register 2 0x00
0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00
0x00 5253 TIM1_ETR TIM1 external trigger register 0x00
0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00
0x00 5255 TIM1_SR1 TIM1 status register 1 0x00
0x00 5256 TIM1_SR2 TIM1 status register 2 0x00
0x00 5257 TIM1_EGR TIM1 event generation register 0x00
0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00
0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00
0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00
0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00
0x00 525C TIM1_CCER1 TIM1 capture/compare enable register 1 0x00
0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0x00
0x00 525E TIM1_CNTRH TIM1 counter high 0x00
0x00 525F TIM1_CNTRL TIM1 counter low 0x00
TIM1
0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00
0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00
0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF
0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF
0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00
0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00
0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00
0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00
0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00
0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00
0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00
0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00
0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00
0x00 526D TIM1_BKR TIM1 break register 0x00
0x00 526E TIM1_DTR TIM1 dead-time register 0x00
0x00 526F TIM1_OISR TIM1 output idle state register 0x00
0x00 5270 to
Reserved area (147 bytes)
0x00 52FF

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Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5300 TIM2_CR1 TIM2 control register 1 0x00

0x00 5301 TIM2_IER TIM2 interrupt enable register 0x00
0x00 5302 TIM2_SR1 TIM2 status register 1 0x00
0x00 5303 TIM2_SR2 TIM2 status register 2 0x00
0x00 5304 TIM2_EGR TIM2 event generation register 0x00
0x00 5305 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00
0x00 5306 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00
0x00 5307 TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00
0x00 5308 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00
0x00 5309 TIM2_CCER2 TIM2 capture/compare enable register 2 0x00
0x00 530A TIM2 TIM2_CNTRH TIM2 counter high 0x00
0x00 530B TIM2_CNTRL TIM2 counter low 0x00
00 530C0x TIM2_PSCR TIM2 prescaler register 0x00
0x00 530D TIM2_ARRH TIM2 auto-reload register high 0xFF
0x00 530E TIM2_ARRL TIM2 auto-reload register low 0xFF
0x00 530F TIM2_CCR1H TIM2 capture/compare register 1 high 0x00
0x00 5310 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00
0x00 5311 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0x00
0x00 5312 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00
0x00 5313 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00
0x00 5314 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00
0x00 5315 to
Reserved area (11 bytes)
0x00 531F

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Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5320 TIM3_CR1 TIM3 control register 1 0x00

0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00
0x00 5322 TIM3_SR1 TIM3 status register 1 0x00
0x00 5323 TIM3_SR2 TIM3 status register 2 0x00
0x00 5324 TIM3_EGR TIM3 event generation register 0x00
0x00 5325 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00
0x00 5326 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00
0x00 5327 TIM3_CCER1 TIM3 capture/compare enable register 1 0x00
0x00 5328 TIM3 TIM3_CNTRH TIM3 counter high 0x00
0x00 5329 TIM3_CNTRL TIM3 counter low 0x00
0x00 532A TIM3_PSCR TIM3 prescaler register 0x00
0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF
0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF
0x00 532D TIM3_CCR1H TIM3 capture/compare register 1 high 0x00
0x00 532E TIM3_CCR1L TIM3 capture/compare register 1 low 0x00
0x00 532F TIM3_CCR2H TIM3 capture/compare register 2 high 0x00
0x00 5330 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00
0x00 5331 to
Reserved area (15 bytes)
0x00 533F
0x00 5340 TIM4_CR1 TIM4 control register 1 0x00
0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00
0x00 5342 TIM4_SR TIM4 status register 0x00
0x00 5343 TIM4 TIM4_EGR TIM4 event generation register 0x00
0x00 5344 TIM4_CNTR TIM4 counter 0x00
0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00
0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF
0x00 5347 to
Reserved area (185 bytes)
0x00 53FF

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Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5400 ADC _CSR ADC control/status register 0x00

0x00 5401 ADC_CR1 ADC configuration register 1 0x00
0x00 5402 ADC_CR2 ADC configuration register 2 0x00
0x00 5403 ADC_CR3 ADC configuration register 3 0x00
ADC
0x00 5404 ADC_DRH ADC data register high 0xXX
0x00 5405 ADC_DRL ADC data register low 0xXX
0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00
0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00
0x00 5408 to
Reserved area (1015 bytes)
0x00 57FF
1. Depends on the previous reset source.
2. Write only register.

Table 13. CPU/SWIM/debug module/interrupt controller registers

Reset
Address Block Register label Register name
status

0x00 7F00 A Accumulator 0x00

0x00 7F01 PCE Program counter extended 0x00
0x00 7F02 PCH Program counter high 0x80
0x00 7F03 PCL Program counter low 0x00
0x00 7F04 XH X index register high 0x00
0x00 7F05 CPU(1) XL X index register low 0x00
0x00 7F06 YH Y index register high 0x00
0x00 7F07 YL Y index register low 0x00
0x00 7F08 SPH Stack pointer high 0x17(2)
0x00 7F09 SPL Stack pointer low 0xFF
0x00 7F0A CC Condition code register 0x28
0x00 7F0B
to 0x00 Reserved area (85 bytes)
7F5F
0x00 7F60 CPU CFG_GCR Global configuration register 0x00

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Table 13. CPU/SWIM/debug module/interrupt controller registers (continued)

Reset
Address Block Register label Register name
status

0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF

0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF
0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF
0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF
ITC
0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF
0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF
0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF
0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF
0x00 7F78
to Reserved area (2 bytes)
0x00 7F79
0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00
0x00 7F81
to Reserved area (15 bytes)
0x00 7F8F
0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF
0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF
0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF
0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF
0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF
0x00 7F95 DM DM_BK2RL DM breakpoint 2 register low byte 0xFF
0x00 7F96 DM_CR1 DM debug module control register 1 0x00
0x00 7F97 DM_CR2 DM debug module control register 2 0x00
0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10
0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00
0x00 7F9A DM_ENFCTR DM enable function register 0xFF
0x00 7F9B
to 0x00 Reserved area (5 bytes)
7F9F
1. Accessible by debug module only
2. Product dependent value, see Figure 8: Register and memory map.

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Table 14. Temporary memory unprotection registers

Reset
Address Block Register label Register name
status

0x00 5800 TMU_K1 Temporary memory unprotection key register 1 0x00

0x00 5801 TMU_K2 Temporary memory unprotection key register 2 0x00
0x00 5802 TMU_K3 Temporary memory unprotection key register 3 0x00
0x00 5803 TMU_K4 Temporary memory unprotection key register 4 0x00
0x00 5804 TMU_K5 Temporary memory unprotection key register 5 0x00
TMU
0x00 5805 TMU_K6 Temporary memory unprotection key register 6 0x00
0x00 5806 TMU_K7 Temporary memory unprotection key register 7 0x00
0x00 5807 TMU_K8 Temporary memory unprotection key register 8 0x00
Temporary memory unprotection control and status
0x00 5808 TMU_CSR 0x00
register

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8 Interrupt table

Table 15. STM8A interrupt table(1)

Interrupt vector Wakeup
Priority Source block Description Comments
address from Halt

- Reset Reset 0x00 8000 Yes -

- TRAP SW interrupt 0x00 8004 - -
0 TLI External top level interrupt 0x00 8008 - -
1 AWU Auto-wakeup from Halt 0x00 800C Yes -
Clock
2 Main clock controller 0x00 8010 - -
controller
3 MISC External interrupt E0 0x00 8014 Yes Port A interrupts
4 MISC External interrupt E1 0x00 8018 Yes Port B interrupts
5 MISC External interrupt E2 0x00 801C Yes Port C interrupts
6 MISC External interrupt E3 0x00 8020 Yes Port D interrupts
7 MISC External interrupt E4 0x00 8024 Yes Port E interrupts
8 Reserved Reserved 0x00 8028 - -
9 Reserved Reserved 0x00 802C - -
10 SPI End of transfer 0x00 8030 Yes -
Update/overflow/
11 Timer 1 0x00 8034 - -
trigger/break
12 Timer 1 Capture/compare 0x00 8038 - -
13 Timer 2 Update/overflow 0x00 803C - -
14 Timer 2 Capture/compare 0x00 8040 - -
15 Timer 3 Update/overflow 0x00 8044 - -
16 Timer 3 Capture/compare 0x00 8048 - -
17 USART Tx complete 0x00 804C - -
18 USART Receive data full reg. 0x00 8050 - -
2 2
19 I C I C interrupts 0x00 8054 Yes -
20 LINUART Tx complete/error 0x00 8058 - -
21 LINUART Receive data full reg. 0x00 805C - -
22 ADC End of conversion 0x00 8060 - -
23 Timer 4 Update/overflow 0x00 8064 - -
End of programming/
24 EEPROM 0x00 8068 - -
write in not allowed area
1. All unused interrupts must be initialized with ‘IRET’ for robust programming.

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9 Option bytes

Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Each option
byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented
one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 16: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be changed in ICP mode (via SWIM).
Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.

Table 16. Option bytes

Option Option bits Factory
Option
Addr. byte default
name
no. 7 6 5 4 3 2 1 0 setting

Read-out
0x00
protection OPT0 ROP[7:0] 0x00
4800
(ROP)
0x00
User boot OPT1 UBC[7:0] 0x00
4801
code
0x00 (UBC) NOPT1 NUBC[7:0] 0xFF
4802
0x00 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00
4803 function
0x00 remapping
(AFR) NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF
4804
0x00 LSI_ IWDG WWD WWDG
OPT3 Reserved 0x00
4805 Watchdog EN _HW G _HW _HALT
0x00 option NLSI_ NIWD NWWD NWWG
NOPT3 Reserved 0xFF
4806 EN G_HW G_HW _HALT
0x00 EXT CKAW
OPT4 Reserved PRSC1 PRSC0 0x00
4807 Clock CLK USEL
0x00 option NEXT NCKAW NPRSC
NOPT4 Reserved NPRSC1 0xFF
4808 CLK USEL 0
0x00
OPT5 HSECNT[7:0] 0x00
4809 HSE clock
0x00 startup
NOPT5 NHSECNT[7:0] 0xFF
480A

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Table 16. Option bytes (continued)

Option Option bits Factory
Option
Addr. byte default
name
no. 7 6 5 4 3 2 1 0 setting

0x00
OPT6 TMU[3:0] 0x00
480B
TMU
0x00
NOPT6 NTMU[3:0] 0xFF
480C
0x00 WAIT
OPT7 Reserved 0x00
480D Flash wait STATE
0x00 states NWAIT
NOPT7 Reserved 0xFF
480E STATE
0x00
Reserved
480F
0x00
OPT8 TMU_KEY 1 [7:0] 0x00
4810
0x00
OPT9 TMU_KEY 2 [7:0] 0x00
4811
0x00
OPT10 TMU_KEY 3 [7:0] 0x00
4812
0x00
OPT11 TMU_KEY 4 [7:0] 0x00
4813
0x00
TMU OPT12 TMU_KEY 5 [7:0] 0x00
4814
0x00
OPT13 TMU_KEY 6 [7:0] 0x00
4815
0x00
OPT14 TMU_KEY 7 [7:0] 0x00
4816
0x00
OPT15 TMU_KEY 8 [7:0] 0x00
4817
0x00
OPT16 TMU_MAXATT [7:0] 0xC7
4818
0x00
4819
Reserved
to
487D
0x00
OPT17 BL [7:0] 0x00
487E Boot-
0x00 loader(1) NOPT
NBL [7:0] 0xFF
487F 17
1. This option consists of two bytes that must have a complementary value in order to be valid. If the option is invalid, it has no
effect on EMC reset.

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Table 17. Option byte description

Option byte no. Description

ROP[7:0]: Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)
OPT0 Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers
reference manual (RM0016) section on Flash/EEPROM memory
readout protection for details.
UBC[7:0]: User boot code area
0x00: No UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
OPT1
0x03 to 0xFF: Pages 4 to 255 defined as UBC, memory write-protected
Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers
reference manual (RM0016) section on Flash/EEPROM write protection
for more details.
AFR7: Alternate function remapping option 7
0: Port D4 alternate function = TIM2_CH1
1: Port D4 alternate function = BEEP
AFR6: Alternate function remapping option 6
0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4
1: Port B5 alternate function = I2C_SDA, port B4 alternate function =
I2C_SCL.
AFR5: Alternate function remapping option 5
0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,
port B1 alternate function = AIN1, port B0 alternate function = AIN0.
1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =
TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate
function = TIM1_CH1N.
AFR4: Alternate function remapping option 4
0: Port D7 alternate function = TLI
OPT2 1: Reserved
AFR3: Alternate function remapping option 3
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = TIM1_BKIN
AFR2: Alternate function remapping option 2
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = CLK_CCO
Note: AFR2 option has priority over AFR3 if both are activated
AFR1: Alternate function remapping option 1
0: Port A3 alternate function = TIM2_CH3, port D2 alternate function
TIM3_CH1.
1: Port A3 alternate function = TIM3_CH1, port D2 alternate function
TIM2_CH3.
AFR0: Alternate function remapping option 0
0: Port D3 alternate function = TIM2_CH2
1: Port D3 alternate function = ADC_ETR

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Table 17. Option byte description (continued)

Option byte no. Description

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
OPT3
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on Halt
0: No reset generated on Halt if WWDG active
1: Reset generated on Halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto-wakeup unit/clock
0: LSI clock source selected for AWU
OPT4 1: HSE clock with prescaler selected as clock source for AWU
PRSC[1:0]: AWU clock prescaler
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
OPT5 This configures the stabilization time to 0.5, 8, 128, and 2048 HSE cycles
with corresponding option byte values of 0xE1, 0xD2, 0xB4, and 0x00.
TMU[3:0]: Enable temporary memory unprotection
OPT6 0101: TMU disabled (permanent ROP).
Any other value: TMU enabled.
WAIT STATE: Wait state configuration
This option configures the number of wait states inserted when reading
OPT7 from the Flash/data EEPROM memory.
0: No wait state
1: One wait state
TMU_KEY 1 [7:0]: Temporary unprotection key 0
OPT8
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 2 [7:0]: Temporary unprotection key 1
OPT9
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 3 [7:0]: Temporary unprotection key 2
OPT10
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 4 [7:0]: Temporary unprotection key 3
OPT11
Temporary unprotection key: Must be different from 0x00 or 0xFF

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Table 17. Option byte description (continued)

Option byte no. Description

TMU_KEY 5 [7:0]: Temporary unprotection key 4

OPT12
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 6 [7:0]: Temporary unprotection key 5
OPT13
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 7 [7:0]: Temporary unprotection key 6
OPT14
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 8 [7:0]: Temporary unprotection key 7
OPT15
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_MAXATT [7:0]: TMU access failure counter
TMU_MAXATT can be initialized with the desired value only if TMU is
disabled (TMU[3:0]=0101 in OPT6 option byte).
OPT16 When TMU is enabled, any attempt to temporary remove the readout
protection by using wrong key values increments the counter.
When the option byte value reaches 0x08, the Flash memory and data
EEPROM are erased.
BL[7:0]: Bootloader enable
If this option byte is set to 0x55 (complementary value 0xAA) the
OPT17
bootloader program is activated also in case of a programmed code
memory (for more details, see the bootloader user manual, UM0560).

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10 Electrical characteristics

10.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

10.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = -40 °C, TA = 25 °C, and
TA = TAmax (given by the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production.

10.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5.0 V. They are
given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range.

10.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

10.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

Figure 9. Pin loading conditions

STM8A PIN

50 pF

MSv37796V1

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10.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 10. Pin input voltage

STM8A PIN

VIN

MSv37797V1

10.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,
Table 19: Current characteristics and Table 20: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only, and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect the device’s reliability. The device’s mission profile (application
conditions) is compliant with the JEDEC JESD47 qualification standard, extended mission
profiles are available on demand.

Table 18. Voltage characteristics

Symbol Ratings Min Max Unit

VDDx - VSS Supply voltage (including VDDA and VDDIO)(1) -0.3 6.5
Input voltage on true open drain pins (PE1, PE2)(2) VSS - 0.3 6.5 V
VIN
(2)
Input voltage on any other pin VSS - 0.3 VDD + 0.3
|VDDx - VDD| Variations between different power pins - 50
mV
|VSSx - VSS| Variations between all the different ground pins - 50
see Absolute maximum ratings
VESD Electrostatic discharge voltage (electrical sensitivity) on
page 88
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected

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Table 19. Current characteristics

Symbol Ratings Max. Unit

IVDDIO Total current into VDDIO power lines (source)(1)(2)(3) 100

(1)(2)(3)
IVSSIO Total current out of VSS IO ground lines (sink) 100
Output current sunk by any I/O and control pin 20
IIO mA
Output current source by any I/Os and control pin -20
IINJ(PIN)(4) Injected current on any pin ±10
IINJ(TOT) Sum of injected currents 50
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external supply.
2. The total limit applies to the sum of operation and injected currents.
3. VDDIO includes the sum of the positive injection currents. VSSIO includes the sum of the negative injection
currents.
4. This condition is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the
injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN >
VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive
injection current allowed and the corresponding VIN maximum must always be respected.

Table 20. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to 150

°C
TJ Maximum junction temperature 160

Table 21. Operating lifetime(1)

Symbol Ratings Value Unit

−40 to 125 °C Grade 1

OLF Conforming to AEC-Q100 rev G
−40 to 150 °C Grade 0
1. For detailed mission profile analysis, please contact the nearest ST Sales Office.

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10.3 Operating conditions

Table 22. General operating conditions
Symbol Parameter Conditions Min Max Unit

1 wait state
16 24
TA = -40 °C to 150 °C
fCPU Internal CPU clock frequency MHz
0 wait state
0 16
TA = -40 °C to 150 °C
VDD/VDDIO Standard operating voltage - 3.0 5.5 V
CEXT: capacitance of external
- 470 3300 nF
capacitor
VCAP(1)
ESR of external capacitor - 0.3 Ω
at 1 MHz(2)
ESL of external capacitor - 15 nH
Suffix A 85
TA Ambient temperature Suffix C - 40 125
Suffix D 150
°C
Suffix A 90
TJ Junction temperature range Suffix C - 40 130
Suffix D 155
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.
2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.

Figure 11. fCPUmax versus VDD

fCPU [MHz]

24
Functionality guaranteed
Functionality @TA -40 to 150 °C at 1 waitstate
not guaranteed 16
in this area

12
Functionality guaranteed
@TA -40 to 150 °C at 0 waitstate
8
4
0
3.0 4.0 5.0 5.5

Supply voltage [V]

MSv44121V1

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Table 23. Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Typ Max Unit

VDD rise time rate - 2(1) -

8
tVDD µs/V
(1)
VDD fall time rate - 2 -

8
Reset release delay VDD rising - 1 1.7 ms
tTEMP
Reset generation delay VDD falling - 3 - µs
Power-on reset
VIT+ - 2.65 2.8 2.95
threshold(2) (3)
V
Brown-out reset
VIT- - 2.58 2.73 2.88
threshold
Brown-out reset
VHYS(BOR) - - 70(1) - mV
hysteresis
1. Guaranteed by design, not tested in production.
2. If VDD is below 3 V, the code execution is guaranteed above the VIT- and VIT+ thresholds. RAM content is
kept. The EEPROM programming sequence must not be initiated.
3. There is inrush current into VDD present after device power on to charge CEXT capacitor. This inrush
energy depends from CEXT capacitor value. For example, a CEXT of 1 μF requires Q=1 μF x 1.8 V =
1.8 μC.

10.3.1 VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in Table 22. Care should be taken to limit the series inductance
to less than 15 nH.

Figure 12. External capacitor CEXT

C ESL

ESR

RLeak
MSv36488V1

1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.

10.3.2 Supply current characteristics

The current consumption is measured as described in Figure 9 on page 59 and Figure 10
on page 60.
If not explicitly stated, general conditions of temperature and voltage apply.

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Table 24. Total current consumption in Run, Wait and Slow mode. General conditions
for VDD apply, TA = −40 °C to 150 °C
Symbol Parameter Conditions Typ Max Unit
(2)
fCPU = 24 MHz 1 ws 8.8 16.9
All peripherals
clocked, code fCPU = 16 MHz 7.5 14.1
(1) Supply current in executed from Flash
IDD(RUN) fCPU = 8 MHz 4.1 7.5(2)
Run mode program memory,
HSE external clock fCPU = 4 MHz 2.5 4.2(2)
(without resonator)
fCPU = 2 MHz 1.6 2.6
fCPU = 24 MHz 4.5 6.1(2)
All peripherals
fCPU = 16 MHz 3.8 5.1
clocked, code
(1) Supply current in
IDD(RUN) executed from RAM, fCPU = 8 MHz 2.3 3.1(2)
Run mode
HSE external clock
fCPU = 4 MHz 1.5 2.1(2)
(without resonator)
mA
fCPU = 2 MHz 1.1 1.6
fCPU = 24 MHz 2.5 3.2(2)
fCPU = 16 MHz 1.75 2.6
CPU stopped, all
(1) Supply current in
IDD(WFI) peripherals off, HSE fCPU = 8 MHz 1.25 2.0(2)
Wait mode
external clock
fCPU = 4 MHz 1.0 1.7(2)
fCPU = 2 MHz 0.90 1.6

fCPU scaled down, External clock 16 MHz

1.60 2.05
Supply current in all peripherals off, fCPU = 125 kHz
IDD(SLOW)(1)
Slow mode code executed from LSI internal RC
RAM 1.60 1.90(2)
fCPU = 128 kHz
1. The current due to I/O utilization is not taken into account in these values.
2. Guaranteed by design, not tested in production.

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Table 25. Total current consumption in Halt and Active-halt modes. General conditions for VDD
applied. TA = −40 °C to 55 °C unless otherwise stated
Conditions

Main
Symbol Parameter Typ Max Unit
voltage Flash Clock source and
regulator mode(2) temperature condition
(MVR)(1)

Clocks stopped 105 135(3)

Supply current in Power-
IDD(H) Off Clocks stopped,
Halt mode down 105 125
TA = 25 °C

Supply current in External clock 16 MHz

Power- 870 1000(3)
Active-halt mode On fMASTER = 125 kHz µA
down
with regulator on LSI clock 128 kHz 250 330(3)
IDD(AH)
Supply current in LSI clock 128 kHz 125 142(3)
Power-
Active-halt mode Off LSI clock 128 kHz,
down 125 130
with regulator off TA = 25 °C
Wakeup time from
Active-halt mode On 10 30(3)
with regulator on Operating
tWU(AH) TA =−40 to 150 °C µs
Wakeup time from mode
Active-halt mode Off 50 80(3)
with regulator off
1. Configured by the REGAH bit in the CLK_ICKR register.
2. Configured by the AHALT bit in the FLASH_CR1 register.
3. Guaranteed by characterization results, not tested in production.

Current consumption for on-chip peripherals

Table 26. Oscillator current consumption

Symbol Parameter Conditions Typ Max(1) Unit

Quartz or fOSC = 24 MHz 1 2.0(3)

ceramic
HSE oscillator current fOSC = 16 MHz 0.6 -
IDD(OSC) resonator,
consumption(2)
CL = 33 pF
fOSC = 8 MHz 0.57 -
VDD = 5 V
mA
Quartz or fOSC = 24 MHz 0.5 1.0(3)
ceramic
HSE oscillator current fOSC = 16 MHz 0.25 -
IDD(OSC) resonator,
consumption(2)
CL = 33 pF
fOSC = 8 MHz 0.18 -
VDD = 3.3 V
1. During startup, the oscillator current consumption may reach 6 mA.
2. The supply current of the oscillator can be further optimized by selecting a high quality resonator with small Rm value. Refer
to crystal manufacturer for more details
3. Informative data.

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Table 27. Programming current consumption

Symbol Parameter Conditions Typ Max Unit

VDD = 5 V, -40 °C to 150 °C, erasing

IDD(PROG) Programming current and programming data or Flash 1.0 1.7 mA
program memory

Table 28. Typical peripheral current consumption VDD = 5.0 V(1)

Typ. Typ. Typ.
Symbol Parameter Unit
fmaster = 2 MHz fmaster = 16 MHz fmaster =24 MHz
IDD(TIM1) TIM1 supply current(2) 0.03 0.23 0.34
(2)
IDD(TIM2) TIM2 supply current 0.02 0.12 0.19
IDD(TIM3) TIM3 supply current(2) 0.01 0.1 0.16
IDD(TIM4) TIM4 supply current(2) 0.004 0.03 0.05
IDD(USART) USART supply current(2) 0.03 0.09 0.15
IDD(LINUART) LINUART supply current(2) 0.03 0.11 0.18
IDD(SPI) SPI supply current(2) 0.01 0.04 0.07 mA

IDD(I2C) I2C supply current(2) 0.02 0.06 0.91

IDD(AWU) AWU supply current(2) 0.003 0.02 0.05
IDD(TOT_DIG) All digital peripherals on 0.22 1 2.4
ADC supply current when
IDD(ADC) 0.93 0.95 0.96
converting(3)
1. Typical values not tested in production. Since the peripherals are powered by an internally regulated, constant digital
supply voltage, the values are similar in the full supply voltage range.
2. Data based on a differential IDD measurement between no peripheral clocked and a single active peripheral. This
measurement does not include the pad toggling consumption.
3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.

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Current consumption curves

Figure 13 to Figure 18 show typical current consumption measured with code executing in
RAM.

Figure 13. Typ. IDD(RUN)HSE vs. VDD Figure 14. Typ. IDD(RUN)HSE vs. fCPU
@fCPU = 16 MHz, peripherals = on @ VDD = 5.0 V, peripherals = on
10 10
9
25°C 25°C
9
IDD(RUN)HSE [mA]

85°C 85°C

IDD(RUN)HSE [mA]
8 8
7 125°C 7 125°C
6 6
5 5
4 4
3 3
2 2
1 1
0 0
2.5 3 3.5 4 4.5 5 5.5 6 0 5 10 15 20 25 30

VDD [V] fcpu [MHz]

Figure 15. Typ. IDD(RUN)HSI vs. VDD Figure 16. Typ. IDD(WFI)HSE vs. VDD
@ fCPU = 16 MHz, peripherals = off @ fCPU = 16 MHz, peripherals = on

4 6
IDD(WFI)HSE [mA]
IDD(RUN)HSI [mA]

5
3 4
2 3
25°C 25°C
2
1 85°C 85°C
1 125°C
125°C
0 0
2.5 3.5 4.5 5.5 6.5 2.5 3.5 4.5 5.5 6.5
VDD [V] VDD [V]

Figure 17. Typ. IDD(WFI)HSE vs. fCPU Figure 18. Typ. IDD(WFI)HSI vs. VDD
@ VDD = 5.0 V, peripherals = on @ fCPU = 16 MHz, peripherals = off

6 2.5

5
IDD(WFI)HSE [mA]

2
IDD(WFI)HSI [mA]

4
1.5
3

1
2 25°C 25°C
85°C 0.5 85°C
1
125°C 125°C
0 0
0 5 10 15 20 25 30 2.5 3 3.5 4 4.5 5 5.5 6

fcpu [MHz] VDD [V]

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10.3.3 External clock sources and timing characteristics

HSE external clock
An HSE clock can be generated by feeding an external clock signal of up to 24 MHz to the
OSCIN pin.
Clock characteristics are subject to general operating conditions for VDD and TA.

Table 29. HSE external clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fHSE_ext TA = -40 °C to 150 °C 0(1) - 24 MHz
frequency
VHSEdHL Comparator hysteresis - 0.1 x VDD - -
OSCIN high-level input pin
VHSEH - 0.7 x VDD - VDD
voltage V
OSCIN low-level input pin
VHSEL - VSS - 0.3 x VDD
voltage
ILEAK_HSE OSCIN input leakage current VSS < VIN < VDD -1 - +1 µA
1. If CSS is used, the external clock must have a frequency above 500 kHz.

Figure 19. HSE external clock source

V
HSEH

V HSEL

fHSE
External clock
source
OSCIN
STM8

MS36489V1

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 24 MHz.
All the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

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Table 30. HSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

RF Feedback resistor - - 220 - kΩ

(1)
CL1/CL2 Recommended load capacitance - - - 20 pF
gm Oscillator trans conductance - 5 - - mA/V
VDD is
tSU(HSE)(2) Startup time - 2.8 - ms
stabilized
1. The oscillator needs two load capacitors, CL1 and CL2, to act as load for the crystal. The total load capacitance (CLoad) is
(CL1 * CL2)/(CL1 + CL2). If CL1 = CL2, Cload = CL1/2. Some oscillators have built-in load capacitors, CL1 and CL2.
2. This value is the startup time, measured from the moment it is enabled (by software) until a stabilized 24 MHz oscillation is
reached. It can vary with the crystal type that is used.

Figure 20. HSE oscillator circuit diagram

Rm
fHSE to core
CO RF
Lm

CL1
Cm OSCIN gm
Resonator

Current control
Resonator

OSCOUT
CL2
STM8

MSv37799V1

HSE oscillator critical gm formula

The crystal characteristics have to be checked with the following formula:

Equation 1

g m » g mcrit

where gmcrit can be calculated with the crystal parameters as follows:

Equation 2

f 2 2
g mcrit = ( 2 × Π × HSE ) × R m ( 2Co + C )

Rm: Notional resistance (see crystal specification)

Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1 = CL2 = C: Grounded external capacitance

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10.3.4 Internal clock sources and timing characteristics

Subject to general operating conditions for VDD and TA.

High-speed internal RC oscillator (HSI)

Table 31. HSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency - - 16 - MHz

Trimmed by the application
HSI oscillator user
for any VDD and TA -1 - 1
trimming accuracy
ACCHS conditions %
HSI oscillator accuracy VDD = 3.0 V ≤ VDD ≤ 5.5 V,
-5 - 5
(factory calibrated) -40 °C ≤ TA ≤ 150 °C
tsu(HSI) HSI oscillator wakeup time - - - 2(1) µs
1. Guaranteed by characterization results, not tested in production.

Figure 21. Typical HSI frequency vs VDD

3%
-40°C
2% 25°C
HSI frequency variation [%]

85°C
1%
125°C
0%

-1%

-2%

-3%
2.5 3 3.5 4 4.5 5 5.5 6
VDD [V]

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Low-speed internal RC oscillator (LSI)

Subject to general operating conditions for VDD and TA.

Table 32. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fLSI Frequency - 112 128 144 kHz

tsu(LSI) LSI oscillator wakeup time - - - 7(1) µs
1. Guaranteed by characterization results, not tested in production.

Figure 22. Typical LSI frequency vs VDD

3%

2%
LSI frequency variation [%]

1% 25°C

0%

-1%

-2%

-3%
2.5 3 3.5 4 4.5 5 5.5 6
VDD [V]

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10.3.5 Memory characteristics

Flash program memory/data EEPROM memory
General conditions: TA = -40 °C to 150 °C.

Table 33. Flash program memory/data EEPROM memory

Symbol Parameter Conditions Min(1) Typ Max Unit

fCPU is 16 to 24 MHz
Operating voltage with 1 ws
VDD 3.0 - 5.5
(all modes, execution/write/erase) fCPU is 0 to 16 MHz
with 0 ws
V
fCPU is 16 to 24 MHz
with 1 ws
VDD Operating voltage (code execution) 2.6 - 5.5
fCPU is 0 to 16 MHz
with 0 ws
Standard programming time (including
erase) for byte/word/block - - 6 6.6
tprog (1 byte/4 bytes/128 bytes)
ms
Fast programming time for 1 block
- - 3 3.3
(128 bytes)
terase Erase time for 1 block (128 bytes) - - 3 3.3
1. Guaranteed by characterization results, not tested in production.

Table 34. Flash program memory

Symbol Parameter Condition Min Max Unit

TWE Temperature for writing and erasing - -40 150 °C

Flash program memory endurance
NWE TA = 25 °C 1000 - cycles
(erase/write cycles)(1)
TA = 25 °C 40 -
tRET Data retention time years
TA = 55 °C 20 -
1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a
write/erase operation addresses a single byte.

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Table 35. Data memory

Symbol Parameter Condition Min Max Unit

TWE Temperature for writing and erasing - -40 150 °C

Data memory endurance(1) TA = 25 °C 300 k -

NWE cycles
(erase/write cycles) TA = -40°C to 125 °C 100 k (2)
-
TA = 25 °C 40(2)(3) -
tRET Data retention time years
(2)(3)
TA = 55 °C 20 -
1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a
write/erase operation addresses a single byte.
2. More information on the relationship between data retention time and number of write/erase cycles is
available in a separate technical document.
3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.

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10.3.6 I/O port pin characteristics

General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or
an external pull-up or pull-down resistor.

Table 36. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL Low-level input voltage -0.3 V 0.3 x VDD

VIH High-level input voltage 0.7 x VDD VDD + 0.3 V
-
0.1 x
Vhys Hysteresis(1) - -
VDD
V
Standard I/0, VDD = 5 V,
VDD - 0.5 V - -
I = 3 mA
VOH High-level output voltage
Standard I/0, VDD = 3 V,
VDD - 0.4 V - -
I = 1.5 mA
High sink and true open
drain I/0, VDD = 5 V - - 0.5
I = 8 mA
VOL Low-level output voltage Standard I/0, VDD = 5 V V
- - 0.6
I = 3 mA
Standard I/0, VDD = 3 V
- - 0.4
I = 1.5 mA
Rpu Pull-up resistor VDD = 5 V, VIN = VSS 35 50 65 kΩ
Fast I/Os
- - 35(2)
Load = 50 pF
Standard and high sink I/Os
- - 125(2)
Rise and fall time Load = 50 pF
tR, tF ns
(10% - 90%) Fast I/Os
- - 20(2)
Load = 20 pF
Standard and high sink I/Os
- - 50(2)
Load = 20 pF
Digital input pad leakage
Ilkg VSS ≤ VIN ≤ VDD - - ±1 µA
current
VSS ≤ VIN ≤ VDD
- - ±250
Analog input pad leakage -40 °C < TA < 125 °C
Ilkg ana nA
current VSS ≤ VIN ≤ VDD
- - ±500
-40 °C < TA < 150 °C
Leakage current in
Ilkg(inj) Injection current ±4 mA - - ±1(3) µA
adjacent I/O(3)
Total current on either
IDDIO Including injection currents - - 60 mA
VDDIO or VSSIO
1. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not tested in
production.

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2. Guaranteed by design.
3. Guaranteed by characterization results, not tested in production.

Figure 23. Typical VIL and VIH vs VDD @ four temperatures

6
-40°C
5 25°C
85°C
4 125°C
VIL / V IH [V]

0
2.5 3 3.5 4 4.5 5 5.5 6
VDD [V]

Figure 24. Typical pull-up resistance RPU vs VDD @ four temperatures

60

55
Pull-Up resistance [k ohm]

50

45

40 -40°C
25°C
35 85°C
125°C
30
2.5 3 3.5 4 4.5 5 5.5 6
VDD [V]

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Figure 25. Typical pull-up current Ipu vs VDD @ four temperatures(1)

140

120

100

Pull-Up current [µA]

80
-40°C
60
25°C
40 85°C

20
125°C

0
0 1 2 3 4 5 6
VDD [V]

1. The pull-up is a pure resistor (slope goes through 0).

Typical output level curves

Figure 26 to Figure 35 show typical output level curves measured with output on a single
pin.

Figure 26. Typ. VOL @ VDD = 3.3 V (standard Figure 27. Typ. VOL @ VDD = 5.0 V (standard
ports) ports)
-40°C -40°C
1.5 1.5
25°C 25°C
1.25 85°C 1.25 85°C
125°C 125°C
1 1
VOL [V]

VOL [V]

0.75 0.75

0.5 0.5

0.25 0.25

0 0
0 1 2 3 4 5 6 7 0 2 4 6 8 10 12
IOL [mA] IOL [mA]

Figure 28. Typ. VOL @ VDD = 3.3 V (true open Figure 29. Typ. VOL @ VDD = 5.0 V (true open
drain ports) drain ports)
-40°C -40°C
2 2
25°C 25°C
1.75 1.75
85°C 85°C
1.5 125°C 1.5 125°C
1.25 1.25
VOL [V]

VOL [V]

1 1

0.75 0.75

0.5 0.5

0.25 0.25

0 0
0 2 4 6 8 10 12 14 0 5 10 15 20 25
IOL [mA] IOL [mA]

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Figure 30. Typ. VOL @ VDD = 3.3 V (high sink Figure 31. Typ. VOL @ VDD = 5.0 V (high sink
ports) ports)
-40°C -40°C
1.5 1.5
25°C 25°C
1.25 85°C 1.25 85°C
125°C 125°C
1 1
VOL [V]

VOL [V]
0.75 0.75

0.5 0.5

0.25 0.25

0 0
0 2 4 6 8 10 12 14 0 5 10 15 20 25
IOL [mA] IOL [mA]

Figure 32. Typ. VDD - VOH @ VDD = 3.3 V Figure 33. Typ. VDD - VOH @ VDD = 5.0 V
(standard ports) (standard ports)
-40°C -40°C
2 2
25°C 25°C
1.75 1.75
85°C 85°C
1.5 125°C 1.5 125°C
1.25 1.25
VDD - V OH [V]

VDD - V OH [V]

1 1

0.75 0.75

0.5 0.5

0.25 0.25

0 0
0 1 2 3 4 5 6 7 0 2 4 6 8 10 12
IOH [mA] IOH [mA]

Figure 34. Typ. VDD - VOH @ VDD = 3.3 V (high Figure 35. Typ. VDD - VOH @ VDD = 5.0 V (high
sink ports) sink ports)
-40°C -40°C
2 2
25°C 25°C
1.75 1.75
85°C 85°C
1.5 125°C 1.5 125°C
1.25 1.25
VDD - V OH [V]

VDD - V OH [V]

1 1

0.75 0.75

0.5 0.5

0.25 0.25

0 0
0 2 4 6 8 10 12 14 0 5 10 15 20 25
IOH [mA] IOH [mA]

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10.3.7 Reset pin characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified.

Table 37. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) NRST low-level input voltage(1) - VSS - 0.3 x VDD

(1)
VIH(NRST) NRST high-level input voltage - 0.7 x VDD - VDD V
(1)
VOL(NRST) NRST low-level output voltage IOL = 3 mA - - 0.6
RPU(NRST) NRST pull-up resistor - 30 40 60 kΩ
tIFP NRST input filtered pulse(1) - 85 - 315
NRST Input not filtered pulse ns
tINFP(NRST) - 500 - -
duration(2)
1. Guaranteed by characterization results, not tested in production.
2. Guaranteed by design, not tested in production.

Figure 36. Typical NRST VIL and VIH vs VDD @ four temperatures

-40°C
6
25°C

5 85°C
125°C
4
VIL / V IH [V]

0
2.5 3 3.5 4 4.5 5 5.5 6
VDD [V]

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Figure 37. Typical NRST pull-up resistance RPU vs VDD

60 -40°C
25°C

NRST Pull-Up resistance [k ohm]

55 85°C
125°C
50

45

40

35

30
2.5 3 3.5 4 4.5 5 5.5 6
VDD [V]

Figure 38. Typical NRST pull-up current Ipu vs VDD

140

120
NRST Pull-Up current [µA]

100

80

60 -40°C
25°C
40
85°C
20 125°C

0
0 1 2 3 4 5 6
VDD [V]

The reset network shown in Figure 39 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 37:
NRST pin characteristics), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external
circuitry, attention must be taken to the charge/discharge time of the external capacitor to
fulfill the external devices reset timing conditions. Minimum recommended capacity is 10 nF.

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Figure 39. Recommended reset pin protection

VDD STM8A

RPU
External
reset NRST Filter Internal reset
circuit
0.1 μF
(Optional)

MSv38341V1

10.3.8 TIM 1, 2, 3, and 4 electrical specifications

Subject to general operating conditions for VDD, fMASTER and TA.

Table 38. TIM 1, 2, 3, and 4 electrical specifications

Symbol Parameter Conditions Min Typ Max Unit

fEXT Timer external clock frequency(1) - - - 24 MHz

1. Not tested in production.

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10.3.9 SPI interface

Unless otherwise specified, the parameters given in Table 39 are derived from tests
performed under ambient temperature, fMASTER frequency, and VDD supply voltage
conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).

Table 39. SPI characteristics

Symbol Parameter Conditions Min Max Unit

Master mode 0 10
fSCK
SPI clock frequency VDD < 4.5 V 0 6(1) MHz
1/tc(SCK) Slave mode
VDD = 4.5 V to 5.5 V 0 8(1)
tr(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF - 25(2)
tf(SCK)
tsu(NSS)(3) NSS setup time Slave mode 4 * tMASTER -
(3)
th(NSS) NSS hold time Slave mode 70 -
tw(SCKH)(3) tw(SCKH)(3)
SCK high and low time Master mode tSCK/2 - 15 tSCK/2 + 15
tw(SCKL)(3) tw(SCKL)(3)

tsu(MI)(3) Master mode 5 -

Data input setup time
tsu(SI)(3) Slave mode 5 -

th(MI)(3) Master mode 7 -

Data input hold time ns
th(SI)(3) Slave mode 10 -
ta(SO)(3)(4) Data output access time Slave mode - 3* tMASTER
tdis(SO)(3)(5) Data output disable time Slave mode 25

Slave mode VDD < 4.5 V - 75

tv(SO)(3) Data output valid time
(after enable edge) V = 4.5 V to 5.5 V - 53
DD

tv(MO)(3) Data output valid time Master mode (after enable edge) - 30
th(SO)(3) Slave mode (after enable edge) 31 -
Data output hold time
th(MO)(3) Master mode (after enable edge) 12 -
1. fSCK < fMASTER/2.
2. The pad has to be configured accordingly (fast mode).
3. Guaranteed by design or by characterization results, not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

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Figure 40. SPI timing diagram in slave mode and with CPHA = 0

1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.

Figure 41. SPI timing diagram in slave mode and with CPHA = 1

NSS input

tSU(NSS) tc(SCK) th(NSS)

SCK input

CPHA=1
CPOL=0 tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1

tr(SCK)
tv(SO) th(SO) tdis(SO)
ta(SO) tf(SCK)
MISO
MSB OUT BIT6 OUT LSB OUT
OUTPUT
tsu(SI) th(SI)
MOSI
INPUT MSB IN BIT 1 IN LSB IN

ai14135b

1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.

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Figure 42. SPI timing diagram - master mode

High

NSS input

tc(SCK)
SCK Output

CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1

tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN

th(MI)
MOSI
MSB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136c

1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.

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10.3.10 I2C interface characteristics

Table 40. I2C characteristics

Standard mode I2C Fast mode I2C(1)
Symbol Parameter Unit
Min(2) Max(2) Min(2) Max(2)

tw(SCLL) SCL clock low time 4.7 - 1.3 -

µs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
th(SDA) SDA data hold time 0(3) - 0(4) 900(3)
tr(SDA) SDA and SCL rise time ns
- 1000 - 300
tr(SCL) (VDD 3 V to 5.5 V)
tf(SDA) SDA and SCL fall time
- 300 - 300
tf(SCL) (VDD 3 V to 5.5 V)
th(STA) START condition hold time 4.0 - 0.6 -
µs
tsu(STA) Repeated START condition setup time 4.7 - 0.6 -
tsu(STO) STOP condition setup time 4.0 - 0.6 - µs
STOP to START condition time
tw(STO:STA) 4.7 - 1.3 - µs
(bus free)
Cb Capacitive load for each bus line - 400 - 400 pF
1. fMASTER, must be at least 8 MHz to achieve max fast I 2C speed (400 kHz)
2. Data based on standard I2C protocol requirement, not tested in production
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL

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10.3.11 10-bit ADC characteristics

Subject to general operating conditions for VDDA, fMASTER and TA unless otherwise
specified.

Table 41. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

fADC ADC clock frequency - 111 kHz - 4 MHz kHz/MHz

VDDA Analog supply - 3 - 5.5

VREF+ Positive reference voltage - 2.75 - VDDA

VREF- Negative reference voltage - VSSA - 0.5

V
- VSSA - VDDA

VAIN Conversion voltage range(1) Devices with

external VREF+/ VREF- - VREF+
VREF- pins
Csamp Internal sample and hold capacitor - - - 3 pF

Sampling time fADC = 2 MHz - 1.5 -

tS(1)
(3 x 1/fADC) fADC = 4 MHz - 0.75 -
fADC = 2 MHz - 7 -
tSTAB Wakeup time from standby µs
fADC = 4 MHz - 3.5 -
Total conversion time including fADC = 2 MHz - 7 -
tCONV sampling time
(14 x 1/fADC) fADC = 4 MHz - 3.5 -

Rswitch Equivalent switch resistance - - - 30 kΩ

1. During the sample time, the sampling capacitance, Csamp (3 pF typ), can be charged/discharged by the
external source. The internal resistance of the analog source must allow the capacitance to reach its final
voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no
effect on the conversion result.

Figure 43. Typical application with ADC

VDD STM8A

VT
Rswitch
VAIN RAIN 0.6 V
AINx 10-bit A/D
Ts conversion
VT
CAIN IL Csamp
0.6 V

MSv38342V1

1. Legend: RAIN = external resistance, CAIN = capacitors, Csamp = internal sample and hold capacitor.

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Table 42. ADC accuracy for VDDA = 5 V

Symbol Parameter Conditions Typ Max(1) Unit

|ET| Total unadjusted error(2) 1.4 3(3)

|EO| Offset error(2) 0.8 3
(2)
|EG| Gain error fADC = 2 MHz 0.1 2
|ED| Differential linearity error(2) 0.9 1
(2)
|EL| Integral linearity error 0.7 1.5
LSB
(2) (4) 4(4)
|ET| Total unadjusted error 1.9
|EO| Offset error(2) 1.3(4) 4(4)
|EG| Gain error(2) fADC = 4 MHz 0.6(4) 3(4)
|ED| Differential linearity error(2) 1.5(4) 2(4)
|EL| Integral linearity error(2) 1.2(4) 1.5(4)
1. Guaranteed by characterization results, not tested in production.
2. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for
IINJ(PIN) and ΣIINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy.
3. TUE 2LSB can be reached on specific sales types on the whole temperature range.
4. Target values.

Figure 44. ADC accuracy characteristics

EG
1023
V –V
1022 DDA SSA
1LSB = -----------------------------------------
1021 IDEAL 1024
(2)
ET
7 (3)
(1)
6
5
EO EL
4
3 ED
2
1 1 LSBIDEAL

0 1 2 3 4 5 6 7 1021102210231024
VSSA VDDA

1. Example of an actual transfer curve

2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.
EO = Offset error: Deviation between the first actual transition and the first ideal one.
EG = Gain error: Deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: Maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: Maximum deviation between any actual transition and the end point correlation
line.

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10.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
• ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Table 43. EMS data

Symbol Parameter Conditions Level/class

VDD = 3.3 V, TA= 25 °C,

Voltage limits to be applied on any I/O pin
VFESD fMASTER = 16 MHz (HSI clock), 3/B
to induce a functional disturbance
Conforms to IEC 1000-4-2
Fast transient voltage burst limits to be VDD= 3.3 V, TA= 25 °C,
VEFTB applied through 100 pF on VDD and VSS fMASTER = 16 MHz (HSI clock), 4/A
pins to induce a functional disturbance Conforms to IEC 1000-4-4

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Electrical characteristics STM8AF6388

Electromagnetic interference (EMI)

Emission tests conform to the IEC 61967-2 standard for test software, board layout and pin
loading.

Table 44. EMI data

Conditions

Max fCPU(1)
Symbol Parameter Unit
General Monitored
conditions frequency band 8 16 24
MHz MHz MHz

VDD = 5 V, 0.1 MHz to 30 MHz 15 17 22

Peak level TA = 25 °C, 30 MHz to 130 MHz 18 22 16
SEMI LQFP80 package dBµV
conforming to IEC 130 MHz to 1 GHz -1 3 5
EMI level 61967-2 - 2 2.5 2.5
1. Guaranteed by characterization results, not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard. For more details, refer to the application
note AN1181.

Table 45. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic discharge voltage TA = 25 °C, conforming

VESD(HBM) 3A 4000
(human body model) to JESD22-A114
Electrostatic discharge voltage TA = 25 °C, conforming
VESD(CDM) 3 500 V
(charge device model) to JESD22-C101
Electrostatic discharge voltage TA = 25 °C, conforming
VESD(MM) B 200
(charge device model) to JESD22-A115
1. Guaranteed by characterization results, not tested in production

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Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
• A supply overvoltage (applied to each power supply pin) and
• A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.

Table 46. Electrical sensitivities

Symbol Parameter Conditions Class(1)

TA = 25 °C
TA = 85 °C
LU Static latch-up class A
TA = 125 °C
TA = 150 °C
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).

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11 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

11.1 LQFP80 package information

Figure 45. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline
SEATING
PLANE
C
A2
A

A1

c
0.25 mm
GAUGE PLANE

ccc C A1

D L k
D1 L1
D3

60 41

61 40
b

E1
E3

80 21

PIN 1 1 20
IDENTIFICATION
e
1S_ME

1. Drawing is not to scale.

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Table 47. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package

mechanical data(1)
millimeters inches
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.220 0.320 0.380 0.0087 0.0126 0.0150
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.350 - - 0.4862 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 - 12.350 - - 0.4862 -
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Figure 46. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package

recommended footprint

60 41

0.4
61 0.65 40

14.3
16.7

80 21

1.2
1 20
12.75

16.7

1S_FP

1. Dimensions are expressed in millimeters.

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Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.

Figure 47. LQFP80 marking example (package top view)

Product
identification (1) XXXXXX

XXXX

Date code
Standard ST logo
Y WW
Revision code
Pin 1 identifier

MS38333V1

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's quality department must be contacted to run a qualification activity prior to any decision to
use these engineering samples.

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11.2 LQFP64 package information

Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

SEATING PLANE
C

A2
A
0.25 mm
GAUGE PLANE

A1

c
ccc C

A1
D K
D1 L
D3 L1
48 33

32
49

E1
E3

E
64 17

PIN 1 1 16
IDENTIFICATION e
5W_ME_V3

1. Drawing is not to scale.

Table 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -

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Table 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data (continued)
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package

recommended footprint

48 33

0.3
49 0.5 32

12.7

10.3

10.3
64 17

1.2
1 16

7.8

12.7

ai14909c

1. Dimensions are expressed in millimeters.

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Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.

Figure 50. LQFP64 marking example (package top view)

Product
identification (1) XXXXXX

XXXX

Date code

Standard ST logo Y WW
Revision code

Pin 1 identifier

MS38334V1

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's quality department must be contacted to run a qualification activity prior to any decision to
use these engineering samples.

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11.3 LQFP48 package information

Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

SEATING
PLANE
C

A2
A

A1

c
0.25 mm
GAUGE PLANE
ccc C

D K

A1
L
D1 L1
D3
36 25

37 24

E1
E3

E
48 13
PIN 1
IDENTIFICATION 1 12

e 5B_ME_V2

1. Drawing is not to scale.

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Table 49. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

recommended footprint
0.50
1.20

0.30
36 25
37 24

0.20
7.30
9.70 5.80

7.30

48 13
1 12

1.20

5.80

9.70

ai14911d

1. Dimensions are expressed in millimeters.

Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.

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Figure 53. LQFP48 marking example (package top view)

Product
identification (1) XXXXXX

XXXX

Date code
Standard ST logo Y WW

Pin 1 identifier Revision code

MS38335V1

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's quality department must be contacted to run a qualification activity prior to any decision to
use these engineering samples.

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11.4 LQFP32 package information

Figure 54. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline

SEATING
PLANE
C

A2
A

c
A1

0.25 mm
GAUGE PLANE
ccc C

K
D
L

A1
D1
L1
D3

24 17

25 16
b

E1
E3

32 9

PIN 1
IDENTIFICATION 1 8

e 5V_ME_V2

1. Drawing is not to scale.

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Table 50. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package

mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.600 - - 0.2205 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.600 - - 0.2205 -
e - 0.800 - - 0.0315 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Figure 55. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package

recommended footprint
0.80

1.20

24 17
25 16 0.50

0.30

7.30

6.10

9.70
7.30

32 9
1 8

1.20

6.10

9.70
5V_FP_V2

1. Dimensions are expressed in millimeters.

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Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.

Figure 56. LQFP32 marking example (package top view)

Product
identification (1) XXXXXX

XXXX

Date code
Standard ST logo Y WW

Pin 1 identifier Revision code

MS38337V1

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's quality department must be contacted to run a qualification activity prior to any decision to
use these engineering samples.

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11.5 VFQFPN32 package information

Figure 57. VFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package outline
Seating plane

C
ddd C
A

A3 A1

D
e

9 16

8 17

E2 b E

24
1
L
32
Pin # 1 ID
R = 0.20 D2
L
Bottom view
42_ME_AMKOR_V1

1. Drawing is not to scale.

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Table 51. VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.800 0.900 1.000 0.0315 0.0354 0.0394

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.200 - - 0.0079 -
b 0.180 0.250 0.300 0.0071 0.0098 0.0118
D 4.850 5.000 5.150 0.1909 0.1969 0.2028
D2 3.500 3.600 3.700 0.1378 0.1417 0.1457
E 4.850 5.000 5.150 0.1909 0.1969 0.2028
E2 3.500 3.600 3.700 0.1378 0.1417 0.1457
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Figure 58. VFQFPN32 - 32-pin, 5 x 5 mm, 0.5 mm pitch very thin profile fine pitch quad
flat package recommended footprint

5.30

3.80

0.60

3.10 (Var A)
3.60 (Var B)

5.30 3.80
3.10 (Var A)
3.60 (Var B)

0.50
0.30

0.75

3.80
42_FP_AMKOR_V1

1. Dimensions are expressed in millimeters.

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Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.

Figure 59. VFQFPN32 marking example (package top view)

Product
identification (1) XXXXXX

Date code

Y WW
Standard ST logo
Revision code

Pin 1 identifier

MS38336V1

1. Parts marked as "ES","E” or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's quality department must be contacted to run a qualification activity prior to any decision to
use these engineering samples.

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11.6 Thermal characteristics

In case the maximum chip junction temperature (TJmax) specified in Table 22: General
operating conditions is exceeded, the functionality of the device cannot be guaranteed.
TJmax, in degrees Celsius, may be calculated using the following equation:
TJmax = TAmax + (PDmax x ΘJA)
where:
TAmax is the maximum ambient temperature in ° C
ΘJA is the package junction-to-ambient thermal resistance in ° C/W
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/Omax represents the maximum power dissipation on output pins

where:
PI/Omax = Σ (VOL * IOL) + Σ((VDD - VOH) * IOH)

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low- and high-level in the
application.

Table 52. Thermal characteristics(1)

Symbol Parameter Value Unit

Thermal resistance junction-ambient

38
LQFP 80 - 14 x 14 mm
Thermal resistance junction-ambient
46
LQFP 64 - 10 x 10 mm
Thermal resistance junction-ambient
ΘJA 57 °C/W
LQFP 48 - 7 x 7 mm
Thermal resistance junction-ambient
59
LQFP 32 - 7 x 7 mm
Thermal resistance junction-ambient
25
VFQFPN 32 - 5 x 5 mm
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.

11.6.1 Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.

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11.6.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see
Figure 60: STM8AF6388 ordering information scheme1 on page 111).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
– Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2)
– IDDmax = 8 mA
– VDD = 5 V
– maximum 20 I/Os used at the same time in output at low-level with IOL = 8 mA
– VOL = 0.4 V
PINTmax = 8 mA x 5 V = 400 mW

PIOmax = 20 x 8 mA x 0.4 V = 64 mW

This gives:
PINTmax = 400 mW and PIOmax 64 mW
PDmax = 400 mW + 64 mW

Thus:
PDmax = 464 mW.
Using the values obtained in Table 52: Thermal characteristics TJmax is calculated as
follows:
For LQFP64 46 °C/W

Tjmax = 82 °C + (46 °C/W x 464 mW) = 82 °C + 21 °C = 103 ° C

This is within the range of the suffix C version parts (-40 °C < Tj < 125 ° C).
Parts must be ordered at least with the temperature range suffix C.

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12 Ordering information

Figure 60. STM8AF6388 ordering information scheme1

Example: STM8A2 F 63 A A T D XXX3 Y

Product class
8-bit automotive microcontroller

Program memory type

F = Flash + EEPROM
P = FASTROM

Device family
63 = Silicon rev S, LIN only

Program memory size

6 = 32 Kbyte
8 = 64 Kbyte
A= 128 Kbyte

Pin count
6 = 32 pins
8 = 48 pins
9 = 64 pins
A = 80 pins

Package type
T = LQFP
U = VFQFPN

Temperature range
A = -40 to 85 °C
C = -40 to 125 °C
D = -40 to 150 °C

Packing
Y = Tray
U = Tube
X = Tape and reel compliant with EIA 481-C

1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the nearest ST Sales Office.
2. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening
according to AEC Q001 and Q002 or equivalent.
3. Customer specific FASTROM code or custom device configuration. This field shows ‘SSS’ if the device
contains a super set silicon, usually equipped with bigger memory and more I/Os. This silicon is supposed
to be replaced later by the target silicon.

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13 STM8 development tools

Development tools for the STM8A microcontrollers include the

• STice emulation system offering tracing and code profiling
• STVD high-level language debugger including assembler and visual development
environment - seamless integration of third party C compilers
• STVP Flash programming software
In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.

13.1 Emulation and in-circuit debugging tools

The STM8 tool line includes the STice emulation system offering a complete range of
emulation and in-circuit debugging features on a platform that is designed for versatility and
cost-effectiveness. In addition, STM8A application development is supported by a low-cost
in-circuit debugger/programmer.
The STice is the fourth generation of full-featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including tracing, profiling and code coverage
analysis to help detect execution bottlenecks and dead code.
In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers
via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of
an application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows users to
order exactly what they need to meet their development requirements and to adapt their
emulation system to support existing and future ST microcontrollers.

13.1.1 STice key features

• Program and data trace recording up to 128 K records
• Advanced breakpoints with up to 4 levels of conditions
• Data breakpoints
• Real-time read/write of all device resources during emulation
• Occurrence and time profiling and code coverage analysis (new features)
• In-circuit debugging/programming via SWIM protocol
• 8-bit probe analyzer
• 1 input and 2 output triggers
• USB 2.0 high-speed interface to host PC
• Power supply follower managing application voltages between 1.62 to 5.5 V
• Modularity that allows users to specify the components they need to meet their
development requirements and adapt to future requirements
• Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.

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13.2 Software tools

STM8 development tools are supported by a complete, free software package from STMi-
croelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer
(STVP) software interface. STVD provides seamless integration of the Cosmic and Raiso-
nance C compilers for STM8.

13.2.1 STM8 toolset

The STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com. This package includes:

ST visual develop
Full-featured integrated development environment from STMicroelectronics, featuring:
• Seamless integration of C and ASM toolsets
• Full-featured debugger
• Project management
• Syntax highlighting editor
• Integrated programming interface
• Support of advanced emulation features for STice such as code profiling and coverage

ST visual programmer (STVP)

Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8A
microcontroller’s Flash memory. STVP also offers project mode for saving programming
configurations and automating programming sequences.

13.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of the
application directly from an easy-to-use graphical interface. Available toolchains include:

C compiler for STM8

All compilers are available in free version with a limited code size depending on the
compiler. For more information, refer to www.cosmic-software.com, www.raisonance.com,
and www.iar.com.

STM8 assembler linker

Free assembly toolchain included in the STM8 toolset, which allows users to assemble and
link their application source code.

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13.3 Programming tools

During the development cycle, STice provides in-circuit programming of the STM8A Flash
microcontroller on the application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming the STM8A.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.

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14 Revision history

Table 53. Document revision history

Date Revision Changes

24-Oct-2017 1 Initial release

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 STM8AF6388

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2017 STMicroelectronics – All rights reserved

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