ST7L34 ST7L35

ST7L38 ST7L39
8-bit MCU for automotive with single voltage Flash/ROM,
data EEPROM, ADC, timers, SPI, LINSCI™

Features
■ Memories
– 8 Kbytes program memory: Single voltage
extended Flash (XFlash) or ROM with
readout protection capability. In-application
SO20
300 mil QFN20

( s )
ct
programming and in-circuit programming
(IAP and ICP) for XFlash devices ■ 2 communication interfaces
– 384 bytes RAM
d u
– Master/slave LINSCI™ asynchronous
– 256 bytes data EEPROM (XFlash and
serial interface
r o
– SPI synchronous serial interface
ROM devices) with readout protection,
300 K write/erase cycles guaranteed ■ P
Interrupt management
e
– XFlash and EEPROM data retention
20 years at 55°C
l e t
– 10 interrupt vectors plus TRAP and reset
– 12 external interrupt lines (on 4 vectors)
■ Clock, reset and supply management ■
s o
A/D converter
– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for
O b – 7 input channels
– 10-bit resolution

)-
main supply and an auxiliary voltage
■ Instruction set
detector (AVD) with interrupt capability for

( s
implementing safe power-down procedures
t
– 8-bit data manipulation
– 63 basic instructions with illegal opcode

u c
– Clock sources: Internal 1% RC oscillator,
crystal/ceramic resonator or external clock detection

d
– Optional x8 PLL for 8 MHz internal clock
o
– 17 main addressing modes

P r
– 5 power saving modes: Halt, active halt,
auto wakeup from halt, wait and slow ■
– 8 x 8 unsigned multiply instructions
Development tools
■ I/O ports

e t e
– Up to 15 multifunctional bidirectional I/O
– Full hardware/software development
package
l
lines
o – DM (debug module)

■
b s– 7 high sink outputs
5 timers
O – Configurable watchdog timer
– Two 8-bit lite timers with prescaler, 1 real-
time base and 1 input capture
– Two 12-bit autoreload timers with 4 PWM
outputs, 1 input capture and 4 output
compare functions

November 2011 Doc ID 11928 Rev 8 1/234

www.st.com 1
 Contents ST7L34 ST7L35 ST7L38 ST7L39

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1 Parametric data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2 Debug module (DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

( s )
4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
u ct
4.1
d
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
o
4.2 r
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
P
4.3
e
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

e t
4.3.1
l
In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

o
4.4
4.3.2

b s
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5
- O
Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5.1
(s )
Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5.2
c t
Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.6 u
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
d
4.7
r o
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

e P
5
l t
Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
e
s o 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

O b 5.2
5.3
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.6 Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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 ST7L34 ST7L35 ST7L38 ST7L39 Contents

6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1 Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.4 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.4.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.4.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.4.3
s )
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
(
7.5 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
u ct
7.5.1
d
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

o
7.5.2
7.5.3
P r
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.5.4
t e
Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 44
e
7.5.5
o l
Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.6
b s
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.6.1
O
Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
-
7.6.2
7.6.3
(s )
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.6.4
c t
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

d u
8
r o
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.1
e P Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

l e t
8.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

s o 8.3 Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

O9
b Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.4 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.4.1 Halt mode recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.5 Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.6 Auto wakeup from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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Contents ST7L34 ST7L35 ST7L38 ST7L39

10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.4 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.6
( s )
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.7
u
Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ct
o d
11
r
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
P
11.1
e
Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

e t
11.1.1
11.1.2
o l
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.1.3
b s
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.1.4 O
Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
-
11.1.5
)
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

(s
11.1.6
t
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
c
11.2
u
Dual 12-bit autoreload timer 3 (AT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
d
11.2.1
r o Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

e P 11.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

let
11.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

s o 11.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Ob 11.3
11.2.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.3.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.4 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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11.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.4.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.4.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.4.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
11.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
11.4.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
11.5 LINSCI serial communication interface (LIN master/slave) . . . . . . . . . . 122
11.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
11.5.2 SCI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
11.5.3
)
LIN features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

( s
ct
11.5.4 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
11.5.5
u
SCI mode - functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
d
11.5.6
o
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
r
11.5.7
11.5.8
e P
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SCI mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
11.5.9
l e t
LIN mode - functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

s o
11.5.10 LIN mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.6 b
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
O
11.6.1
-
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

)
(s
11.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
11.6.3
c t
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
11.6.4
d u
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

r
11.6.5
o Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

e P 11.6.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

12
l e t
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
o
bs
12.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

O 12.1.1
12.1.2
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.2.1 Using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.2.2 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

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 Contents ST7L34 ST7L35 ST7L38 ST7L39

13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
13.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
13.2.2
s )
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
(
13.3
13.2.3

u ct
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

o d
13.3.1
13.3.2
P r
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 186
13.3.3
t e
Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 188
e
13.3.4 l
Internal RC oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
o
13.4 s
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
b
13.4.1
O
Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

-
13.5
13.4.2

(s )
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
13.5.1
c t
General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
u
od
13.5.2 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 194
13.6
P rMemory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

e te 13.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

o l 13.6.2
13.6.3
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
EEPROM data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

b s 13.7 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . 196

O 13.7.1
13.7.2
Functional electromagnetic susceptibility (EMS) . . . . . . . . . . . . . . . . . 196
Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
13.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 198
13.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
13.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
13.10 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 207

6/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Contents

13.10.1 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

13.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

14 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

14.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
14.2 Packaging for automatic handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
14.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

15 Device configuration and ordering information . . . . . . . . . . . . . . . . . 215

15.1
s )
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
(
15.2
ct
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
u
15.2.1
d
Flash option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

o
15.3
15.2.2

P r
ROM option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Device ordering information and transfer of customer code . . . . . . . . . . 219
15.4 t e
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
e
15.4.1
o l
Starter Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
15.4.2
b s
Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
15.4.3
O
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
-
15.4.4
)
Order codes for development and programming tools . . . . . . . . . . . . . 225

(s
16
c t
Important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
16.1
d u
Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 226
16.2 r o
LINSCI limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

e P 16.2.1 Header time-out does not prevent wake-up from mute mode . . . . . . . 226

l e t
17
s o Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

O b

Doc ID 11928 Rev 8 7/234

 List of tables ST7L34 ST7L35 ST7L38 ST7L39

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 2. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4. EECSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5. Data EEPROM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. CC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7. RCCR calibration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 9. RCCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 10.
Table 11. Effect of low power modes on system integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
( s )
Clock cycle delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 12.
Table 13.
Supply, reset and clock management interrupt control/wake-up capability . . . . . . . . . . . . 47

u ct
SICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 14.
d
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
o
Table 15.
Table 16.
P r
EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 17.
Table 18.
t e
EISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
LTCSR/ATCSR register status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
e
Table 19.
l
AWUCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
o
Table 20.
Table 21.
b s
AWUPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
AWUPR dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 22.
Table 23.
- O
AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DR value and output pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 24.
Table 25.
(s )
I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
I/O configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 26.
c t
Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 27.
Table 28.
d u
I/O interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Port configuration (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 29.
r o
Port configuration (external interrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 30.
Table 31.
e P
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 32.
Table 33.
l e t
WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

s o
Table 34. Effect of low power modes on AT3 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

O b
Table 35.
Table 36.
Table 37.
AT3 interrupt control/wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ATCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CNTR1H and CNTR1L register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 38. ATR1H and ATR1L register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 39. PWMCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 40. PWMxCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 41. BREAKCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 42. DCRxH and DCRxL register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 43. ATICRH and ATICRL register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 44. ATCSR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 45. ATR2H and ATR2L register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 46. DTGR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 47. Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 48. Effect of low power modes on lite timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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 ST7L34 ST7L35 ST7L38 ST7L39 List of tables

Table 49. Lite timer 2 interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 50. LTCSR2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 51. LTARR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 52. LTCNTR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 53. LTCSR1 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 54. LTICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 55. Lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 56. Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 57. SPI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 58. SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 59. SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 60. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 61. Character formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 62.
s
Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

( )
ct
Table 63. SCI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 64. SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 65.
u
SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
d
Table 66.
Table 67.
r o
SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SCIBRR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 68.
Table 69.
e P
SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SCIETPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 70.
e t
SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
l
Table 71.
Table 72.
s o
SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 73.
Table 74.
O b
SCICR3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
LPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 75.
Table 76.
) -
LIN mantissa rounded values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
LPFR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 77.
Table 78. t (s
LDIV fractions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

c
LHLR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 79.
Table 80. d u
LIN header mantissa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
LIN header fractions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 81.
r o
LINSCI1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 82.
Table 83.
e P
Effect of low power modes on the A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 84.
l e tADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

s o
Table 85.
Table 86.
ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
ADC clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

O b
Table 87.
Table 88.
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
CPU addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 89. CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 90. Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 91. Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 92. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 173
Table 93. Short instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 94. Relative mode instructions (direct and indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 95. Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 96. Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 97. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 98. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 99. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 100. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Doc ID 11928 Rev 8 9/234

 List of tables ST7L34 ST7L35 ST7L38 ST7L39

Table 101. Operating conditions (tested for TA = -40 to +125 °C) @ VDD = 4.5 to 5.5 V . . . . . . . . . . 183
Table 102. Operating conditions (tested for TA = -40 to +125 °C) @ VDD = 4.5 to 5.5 V . . . . . . . . . . 183
Table 103. Operating conditions (tested for TA = -40 to +125 °C) @ VDD = 3.0 to 3.6 V . . . . . . . . . . 184
Table 104. Operating conditions (tested for TA = -40 to +125 °C) @ VDD = 3.0 to 3.6 V . . . . . . . . . . 185
Table 105. Operating conditions with low voltage detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 106. Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 107. Internal RC oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 108. Supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 109. On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 110. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 111. Oscillator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 112. Typical ceramic resonator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 113. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 114. Characteristics of dual voltage HDFlash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

( s )
ct
Table 115. Characteristics of EEPROM data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 116. Electromagnetic test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 117.
u
EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
d
Table 118.
Table 119.
r o
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Latch up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 120.
Table 121.
e P
I/O general port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 122.
e t
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
l
Table 123.
Table 124.
s o
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 125.
Table 126.
O b
ADC accuracy with 4.5 V < VDD < 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
ADC accuracy with 3 V < VDD < 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 127.
Table 128.
) -
20-pin plastic small outline package, 300-mil width, mechanical data . . . . . . . . . . . . . . . 212
QFN 5x6: 20-terminal very thin fine pitch quad flat no-lead package . . . . . . . . . . . . . . . . 213
Table 129.
Table 130. t (s
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

c
Flash and ROM option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 131.
Table 132. d u
Option byte 0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Option byte 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 133.
r o
Option byte 0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 134.
Table 135.
e P
Option byte 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
ST7L3 development and programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 136.
l e t
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

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O b

10/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 List of figures

List of figures

Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 2. 20-pin SO package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. 20-pin QFN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. EEPROM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 8. Data EEPROM write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10.
Figure 11.
( s )
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12.
Figure 13.
u ct
PLL output frequency timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14.
d
ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
o
Figure 15.
Figure 16.
P r
Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 17.
Figure 18.
t e
Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low voltage detector vs. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
e
Figure 19.
l
Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
o
Figure 20.
Figure 21.
b s
Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 22.
Figure 23.
- O
Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 24.
Figure 25.
(s )
Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 26.
c t
Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 27.
Figure 28.
d u
Active halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Active halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 29.
r o
AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 30.
Figure 31.
e P
AWUF halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 32.
l
Figure 33. e t
I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

s o
Figure 34. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

O b
Figure 35.
Figure 36.
Figure 37.
Single timer mode (ENCNTR2 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Dual timer mode (ENCNTR2 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PWM polarity inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 38. PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 39. PWM signal from 0% to 100%duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 40. Dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 41. Block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 42. Block diagram of output compare mode (single timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 43. Block diagram of input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 44. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 45. Long range input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 46. Long range input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 47. Lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 48. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Doc ID 11928 Rev 8 11/234

 List of figures ST7L34 ST7L35 ST7L38 ST7L39

Figure 49. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 50. Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 51. Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 52. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 53. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 54. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 116
Figure 55. Single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 56. SCI block diagram (in conventional baud rate generator mode). . . . . . . . . . . . . . . . . . . . 125
Figure 57. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 58. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 59. LIN characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 60. SCI block diagram in LIN slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 61. LIN header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 62.
s )
LIN identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

(
ct
Figure 63. LIN header reception timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 64. LIN synch field measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 65.
u
LDIV read/write operations when LDUM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
d
Figure 66.
Figure 67.
r o
LDIV read/write operations when LDUM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 68.
Figure 69.
e P
LSF bit set and clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 70.
e t
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
l
Figure 71.
Figure 72.
s o
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
fCLKIN maximum operating frequency vs VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . 182
Figure 73.
Figure 74.
O b
Typical accuracy with RCCR = RCCR0 vs. VDD = 4.5 to 5.5 V and temperature. . . . . . . 184
fRC vs. VDD and temperature for calibrated RCCR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 75.
Figure 76.
) -
Typical accuracy with RCCR = RCCR1 vs. VDD = 3 to 3.6 V and temperature. . . . . . . . 185
fRC vs. VDD and temperature for calibrated RCCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 77.
Figure 78. t (s
PLL x 8 output vs. CLKIN frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

c
Typical IDD in run mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 79.
Figure 80. d u
Typical IDD in slow mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Typical IDD in wait mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 81.
r o
Typical IDD in slow-wait mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 82.
Figure 83.
e P
Typical IDD vs. temperature at VDD = 5 V and fCLKIN = 16 MHz . . . . . . . . . . . . . . . . . . . . 191
Typical IDD vs. temperature and VDD at fCLKIN = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 84.
l e t
Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

s o
Figure 85.
Figure 86.
Typical IPU vs. VDD with VIN = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Typical VOL at VDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

O b
Figure 87.
Figure 88.
Typical VOL at VDD = 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Typical VOL at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 89. Typical VOL at VDD = 3 V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 90. Typical VOL at VDD = 4 V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 91. Typical VOL at VDD = 5 V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 92. Typical VDD - VOH at VDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 93. Typical VDD - VOH at VDD = 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 94. Typical VDD - VOH at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 95. Typical VOL vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 96. Typical VDD - VOH vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 97. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 98. RESET pin protection when LVD Is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 99. SPI slave timing diagram with CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 100. SPI slave timing diagram with CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

12/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 List of figures

Figure 101. SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 102. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 103. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 104. 20-pin plastic small outline package, 300-mil width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 105. QFN 5x6, 20-terminal very thin fine pitch quad flat no-lead package . . . . . . . . . . . . . . . . 213
Figure 106. pin 1 orientation in tape and reel conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 107. ST7FL3x Flash commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 108. ST7FL3x FASTROM commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 109. ROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 110. Header reception event sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 111. LINSCI interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

( s )
u ct
o d
P r
e t e
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

Doc ID 11928 Rev 8 13/234

 Description ST7L34 ST7L35 ST7L38 ST7L39

1 Description

The ST7L3x is a member of the ST7 microcontroller family suitable for automotive
applications. All ST7 devices are based on a common industry-standard 8-bit core, featuring
an enhanced instruction set.
The ST7L3x features Flash memory with byte-by-byte in-circuit programming (ICP) and in-
application programming (IAP) capability.
Under software control, the ST7L3x devices can be placed in wait, slow or halt mode,
reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
( s )
feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

u ct
Table 1. Device summary
o d
Pr
Feature ST7L34 ST7L35 ST7L38 ST7L39

Program memory

e e
8 Kbytes
t
ol
RAM (stack) 384 bytes (128 bytes)
Data EEPROM -

b s Lite timer,
256 bytes
Lite timer,
Peripherals
Lite timer,

-
autoreload timer, O autoreload timer,
SPI, 10-bit ADC,
Lite timer,
autoreload timer,
autoreload timer,
SPI, 10-bit ADC,

(s )
SPI, 10-bit ADC
LINSCI
SPI, 10-bit ADC
LINSCI

ct
Operating supply 3.0 V to 5.5 V

du
CPU frequency Up to 8 MHz (with external resonator/clock or internal RC oscillator)

ro
Operating temperature Up to -40 to 85°C / -40 to 125°C

e P
Packages SO20 300mil, QFN20

1.1 l e t
Parametric data
s o
O b For easy reference, all parametric data is located in Section 13: Electrical characteristics.

1.2 Debug module (DM)

The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD).
For a description of the DM registers, refer to the ST7 ICC protocol reference manual.

14/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Description

Figure 1. General block diagram

Int.
1% RC
1 MHz 12-bit
PLL x8 autoreload
timer 3
CLKIN

/2 8-bit
lite timer 2
OSC1 Ext.
OSC2 osc
1 MHz Internal PA7:0
to clock Port A (8 bits)
16 MHz
PB6:0

)
LVD Port B (7 bits)

Address and data bus

VDD
VSS
Power
supply ADC

ct (
RESET Control
d u
o
Debug module

8-bit core
ALU
P r SPI

e t e
Program

o l LINSCI

s
memory
(8 Kbytes)

O b Watchdog

)-
RAM
Data EEPROM
(384 bytes)

s
(128 bytes)

c t (
d u
r o
e P
l e t
s o
O b

Doc ID 11928 Rev 8 15/234

 Pin description ST7L34 ST7L35 ST7L38 ST7L39

2 Pin description

Figure 2. 20-pin SO package pinout

VSS 1 20 OSC1/CLKIN

VDD 2 19 OSC2
RESET 3 18 PA0 (HS)/LTIC)

SS/AIN0/PB0 4 17 PA1 (HS)/ATIC

SCK/AIN1/PB1 5 ei3 ei0 16 PA2 (HS)/ATPWM0

MISO/AIN2/PB2 6 15 PA3 (HS)/ATPWM1

MOSI/AIN3/PB3 ei2 14 PA4 (HS)/ATPWM2

)
7
CLKIN/AIN4/PB4 8 ei1 13 PA5 (HS)/ATPWM3/ICCDATA

( s
ct
AIN5/PB5 9 12 PA6/MCO/ICCCLK/BREAK
ei2

u
RDI/AIN6/PB6 10 11 PA7 (HS)/TDO

o d
1. eix: Associated external interrupt vector
2. (HS): 20mA high sink capability
P r
Figure 3. 20-pin QFN package pinout
e t e
o l
b s
O
VDD OSC1/CLKIN

)-
20 19 18 17
VSS OSC2

t(s
RESET 1 16 PA0 (HS)/LTIC

uc
SS/AIN0/PB0 2 15 PA1 (HS)/ATIC

o d ei0

r
SCK/AIN1/PB1 3 14 PA2 (HS)/ATPWM0
ei3
eix (HS)
associated
20mA external
high sinkinterrupt
capability
vector

e P MISO/AIN2/PB2 4 13 PA3 (HS)/ATPWM1

l e t MOSI/AIN3/PB3 5 ei2 12 PA4 (HS)/ATPWM2

s o ei1

O b CLKIN/AIN4/PB4 6

7
ei2

RDI/AIN6/PB6
8 9 10
11 PA5 (HS)/ATPWM3/ICCDATA

AIN5/PB5 PA7(HS)/TDO PA6/MCO/ICCCLK/BREAK

16/234 Doc ID 11928 Rev 8

ST7L34 ST7L35 ST7L38 ST7L39 Pin description

Legend/abbreviations for Table 2:

Type: I = input, O = output, S = supply
Input/output level: CT = CMOS 0.3 VDD/0.7 VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration inputs: float = floating, wpu = weak pull-up,
int = interrupt, ana = analog ports
Port and control configuration outputs: OD = open drain, PP = push-pull
Note: The reset configuration of each pin (shown in bold) is valid as long as the device is in reset
state.

Table 2. Device pin description

Pin no. Level Port/control
Main

s )
Type

function
Input(1) Output

ct (
Output
QFN20

Pin name Alternate function

SO20

Input

float (after
wpu
reset)

ana
u
OD

PP
int d
1 19 VSS S Ground
r o
2 20 VDD S
P
Main power supply

e
3 1 RESET I/O CT X X

l e tTop priority non maskable interrupt

(active low)

4 2 PB0/AIN0/SS I/O CT X
s X X oX Port B0
ADC analog input 0 or SPI

5 3 PB1/AIN1/SCK I/O CT X ei3

O b X X X Port B1
slave select (active low)
ADC analog input 1 or SPI

) - serial clock

(s
ADC analog input 2 or SPI
6 4 PB2/AIN2/MISO I/O CT X X X X Port B2

c t master in/slave out data

7 5 PB3/AIN3/MOSI I/O
d u CT X ei2 X X X Port B3
ADC analog input 3 or SPI
master out/slave in data

8 6 PB4/AIN4/CLKIN/ r oI/O CT X X X X X Port B4

ADC analog input 4 or

e P external clock input

let
9 7 PB5/AIN5 I/O CT X X X X Port B5 ADC analog input 5
ei2 ADC analog input 6 or
10

s o 8 PB6/AIN6/RDI I/O CT X X X X Port B6

LINSCI input

Ob
11 9 PA7/TDO I/O CT HS X X X X Port A7 LINSCI output

Doc ID 11928 Rev 8 17/234

 Pin description ST7L34 ST7L35 ST7L38 ST7L39

Table 2. Device pin description (continued)

Pin no. Level Port/control
Main

Type
Input (1)
Output function

Output
QFN20

Pin name Alternate function

SO20

Input
(after

float

wpu
reset)

ana
OD

PP
int
Main clock output or in-
circuit communication clock
or external BREAK
Caution: During normal
operation this pin must be
pulled- up, internally or

12 10
PA6 /MCO/ICCCLK/
I/O CT X X X Port A6
( s )
externally (external pull-up
of 10 k mandatory in noisy

ct
BREAK
environment). This is to
avoid entering ICC mode
ei1

d u
unexpectedly during a reset.

r o
In the application, even if the
pin is configured as output,

e P any reset puts it back in

input pull-up

PA5/ICCDATA/
l e t Autoreload timer PWM3 or
13 11
ATPWM3
I/O CT HS X

s
X
oX Port A5 in-circuit communication
data
14 12 PA4/ATPWM2 I/O CT HS X
O b X X Port A4 Autoreload timer PWM2

)-
15 13 PA3/ATPWM1 I/O CT HS X X X Port A3 Autoreload timer PWM1

t(s
16 14 PA2/ATPWM0 I/O CT HS X X X Port A2 Autoreload timer PWM0
ei0

uc
Autoreload timer input
17 15 PA1/ATIC I/O CT HS X X X Port A1
capture
18 16 PA0/LTIC
o d I/O CT HS X X X X Port A0 Lite timer input capture
19 17 OSC2
P r O Resonator oscillator inverter output

20 18

e t e
OSC1/CLKIN I X
Resonator oscillator inverter input or
external clock input

o l
1. For input with interrupt possibility ‘eix’ defines the associated external interrupt vector which can be assigned to one of the

b s
I/O pins using the EISR register. Each interrupt can be either weak pull-up or floating defined through option register OR.

18/234 Doc ID 11928 Rev 8

ST7L34 ST7L35 ST7L38 ST7L39 Register and memory map

3 Register and memory map

As shown in Figure 4, the MCU can address 64 Kbytes of memories and I/O registers.
The available memory locations consist of 128 bytes of register locations, 384 bytes of
RAM, 256 bytes of data EEPROM and up to 8 Kbytes of user program memory. The RAM
space includes up to 128 bytes for the stack from 180h to 1FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see Figure 4) mapped in the upper part of the ST7
addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh).
The size of Flash sector 0 and other device options are configurable by option byte (refer to
Section 15.2: Option bytes on page 215).
( s )
Note: Memory locations marked as ‘Reserved’ must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
u ct
o d
Figure 4. Memory map
0080h P r
Short addressing
RAM (zero page)

e t e
0000h
HW registers
00FFh
0100h

o l
s
(see Table 3) 16-bit addressing
007Fh RAM
0080h

01FFh
RAM
(384 bytes)
017Fh
0180h

O b
128 bytes stack
0200h
0FFFh
Reserved

) -
01FFh

(s
1000h DEE0h

t
Data EEPROM RCCRH0
DEE1h
10FFh
1100h
(256 bytes)

u c DEE2h
RCCRL0
RCCRH1

od
DEE3h
RCCRL1

r Reserved 8K Flash DEE4h

program memory
DFFFh

e
E000hP See note 1 below and Section 7.1 on page 37

let
E000h 7 Kbytes
Flash memory FBFFh sector 1
FC00h 1 Kbyte

o
(8K)
sector 0

b s FFDFh
FFE0h
Interrupt and reset vectors
FFFFh

O FFFFh
(see Table 14)

1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also the RC
calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC
calibration values locations) has been erased (after the readout protection removal), then the RC calibration values can still
be obtained through these four addresses.

Doc ID 11928 Rev 8 19/234

 Register and memory map ST7L34 ST7L35 ST7L38 ST7L39

Legend for Table 3: x = undefined, R/W = read/write, RO = read only

Table 3. Hardware register map

Register Reset
Address Block Register name Remarks
label status

0000h PADR Port A data register FFh(1) R/W

0001h Port A PADDR Port A data direction register 00h R/W
0002h PAOR Port A option register 40h R/W
0003h PBDR Port B data register FFh(1) R/W
0004h Port B PBDDR Port B data direction register 00h R/W
0005h PBOR Port B option register 00h R/W(2)
0006h
0007h
Reserved area (2 bytes)

( s )
0008h
0009h
LTCSR2
LTARR
Lite timer control/status register 2
Lite timer autoreload register
0Fh

u
00h ct R/W
R/W
000Ah
Lite timer
2
LTCNTR Lite timer counter 2 register

o d 00h RO
000Bh
000Ch
LTCSR1
LTICR
P
Lite timer input capture registerr
Lite timer control/status register 1 0x00 0000b
xxh
R/W
RO
000Dh
000Eh
ATCSR
CNTR1H
Timer control/status register
Counter register 1 high
e t e 0x00 0000b
00h
R/W
RO
000Fh CNTR1L
l
Counter register 1 low
o
00h RO
0010h
0011h
0012h
ATR1H
ATR1L
PWMCR
s
Autoreload register 1 high

b
Autoreload register 1 low
PWM output control register
00h
00h
00h
R/W
R/W
R/W
0013h PWM0CSR
O
PWM 0 control/status register
-
00h R/W
0014h
0015h
PWM1CSR
PWM2CSR
(s ) PWM 1 control/status register
PWM 2 control/status register
00h
00h
R/W
R/W
0016h
0017h
c t
PWM3CSR
DCR0H
PWM 3 control/status register
PWM 0 duty cycle register high
00h
00h
R/W
R/W
0018h
0019h
Auto-
d
reload u
DCR0L
DCR1H
PWM 0 duty cycle register low
PWM 1 duty cycle register high
00h
00h
R/W
R/W
001Ah
r o
timer 3 DCR1L PWM 1 duty cycle register low 00h R/W

e P
001Bh
001Ch
DCR2H
DCR2L
PWM 2 duty cycle register high
PWM 2 duty cycle register low
00h
00h
R/W
R/W

l e t
001Dh
001Eh
DCR3H
DCR3L
PWM 3 duty cycle register high
PWM 3 duty cycle register low
00h
00h
R/W
R/W

s o 001Fh
0020h
ATICRH
ATICRL
Input capture register high
Input capture register low
00h
00h
RO
RO

O b 0021h
0022h
ATCSR2
BREAKCR
Timer control/status register 2
Break control register
03h
00h
R/W
R/W
0023h ATR2H Autoreload register 2 high 00h R/W
0024h ATR2L Autoreload register 2 low 00h R/W
0025h DTGR Dead time generator register 00h R/W
0026h to
Reserved area (8 bytes)
002Dh
002Eh WDG WDGCR Watchdog control register 7Fh R/W
0002Fh Flash FCSR Flash control/status register 00h R/W
00030h EEPROM EECSR Data EEPROM control/status register 00h R/W

20/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Register and memory map

Table 3. Hardware register map (continued)

Register Reset
Address Block Register name Remarks
label status

0031h SPIDR SPI data I/O register xxh R/W

0032h SPI SPICR SPI control register 0xh R/W
0033h SPICSR SPI control/status register 00h R/W
0034h ADCCSR A/D control/status register 00h R/W
0035h ADC ADCDRH A/D data register high xxh RO
0036h ADCDRL A/D control and data register low x0h R/W
0037h ITC EICR External interrupt control register 00h R/W
0038h MCC MCCSR Main clock control/status register 00h R/W
0039h Clock and RCCR RC oscillator control register FFh
( s )
R/W
003Ah reset SICSR System integrity control/status register 0110 0xx0b

c t R/W
003Bh Reserved area (1 byte)

d u
003Ch ITC EISR External interrupt selection register

r o 00h R/W
003Dh to
003Fh
Reserved area (3 bytes)

e P
SCI status register
e t
ol
0040h SCISR C0h RO
SCI data register
0041h SCIDR xxh R/W
0042h
0043h
LINSCI
(LIN
SCIBRR
SCICR1
b s
SCI baud rate register
SCI control register 1
SCI control register 2
00xx xxxxb
xxh
R/W
R/W
0044h
0045h
master/
slave)
SCICR2
SCICR3
- O
SCI control register 3
00h
00h
R/W
R/W
0046h
0047h
SCIERPR
SCIETPR
(s ) SCI extended receive prescaler register
SCI extended transmit prescaler
00h
00h
R/W
R/W

c t register
0048h
u Reserved area (1 byte)

od
0049h AWUPR AWU prescaler register FFh R/W
AWU
004Ah

P
004Bh
r AWUCSR
DMCR
AWU control/status register
DM control register
00h
00h
R/W
R/W

e t e
004Ch DMSR DM status register 00h R/W

o l 004Dh
004Eh
DM(3)
DMBK1H
DMBK1L
DM breakpoint register 1 high
DM breakpoint register 1 low
00h
00h
R/W
R/W

b s 004Fh
0050h
DMBK2H
DMBK2L
DM breakpoint register 2 high
DM breakpoint register 2 low
00h
00h
R/W
R/W

O 0051h to
007Fh
Reserved area (47 bytes)

1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration,
the values of the I/O pins are returned instead of the DR register contents
2. The bits associated with unavailable pins must always keep their reset value
3. For a description of the debug module registers, see ST7 ICC protocol reference manual

Doc ID 11928 Rev 8 21/234

 Flash program memory ST7L34 ST7L35 ST7L38 ST7L39

4 Flash program memory

4.1 Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or
on-board using in-circuit programming (ICP) or in-application programming (IAP).
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.

( s )
4.2 Main features
u ct
● In-circuit programming (ICP)
o d
● In-application programming (IAP)
P r
●
RAM
e te
In-circuit testing (ICT) for downloading and executing user application test patterns in

● Sector 0 size configurable by option byte

o l
● Readout and write protection
b s
4.3 Programming modes - O
(s )
–
c t
The ST7 can be programmed in three different ways:
Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte

d u
row and data EEPROM (if present) can be programmed or erased.
–
r o
In-circuit programming. In this mode, Flash sectors 0 and 1, option byte row and

e P data EEPROM (if present) can be programmed or erased without removing the
device from the application board.

l e t – In-application programming. In this mode, sector 1 and data EEPROM (if present)
can be programmed or erased without removing the device from the application

s o board and while the application is running.

O b
4.3.1 In-circuit programming (ICP)
ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a
printed circuit board (PCB) to communicate with an external programming device connected
via a cable. ICP is performed in three steps:
– Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a
specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled
low. When the ST7 enters ICC mode, it fetches a specific reset vector which points
to the ST7 system memory containing the ICC protocol routine. This routine
enables the ST7 to receive bytes from the ICC interface.
– Download ICP driver code in RAM from the ICCDATA pin
– Execute ICP driver code in RAM to program the Flash memory

22/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Flash program memory

Depending on the ICP driver code downloaded in RAM, Flash memory programming can be
fully customized (number of bytes to program, program locations, or selection of the serial
communication interface for downloading).

4.3.2 In-application programming (IAP)

This mode uses an IAP driver program previously programmed in sector 0 by the user (in
ICP mode).
IAP mode is fully controlled by user software, allowing it to be adapted to the user
application (such as a user-defined strategy for entering programming mode or a choice of
communications protocol used to fetch the data to be stored). This mode can be used to
program any memory areas except sector 0, which is write/erase protected to allow
recovery in case errors occur during the programming operation.

( s )
4.4 ICC interface
u ct
o d
ICP needs a minimum of four and up to six pins to be connected to the programming tool.
These pins are:
– RESET: Device reset P r
– VSS: Device power supply ground
e te
– ICCCLK: ICC output serial clock pin
o l
–
s
ICCDATA: ICC input serial data pin
b
–
–
- O
CLKIN/PB4: Main clock input for external source
VDD: Application board power supply (optional, see note 3, Figure 5: Typical ICC

)
interface on page 24)

(s
c t
d u
r o
e P
l e t
s o
O b

Doc ID 11928 Rev 8 23/234

 Flash program memory ST7L34 ST7L35 ST7L38 ST7L39

Figure 5. Typical ICC interface

Programming tool
ICC connector
ICC cable
ICC connector Application board
(See note 3) HE10 connector type

Optional
(see note 4) 9 7 5 3 1

10 8 6 4 2

Application reset source

See note 2

( s )
ct
Application See note 1 and caution Application I/O
power supply See note 1

d u
o
(see note 5)

RESET

ICCCLK

ICCDATA
CLKIN/PB4
VDD

P r ST7

e t e
o l
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the

s
programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as inputs by the application, isolation such as a serial resistor must be

b
implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended
resistor values.

- O
2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the

(s )
programming tool and the application reset circuit if it drives more than 5 mA at high level (push-pull output or pull-up
resistor < 1K). A schottky diode can be used to isolate the application reset circuit in this case. When using a classical RC
network with R > 1K or a reset management IC with open drain output and pull-up resistor > 1K, no additional components

t
are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

c
d u
3. The use of pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when
using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool
manual.

r o
4. Pin 9 must be connected to the PB4 pin of the ST7 when the clock is not available in the application or if the selected clock

case.

e P
option is not programmed in the option byte. ST7 devices with multi-oscillator capability must have OSC2 grounded in this

l e t
5. With any programming tool, while the ICP option is disabled, the external clock must be provided on PB4.
6. In ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte.
Caution:
s o During normal operation the ICCCLK pin must be pulled up, internally or externally (external

O b pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode
unexpectedly during a reset. In the application, even if the pin is configured as output, any
reset puts it back in input pull-up.

24/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Flash program memory

4.5 Memory protection

There are two different types of memory protection: Readout protection and write/erase
protection, which can be applied individually.

4.5.1 Readout protection

Readout protection, when selected, protects against program memory content extraction
and against write access to Flash memory. Even if no protection can be considered as
totally unbreakable, the feature provides a very high level of protection for a general purpose
microcontroller. Both program and data EE memory are protected.
In Flash devices, this protection is removed by reprogramming the option. In this case, both
program and data EE memory are automatically erased and the device can be
reprogrammed.
( s )
Readout protection selection depends on the device type:
●
u ct
In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
●
o d
In ROM devices it is enabled by the mask option specified in the option list.

4.5.2 Flash write/erase protection P r

e te
o l
Write/erase protection, when set, makes it impossible to both overwrite and erase program
memory. It does not apply to EE data. Its purpose is to provide advanced security to
s
applications and prevent any change being made to the memory content.
b
- O
Warning:
)
Once set, write/erase protection can never be removed. A

(s
write-protected Flash device is no longer reprogrammable.

c t
d u
Write/erase protection is enabled through the FMP_W bit in the option byte.

r o
4.6 P
Related documentation
e
l e t
For details on Flash programming and ICC protocol, refer to the ST7 Flash programming

s o reference manual and to the ST7 ICC protocol reference manual.

O b

Doc ID 11928 Rev 8 25/234

 Flash program memory ST7L34 ST7L35 ST7L38 ST7L39

4.7 Register description

Flash control/status register (FCSR)

Reset value: 0000 0000 (00h)

FCSR 1st RASS key: 0101 0110 (56h)
2nd RASS key: 10101110 (AEh)
7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved Reserved OPT LAT PGM

- - - - - R/W R/W R/W

( s )
ct
Note: This register is reserved for programming using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing operations.

d u
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
r o
e P
l e t
s o
O b
) -
c t (s
d u
r o
e P
l e t
s o
O b

26/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Data EEPROM

5 Data EEPROM

5.1 Introduction
The electrically erasable programmable read only memory can be used as a non volatile back-up for
storing data. Using the EEPROM requires a basic access protocol described in this chapter.

5.2 Main features

● Up to 32 bytes programmed in the same cycle
●
●
EEPROM mono-voltage (charge pump)
Chained erase and programming cycles
( s )
●
●
Internal control of the global programming cycle duration
Wait mode management u ct
● Readout protection
o d
Figure 6. EEPROM block diagram P r
e t e
o l High voltage pump

b s
EECSR 0 0 0 0 0 0

- O
E2LAT E2PGM

(s )
c t
Address

d
decoder u 4 Row
decoder
EEPROM
memory matrix

r o (1 row = 32 x 8 bits)

e P
let
128 128

so
4 Data 32 x 8 bits

b multiplexer data latches

O 4

Address bus Data bus

Doc ID 11928 Rev 8 27/234

 Data EEPROM ST7L34 ST7L35 ST7L38 ST7L39

5.3 Memory access

The data EEPROM memory read/write access modes are controlled by the E2LAT bit of the
EEPROM control/status register (EECSR). The flowchart in Figure 7: Data EEPROM
programming flowchart on page 29 describes these different memory access modes.

Read operation (E2LAT = 0)

The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR
register is cleared.
On this device, data EEPROM can also be used to execute machine code. Do not write to
the data EEPROM while executing from it. This would result in an unexpected code being
executed.

Write operation (E2LAT = 1)

( s )
u ct
To access the write mode, the E2LAT bit must be set by software (the E2PGM bit remains

32 data latches according to its address.

o d
cleared). When a write access to the EEPROM area occurs, the value is latched inside the

P r
When PGM bit is set by the software, all the previous bytes written in the data latches (up to

e te
32) are programmed in the EEPROM cells. The effective high address (row) is determined
by the last EEPROM write sequence. To avoid wrong programming, the user must ensure
l
that all the bytes written between two programming sequences have the same high address:
o
b s
Only the five least significant bits of the address can change.
At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.
Note:
- O
Care should be taken during the programming cycle. Writing to the same memory location
)
over-programs the memory (logical AND between the two write access data results)

(s
c t
because the data latches are only cleared at the end of the programming cycle and by the
falling edge of the E2LAT bit. It is not possible to read the latched data. This note is

u
illustrated by Figure 9: Data EEPROM programming cycle on page 31.
d
r o
e P
l e t
s o
O b

28/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Data EEPROM

Figure 7. Data EEPROM programming flowchart

Read mode Write mode

E2LAT = 0 E2LAT = 1
E2PGM = 0 E2PGM = 0

Write up to 32 bytes
Read bytes
in EEPROM area
in EEPROM area
(with the same 11 MSB of the address)

Start programming cycle

( s )
ct
E2LAT = 1

u
E2PGM = 1 (set by software)

o d
0
E2LAT
P r 1

Cleared by hardware

e t e
o l
Figure 8. Data EEPROM write operation b s
- O
⇓ Row/byte ⇒

(s ) 0 1 2 3 ... 30 31 Physical address

ct
0 00h...1Fh

du
Row definition 1 20h...3Fh

r o ...

P
N Nx20h...Nx20h+1Fh

e t e
ol
Read operation impossible Read operation possible

b s Byte 1 Byte 2 Byte 32 Programming cycle

O Phase 1 Phase 2

Writing data latches Waiting E2PGM and E2LAT to fall

E2LAT bit
Set by user application Cleared by hardware
E2PGM bit

1. If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed.

Doc ID 11928 Rev 8 29/234

 Data EEPROM ST7L34 ST7L35 ST7L38 ST7L39

5.4 Power saving modes

Wait mode
The data EEPROM can enter wait mode on execution of the WFI instruction of the
microcontroller or when the microcontroller enters active halt mode.The data EEPROM
immediately enters this mode if there is no programming in progress, otherwise the data
EEPROM finishes the cycle and then enters wait mode.

Active halt mode

Refer to wait mode.

Halt mode

(
The data EEPROM immediately enters halt mode if the microcontroller executes the HALTs )
corrupted.
u ct
instruction. Therefore, the EEPROM stops the function in progress, and data may be

o d
5.5 Access error handling P r
t e
If a read access occurs while E2LAT = 1, then the data bus is not driven.
e
o l
If a write access occurs while E2LAT = 0, then the data on the bus is not latched.

b s
If a programming cycle is interrupted (by reset action), the integrity of the data in memory is
not guaranteed.

- O
5.6 Data EEPROM readout
( s ) protection
c t
page 215).
d u
The readout protection is enabled through an option bit (see Section 15.2: Option bytes on

r o
When this option is selected, the programs and data stored in the EEPROM memory are
P
protected against readout (including a rewrite protection). In Flash devices, when this

e
t
protection is removed by reprogramming the option byte, the entire program memory and

e
ol
EEPROM is first automatically erased.

b s
Note: Both program memory and data EEPROM are protected using the same option bit.

30/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Data EEPROM

Figure 9. Data EEPROM programming cycle

Read operation not possible Read operation possible

Internal
programming
voltage
Erase cycle Write cycle

Write of
data latches tPROG

LAT

( s )
ct
PGM

d u
5.7 Register description r o
e P
EEPROM control/status register (EECSR)

l e t
EECSR
s o Reset value: 0000 0000 (00h)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
O b 3
Reserved
2
Reserved
1
E2LAT E2PGM
0

- - -
) - - - - R/W R/W

Table 4. EECSR register description

c t (s
u
od
Bit Bit name Function

Pr
7:2 - Reserved, forced by hardware to 0
Latch access transfer

1
e t e E2LAT
This bit is set by software. It is cleared by hardware at the end of the programming
cycle. It can only be cleared by software if the E2PGM bit is cleared.

ol
0: Read mode

b s 1: Write mode
Programming control and status

O 0 E2PGM
This bit is set by software to begin the programming cycle. At the end of the
programming cycle, this bit is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: If the E2PGM bit is cleared during the programming cycle, the
memory data is not guaranteed

Table 5. Data EEPROM register map and reset values

Address (Hex.) Register label 7 6 5 4 3 2 1 0

EECSR E2LAT E2PGM

0030h
Reset value 0 0 0 0 0 0 0 0

Doc ID 11928 Rev 8 31/234

 Central processing unit ST7L34 ST7L35 ST7L38 ST7L39

6 Central processing unit

6.1 Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-
bit data manipulation.

6.2 Main features

● 63 basic instructions
●
●
Fast 8-bit by 8-bit multiply
17 main addressing modes
( s )
●
●
Two 8-bit index registers
16-bit stack pointer u ct
● Low power modes
o d
● Maskable hardware interrupts
P r
● Non-maskable software interrupt

e te
o l
6.3 CPU registers
b s
accessed by specific instructions.
- O
The six CPU registers shown in Figure 10 are not present in the memory mapping and are

Figure 10. CPU registers

(s )
c t
u
od
7 0
Accumulator register

P r Reset value = XXh

7 0

e t e Reset value = XXh

X index register

o l 7 0

s
Y index register

O b 15 PCH 8 7
Reset value = XXh

PCL 0
Program counter regsiter
Reset value = reset vector @ FFFEh-FFFFh
7 0
1 1 1 H I N Z C Condition code register
Reset value = 1 1 1 X 1 X X X

15 8 7 0
Stack pointer register
Reset value = stack higher address

1. X = undefined value

32/234 Doc ID 11928 Rev 8

ST7L34 ST7L35 ST7L38 ST7L39 Central processing unit

Accumulator register (A)

The accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.

Index registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective
addresses or temporary storage areas for data manipulation. (The cross-assembler
generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).

Program counter register (PC)

( s )
u ct
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers, PCL (program counter low which is
the LSB) and PCH (program counter high which is the MSB).
o d
Condition code register (CC)
P r
e t e
CC

o l Reset value: 111x 1xxx

bs
7 6 5 4 3 2 1 0

1 1 1 H I N Z C

- O R/W R/W R/W R/W R/W

( s )
c t
The 8-bit condition code register contains the interrupt masks and four flags representative

d u
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.

r o
These bits can be individually tested and/or controlled by specific instructions.

e P
let
Table 6. CC register description
Bit Bit name Function

s o Half carry

Ob This bit is set by hardware when a carry occurs between bits 3 and 4
of the ALU during an ADD or ADC instructions. It is reset by
4 H hardware during the same instructions.
0: No half carry has occurred
1: A half carry has occurred
This bit is tested using the JRH or JRNH instruction. The H bit is
useful in BCD arithmetic subroutines.

Doc ID 11928 Rev 8 33/234

 Central processing unit ST7L34 ST7L35 ST7L38 ST7L39

Table 6. CC register description (continued)

Bit Bit name Function

Interrupt mask
This bit is set by hardware when entering in interrupt or by software
to disable all interrupts except the TRAP software interrupt. This bit
is cleared by software.
0: Interrupts are enabled
1: Interrupts are disabled
This bit is controlled by the RIM, SIM and IRET instructions and is
3 I tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be
processed when I is cleared. By default an interrupt routine is

( s )
not interruptible because the I bit is set by hardware at the start
of the routine and reset by the IRET instruction at the end of the

ct
routine. If the I bit is cleared by software in the interrupt routine,
pending interrupts are serviced regardless of the priority level of
the current interrupt routine.
d u
Negative
r o
e P
This bit is set and cleared by hardware. It is representative of the
result sign of the last arithmetic, logical or data manipulation. It is a
2 N
l t
copy of the 7th bit of the result.
e
0: The result of the last operation is positive or null

s o
1: The result of the last operation is negative (in other words, the
most significant bit is a logic 1)
b
This bit is accessed by the JRMI and JRPL test instructions.

O
Zero

) -
This bit is set and cleared by hardware. This bit indicates that the
1 Z

c t (s result of the last arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero

d u 1: The result of the last operation is zero

This bit is accessed by the JREQ and JRNE test instructions.

r o Carry/borrow

e P This bit is set and cleared by hardware and software. It indicates an

overflow or an underflow has occurred during the last arithmetic

l e t 0 C
operation.
0: No overflow or underflow has occurred

s o 1: An overflow or underflow has occurred

O b This bit is driven by the SCF and RCF instructions and tested by the
JRC and JRNC instructions. It is also affected by the ‘bit test and
branch’, shift and rotate instructions.

34/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Central processing unit

Stack pointer register (SP)

SP Reset value: 01 FFh

15 14 13 12 11 10 9 8

Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1

- - - - - - - R/W
7 6 5 4 3 2 1 0

1 SP[6:0]

R/W R/W

( s )
ct
The stack pointer is a 16-bit register which always points to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented

d u
before data is popped from the stack (see Figure 11: Stack manipulation example on
page 36).
r o
e P
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware.
Following an MCU reset, or after a reset stack pointer instruction (RSP), the stack pointer

l e t
contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.

instruction.
s o
The least significant byte of the stack pointer (called S) can be directly accessed by a LD

Note:
O b
When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit,

) -
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.

t (s
The stack is used to save the return address during a subroutine call and the CPU context
c
during an interrupt. The user may also directly manipulate the stack by means of the PUSH

d u
and POP instructions. In the case of an interrupt, the PCL is stored at the first location

r o
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 11: Stack manipulation example on page 36.
●

e P
When an interrupt is received, the SP is decremented and the context is pushed on the

l e
●
t stack
On return from interrupt, the SP is incremented and the context is popped from the

s o stack

O b A subroutine call occupies two locations and an interrupt five locations in the stack area.

Doc ID 11928 Rev 8 35/234

 Central processing unit ST7L34 ST7L35 ST7L38 ST7L39

Figure 11. Stack manipulation example

Call Interrupt PUSH Y POP Y IRET RET or RSP

subroutine event

@ 0180h

SP
SP SP
Y
CC CC CC
A A A
X X X

SP
PCH
PCL
PCH
PCL
PCH
PCL SP

( s )
@ 01FFh
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
u ct
SP

o d
1. Legend: stack higher address = 01FFh; stack lower address = 0180h
P r
e t e
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

36/234 Doc ID 11928 Rev 8

ST7L34 ST7L35 ST7L38 ST7L39 Supply, reset and clock management

7 Supply, reset and clock management

The device includes a range of utility features for securing the application in critical
situations (for example, in case of a power brown-out) and reducing the number of external
components.
Main features
● Clock management
– 1 MHz internal RC oscillator (enabled by option byte)
– 1 to 16 MHz or 32 kHz external crystal/ceramic resonator (selected by option byte)
– External clock input (enabled by option byte)
– PLL for multiplying the frequency by 8 (enabled by option byte)
( s )
ct
● Reset sequence manager (RSM)
● System integrity management (SI)
–
d u
Main supply low voltage detection (LVD) with reset generation (enabled by option
byte)
r o
–
P
Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main

e
l e t
supply (enabled by option byte)

7.1 s
Internal RC oscillator adjustment o
O b
The device contains an internal RC oscillator with high accuracy for a given device,

) -
temperature and voltage. It must be calibrated to obtain the frequency required in the
application. This is done by the software writing an 8-bit calibration value in the RCCR (RC

t ( s
control register) and in the bits [6:5] in the SICSR (SI control status register).

u c
Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), that is,

d
each time the device is reset, the calibration value must be loaded in the RCCR. Predefined

o
P r
calibration values are stored in EEPROM for 3.3 V and 5 V VDD supply voltages at 25°C, as
shown in Table 7.

e t e
Table 7. RCCR calibration registers

ol RCCR Conditions ST7L3 addresses

Obs RCCRH0

RCCRL0
VDD = 5 V
TA = 25°C
fRC = 1 MHz(1)
DEE0h(2) (CR[9:2] bits)

DEE1h(2) (CR[1:0] bits)

RCCRH1 VDD = 3.3 V DEE2h(2)(CR[9:2] bits)

TA = 25°C
RCCRL1 fRC = 1 MHz(1) DEE3h(2) (CR[1:0] bits)

1. RCCR0 and RCCR1 calibrated within these conditions in order to reach RC accuracy as mentioned in
Table 101: Operating conditions (tested for TA = -40 to +125 °C) @ VDD = 4.5 to 5.5 V on page 183 and
Table 103: Operating conditions (tested for TA = -40 to +125 °C) @ VDD = 3.0 to 3.6 V on page 184
2. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes
containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM
data or Flash space (including the RC calibration values locations) has been erased (after the readout
protection removal), then the RC calibration values can still be obtained through these four addresses.
For compatibility reasons with the SICSR register, CR[1:0] bits are stored in the fifth and sixth positions of
DEE1 and DEE3 addresses.

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Supply, reset and clock management ST7L34 ST7L35 ST7L38 ST7L39

Note: 1 In ICC mode, the internal RC oscillator is forced as a clock source, regardless of the
selection in the option byte.
2 For more information on the frequency and accuracy of the RC oscillator see Section 13:
Electrical characteristics.
3 To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100 nF, between the VDD and VSS pins as close as possible to the ST7
device.
4 These bytes are systematically programmed by ST, including on FASTROM devices.
Consequently, customers intending to use FASTROM service must not use these bytes.
5 RCCR0 and RCCR1 calibration values are not erased if the readout protection bit is reset
after it has been set (see Section 4.5.1: Readout protection on page 25).
Caution: If the voltage or temperature conditions change in the application, the frequency may need
to be recalibrated.
( s )
Refer to application note AN1324 for information on how to calibrate the RC frequency using
u ct
an external reference signal.

o d
7.2 Phase locked loop P r
e t e
o l
The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external
clock by 8 to obtain an fOSC of 8 MHz. The PLL is enabled (by 1 option bit) and the
multiplication factor is 8.
● b s
The x8 PLL is intended for operation with VDD in the 3.6 V to 5.5 V range.

- O
If the PLL is disabled and the RC oscillator is enabled, then fOSC = 1 MHz.

(s )
If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock.

c t
u
Figure 12. PLL output frequency timing diagram

d
r o
e P LOCKED bit set

let
4/8 x input freq.

s o
Output frequency

Ob tSTAB

tLOCK

tSTARTUP

When the PLL is started, after reset or wakeup from halt mode or AWUFH mode, it outputs
the clock after a delay of tSTARTUP.

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 ST7L34 ST7L35 ST7L38 ST7L39 Supply, reset and clock management

When the PLL output signal reaches the operating frequency, the locked bit in the SICSCR
register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of tSTAB (see
Figure 12 and Section 13.3.4: Internal RC oscillator and PLL on page 188).
Refer to Section 7.6.4: Register description on page 48 for a description of the locked bit in
the SICSR register.

7.3 Register description

Main clock control/status register (MCCSR)

MCCSR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1
( s )0

Reserved Reserved Reserved Reserved Reserved Reserved MCO

u ct SMS

- - - - - -
o d R/W R/W

Table 8. MCCSR register description P r

Bit Bit name
e t e
Function

o l
7:2 -
s
Reserved, must be kept cleared

b
Main clock out enable

1 MCO O
This bit is read/write by software and cleared by hardware after a

-
reset. This bit enables the MCO output clock.

(s )
0: MCO clock disabled, I/O port free for general purpose I/O

c t 1: MCO clock enabled

d u Slow mode select

This bit is read/write by software and cleared by hardware after a
0
r o SMS reset. This bit selects the input clock fOSC or fOSC/32.

e P 0: Normal mode (fCPU = fOSC)

1: Slow mode (fCPU = fOSC/32)

l e t
s o RC control register (RCCR)

O b RCCR
7 6 5 4 3 2
Reset value: 1111 1111 (FFh)
1 0

CR[9:2]

R/W

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 Supply, reset and clock management ST7L34 ST7L35 ST7L38 ST7L39

Table 9. RCCR register description

Bit Bit name Function

RC oscillator frequency adjustment bits

These bits must be written immediately after reset to adjust the RC
oscillator frequency and to obtain an accuracy of 1%. The
application can store the correct value for each voltage range in
EEPROM and write it to this register at startup.
00h = Maximum available frequency
7:0 CR[9:2]
FFh = Lowest available frequency
These bits are used with the CR[1:0] bits in the SICSR register.
Refer to Section 7.6.4: Register description on page 48.
Note: To tune the oscillator, write a series of different values in the
register until the correct frequency is reached. The fastest
method is to use a dichotomy starting with 80h.
( s )
Figure 13. Clock management block diagram u ct
o d
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 RCCR
P r
e t e
CR1 CR0

o l SICSR

Tunable
1% RC oscillator
1 MHz
O bs CLKIN/2 (ext clock)
RC OSC

) - PLL 1 MHz -> 8 MHz

PLL clock 8 MHz fOSC

s
OSCRANGE[2:0]

CLKIN
c (
option bits

t /2
OSC option bit

u
CLKIN OSC,PLLOFF,
fCLKINCLKIN divider

d
OSCRANGE[2:0]
option bits

r
CLKIN/ o
e POSC1
OSC2
OSC
1-16 MHZ
/2
divider
Crystal OSC /2

l e t or 32 kHz

s o
O b fOSC
8-bit lite timer 2 counter

fOSC/32
fLTIMER
(1ms timebase @ 8 MHz fOSC)

/32DIVIDER
/32 divider 1
fCPU

fOSC To CPU and

0 peripherals

MCO SMS MCCSR

fCPU
MCO

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 ST7L34 ST7L35 ST7L38 ST7L39 Supply, reset and clock management

7.4 Multi-oscillator (MO)

The main clock of the ST7 can be generated by four different source types coming from the
multi-oscillator block (1 to 16 MHz or 32 kHz):
● An external source
● 5 crystal or ceramic resonator oscillators
● An internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 14: ST7 clock sources on page 42. Refer to Section 13: Electrical characteristics for
more details.

7.4.1 External clock source

( s )
drive the OSC1 pin while the OSC2 pin is tied to ground.
u ct
In external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle must

o d
Note:
r
When the multi-oscillator is not used, PB4 is selected by default as the external clock.

P
7.4.2 Crystal/ceramic oscillators

e t e
o l
This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of four oscillators with different frequency ranges

b s
has to be done by option byte in order to reduce consumption (refer to Section 15.2 on page
215 for more details on the frequency ranges). In this mode of the multi-oscillator, the

- O
resonator and the load capacitors must be placed as close as possible to the oscillator pins

(s )
to minimize output distortion and startup stabilization time. The loading capacitance values
must be adjusted according to the selected oscillator.

c t
These oscillators are not stopped during the reset phase to avoid losing time in the oscillator
startup phase.
d u
7.4.3 r o
Internal RC oscillator

e P
In this mode, the tunable 1%RC oscillator is the main clock source. The two oscillator pins

l e t
must be tied to ground.

s o The calibration is done through the RCCR[7:0] and SICSR[6:5] registers.

O b

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 Supply, reset and clock management ST7L34 ST7L35 ST7L38 ST7L39

Figure 14. ST7 clock sources

Hardware configuration

External clock
ST7
OSC1 OSC2

External source
Crystal/ceramic resonators

ST7

( s )
ct
OSC1 OSC2

d u
CL1
rCL2 o
Load
capacitors
e P
l e t
o
Internal RC oscillator

b sOSC1
ST7
OSC2

- O
(s )
c t
d u
7.5 r o
Reset sequence manager (RSM)

e P
7.5.1 t
Introduction
e
s ol The reset sequence manager includes three reset sources as shown in Figure 16: Reset

O b block diagram on page 44:

● External RESET source pulse
● Internal LVD reset (low voltage detection)
● Internal watchdog reset
Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 12.2.2: Illegal opcode reset on page 175 for further details.
These sources act on the RESET pin which is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.

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 ST7L34 ST7L35 ST7L38 ST7L39 Supply, reset and clock management

The basic reset sequence consists of three phases as shown in Figure 15:
● Active phase depending on the reset source
● 256 or 4096 CPU clock cycle delay (see Table 10)
● Reset vector fetch
Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the reset state. The shorter or longer clock cycle delay is
automatically selected depending on the clock source chosen by option byte: The reset
vector fetch phase duration is two clock cycles.

Table 10. Clock cycle delays

( s )
Clock source
ct
CPU clock cycle delay
u
Internal RC oscillator
o d
Pr
256
External clock (connected to CLKIN pin)

ete
External crystal/ceramic oscillator
4096
(connected to OSC1/OSC2 pins)

o l
b s
If the PLL is enabled by option byte, it outputs the clock after an additional delay of tSTARTUP
(see Figure 12: PLL output frequency timing diagram on page 38).

Figure 15. Reset sequence phases

- O
(s )
c t
d u Reset

r o Active phase
Internal reset
256 or 4096 clock cycles
Fetch vector

e P
l e t
7.5.2
s o Asynchronous external RESET pin

O b The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Section 13: Electrical
characteristics for more details.
A reset signal originating from an external source must have a duration of at least th(RSTL)in
in order to be recognized (see Figure 17: Reset sequences on page 45). This detection is
asynchronous and therefore the MCU can enter the reset state even in halt mode.

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 Supply, reset and clock management ST7L34 ST7L35 ST7L38 ST7L39

Figure 16. Reset block diagram

VDD

RON

RESET Filter Internal reset

Watchdog reset
Pulse Illegal opcode reset(1)
generator

)
LVD reset

( s
u ct
d
1. See Section 12.2.2: Illegal opcode reset on page 175 for more details on illegal opcode reset conditions

o
P r
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in Section 13:
Electrical characteristics.

e t e
7.5.3 External power-on reset
o l
b s
If the LVD is disabled by the option byte, to start up the microcontroller correctly, the user

- O
must use an external reset circuit to ensure that the reset signal is held low until VDD is over
the minimum level specified for the selected fOSC frequency.

(s )
A proper reset signal for a slow rising VDD supply can generally be provided by an external

t
RC network connected to the RESET pin.
c
7.5.4
d u
Internal low voltage detector (LVD) reset

r o
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
●
e P
Power-on reset

l
●
e t Voltage drop reset

s o The device RESET pin acts as an output that is pulled low when VDD < VIT+ (rising edge) or
VDD < VIT- (falling edge) as shown in Figure 17: Reset sequences on page 45.

O b The LVD filter spikes on VDD larger than tg(VDD) to avoid parasitic resets.

7.5.5 Internal watchdog reset

The reset sequence generated by an internal Watchdog counter overflow is shown in
Figure 17: Reset sequences on page 45.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.

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ST7L34 ST7L35 ST7L38 ST7L39 Supply, reset and clock management

Figure 17. Reset sequences

VDD

VIT+(LVD)
VIT-(LVD)

LVD External Watchdog

reset reset reset
Run Run Run Run
Active Active
Active phase phase phase

( s )
th(RSTL)in

u ct
tw(RSTL)out

External
RESET

o d
source

P r
e
RESET pin

Watchdog
l e t
reset

s o
Internal reset (256 or 4096 tCPU)
O b Watchdog underflow

Vector fetch

) -
c t (s
7.6
u
System integrity management (SI)
d
r o
The system integrity management block contains the low voltage detector (LVD) and
auxiliary voltage detector (AVD) functions. It is managed by the SICSR register.
Note:
e P
A reset can also be triggered following the detection of an illegal opcode or prebyte code.

l e t
Refer to Section 12.2.2: Illegal opcode reset on page 175 for further details.

o
bs
7.6.1 Low voltage detector (LVD)

O The low voltage detector (LVD) function generates a static reset when the VDD supply
voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well
as the power-down, keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value
for power-on to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).
The LVD reset circuitry generates a reset when VDD is below:
– VIT+(LVD) when VDD is rising
– VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 18: Low voltage detector vs. reset on page 46.
The LVD can be enabled by option byte with highest voltage threshold.

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 Supply, reset and clock management ST7L34 ST7L35 ST7L38 ST7L39

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD),
the MCU can only be in two modes:
– Under full software control
– In static safe reset
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to
reset other devices.
Note: 1 The LVD allows the device to be used without any external reset circuitry.
2 The LVD is an optional function which can be selected by the option byte.
3

( s )
Use of LVD with capacitive power supply: With this type of power supply, if power cuts occur
in the application, it is recommended to pull VDD down to 0 V to ensure optimum restart

enabled on page 206 and Note on the same page.

u ct
conditions. Refer to the circuit example in Figure 98: RESET pin protection when LVD Is

4
o d
For the application to function correctly, it is recommended to make sure that the VDD supply

functions properly.
P r
voltage rises monotonously when the device is exiting from reset, to ensure the application

Figure 18. Low voltage detector vs. reset

e te
VDD
o l
b s
Vhys
VIT+(LVD)
VIT-(LVD)
- O
(s )
c t
d u
RESET

r o
e P
l e t
s o
O b

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ST7L34 ST7L35 ST7L38 ST7L39 Supply, reset and clock management

Figure 19. Reset and supply management block diagram

Watchdog timer
Status flag
(WDG)

System integrity management

AVD interrupt request
Reset sequence
RESET SICSR
manager (RSM)
WD LOC LV AV AV
GRF KED DRF DF DIE

VSS
Low voltage
detector

( s )
ct
VDD (LVD)

Auxiliary voltage
detector
d u
r (AVD)
o
e P
7.6.2 Low power modes l e t
s o
Table 11.
b
Effect of low power modes on system integrity

O
)-
Mode Description

Wait

t ( s
No effect on SI. AVD interrupts cause the device to exit from wait mode.
The SICSR register is frozen. The AVD becomes inactive and the AVD interrupt
Halt

u c
cannot be used to exit from halt mode.

o d
7.6.3 r
Interrupts
P
e te
The AVD interrupt event generates an interrupt if the corresponding enable control bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

o l
bs
Table 12. Supply, reset and clock management interrupt control/wake-up capability
Interrupt event Event flag Enable control bit Exit from wait Exit from halt
O AVD event AVDF AVDIE Yes No

Auxiliary voltage detector (AVD)

The voltage detector function (AVD) is based on an analog comparison between a VIT-(AVD)
and VIT+(AVD) reference value and the VDD main supply voltage (VAVD). The VIT-(AVD)
reference value for falling voltage is lower than the VIT+(AVD) reference value for rising
voltage in order to avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly readable by the application software through a
real time status bit (AVDF) in the SICSR register. This bit is read only.
Caution: The AVD functions only if the LVD is enabled through the option byte.

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 Supply, reset and clock management ST7L34 ST7L35 ST7L38 ST7L39

Monitoring the VDD main supply

The AVD voltage threshold value is relative to the selected LVD threshold configured by
option byte (see Section 15.2 on page 215).
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
VIT+(LVD) or VIT-(AVD) threshold (AVDF bit is set).
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See Figure 20.

Figure 20. Using the AVD to monitor VDD

VDD
Early warning interrupt
(power has dropped, MCU
not yet in reset)

( s )
ct
Vhyst
VIT+(AVD)

VIT-(AVD)

d u
VIT+(LVD)

r o
VIT-(LVD)

e P
AVDF bit 0 1 RESET
l e t 1 0

s o
b
AVD interrupt
request if
AVDIE bit = 1
O
)-
Interrupt cleared by reset Interrupt cleared by hardware

LVD RESET

t ( s
u c
7.6.4 Register description
o d
P r
System integrity (SI) control/status register (SICSR)

e te
o l SICSR Reset value: 0110 0xx0 (6xh)

b s 7

Reserved
6

CR[1:0]
5

WDGRF
4

LOCKED
3 2

LVDRF
1

AVDF
0

AVDIE

O - R/W R/W R/W R/W R/W R/W

Table 13. SICSR register description

Bit Bit name Function

7 - Reserved, must be kept cleared

RC oscillator frequency adjustment bits
These bits, as well as CR[9:2] bits in the RCCR register must be
6:5 CR[1:0] written immediately after reset to adjust the RC oscillator frequency
and to obtain an accuracy of 1%. Refer to Section 7.3: Register
description on page 39

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ST7L34 ST7L35 ST7L38 ST7L39 Supply, reset and clock management

Table 13. SICSR register description (continued)

Bit Bit name Function

Watchdog reset flag

This bit indicates that the last reset was generated by the watchdog
peripheral. It is set by hardware (watchdog reset) and cleared by
software (by reading SICSR register) or an LVD reset (to ensure a
4 WDGRF stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is
given as follows:
00 (LVDRF, WDGRF): Reset sources = External RESET pin
01 (LVDRF, WDGRF): Reset sources = Watchdog
1X (LVDRF, WDGRF): Reset sources = LVD
PLL locked flag

( s )
ct
This bit is set and cleared by hardware. It is set automatically when
3 LOCKED the PLL reaches its operating frequency.
0: PLL not locked
1: PLL locked
d u
LVD reset flag
r o
P
This bit indicates that the last reset was generated by the LVD block.

e
e t
It is set by hardware (LVD reset) and cleared by software (by
reading). When the LVD is disabled by option byte, the LVDRF bit
l
2 LVDRF value is undefined.

s o
Note: The LVDRF flag is not cleared when another reset type occurs

O b
(external or watchdog), the LVDRF flag remains set to keep
trace of the original failure. In this case, a watchdog reset can

) - be detected by software while an external reset can not.

(s
Voltage detector flag

c t This read-only bit is set and cleared by hardware. If the AVDIE bit is
set, an interrupt request is generated when the AVDF bit is set. Refer
1
u
AVDF
d
to Figure 20 and to Monitoring the VDD main supply on page 48 for

r o additional details.
0: VDD over AVD threshold

e P 1: VDD under AVD threshold

let
Voltage detector interrupt enable
This bit is set and cleared by software. It enables an interrupt to be

s o 0 AVDIE
generated when the AVDF flag is set. The pending interrupt
information is automatically cleared when software enters the AVD

Ob interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled

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 Interrupts ST7L34 ST7L35 ST7L38 ST7L39

8 Interrupts

The ST7 core may be interrupted by one of two different methods: Maskable hardware
interrupts as listed in Table 14: Interrupt mapping on page 53 and a non-maskable software
interrupt (TRAP). The interrupt processing flowchart is shown in Figure 21: Interrupt
processing flowchart on page 52.
The maskable interrupts must be enabled by clearing the I bit in order to be serviced.
However, disabled interrupts may be latched and processed when they are enabled (see
external interrupts subsection).
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:

( s )
ct
● Normal processing is suspended at the end of the current instruction execution.
● The PC, X, A and CC registers are saved onto the stack.
● The I bit of the CC register is set to prevent additional interrupts.
d u
●
r o
The PC is then loaded with the interrupt vector of the interrupt to service and the first

mapping for vector addresses).

e P
instruction of the interrupt service routine is fetched (refer to Table 14: Interrupt

l e t
The interrupt service routine should finish with the IRET instruction which causes the

o
contents of the saved registers to be recovered from the stack.
s
Note:
b
As a consequence of the IRET instruction, the I bit is cleared and the main program
resumes.
O
Priority management
) -
t (s
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
c
entering in interrupt routine.

d u
In the case when several interrupts are simultaneously pending, an hardware priority

r o
defines which one will be serviced first (see Table 14: Interrupt mapping).

e P
Interrupts and low power mode

l e t
All interrupts allow the processor to leave the wait low power mode. Only external and

s o specifically mentioned interrupts allow the processor to leave the halt low power mode (refer
to the ‘Exit from halt’ column inTable 14: Interrupt mapping).

O b
8.1 Non maskable software interrupt
This interrupt is entered when the TRAP instruction is executed regardless of the state of
the I bit. It is serviced according to the flowchart in Figure 21: Interrupt processing flowchart
on page 52.

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 ST7L34 ST7L35 ST7L38 ST7L39 Interrupts

8.2 External interrupts

External interrupt vectors can be loaded into the PC register if the corresponding external
interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the
halt low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt
register (if available).
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
Caution: The type of sensitivity defined in the miscellaneous or interrupt register (if available) applies
to the ei source. In case of a NANDed source (as described in Section 10: I/O ports), a low

case of rising-edge sensitivity.

( s )
level on an I/O pin, configured as input with interrupt, masks the interrupt request even in

u ct
8.3 Peripheral interrupts
o d
they are active if both the following conditions are met: P r
Different peripheral interrupt flags in the status register are able to cause an interrupt when

● The I bit of the CC register is cleared

e t e
●
l
The corresponding enable bit is set in the control register
o
s
If either of these two conditions is false, the interrupt is latched and thus remains pending.
b
Clearing an interrupt request is done by:
●
- O
Writing ‘0’ to the corresponding bit in the status register or
●

(s )
Access to the status register while the flag is set followed by a read or write of an

t
associated register.
c
Note:
u
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
d
being enabled) will therefore be lost if the clear sequence is executed.

r o
e P
l e t
s o
O b

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 Interrupts ST7L34 ST7L35 ST7L38 ST7L39

Figure 21. Interrupt processing flowchart

From reset

N
I bit set?

Y
N Interrupt
pending?

Fetch next instruction Y

)
N
IRET?
Stack PC, X, A, CC

( s
ct
set I bit
Y
load pc from interrupt vector
Execute instruction

d u
r o
Restore PC, X, A, CC from stack
this clears I bit by default

e P
l e t
s o
O b
) -
c t (s
d u
r o
e P
l e t
s o
O b

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 ST7L34 ST7L35 ST7L38 ST7L39 Interrupts

Table 14. Interrupt mapping

Source Register Priority Exit from halt Address
No. Description
block label order or AWUFH vector

Reset Reset Highest Yes FFFEh-FFFFh

- priority
TRAP Software interrupt No FFFCh-FFFDh
(1)
0 AWU Auto wakeup interrupt AWUCSR Yes FFFAh-FFFBh
1 ei0 External interrupt 0 FFF8h-FFF9h
2 ei1 External interrupt 1 FFF6h-FFF7h
- Yes
3 ei2 External interrupt 2 FFF4h-FFF5h
4 ei3 External interrupt 3 FFF2h-FFF3h
5 Lite timer Lite timer RTC2 interrupt LTCSR2 No
s )
FFF0h-FFF1h
(
6 LINSCI LINSCI interrupt
SCICR1/
SCICR2
No

u ct
FFEEh-FFEFh

7 SI AVD interrupt SICSR No

o d FFECh-FFEDh

8
At timer
At timer output compare Interrupt
or input capture interrupt
PWMxCSR
or ATCSR
P r No FFEAh-FFEBh

e
let
9 At timer overflow interrupt ATCSR Yes(2) FFE8h-FFE9h
10 Lite timer input capture interrupt LTCSR No FFE6h-FFE7h
11
Lite timer
Lite timer RTC1 interrupt
s
LTCSRo Yes(2) FFE4h-FFE5h
12 SPI SPI peripheral interrupts
O b
SPICSR Yes FFE2h-FFE3h

13 At timer At timer overflow interrupt 2

) - ATCSR2 lowest
priority
No FFE0h-FFE1h

t ( s
1. This interrupt exits the MCU from ‘auto wakeup from halt’ mode only

u c
2. These interrupts exit the MCU from ‘active halt’ mode only

o d
P r
e t e
o l
b s
O

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Interrupts ST7L34 ST7L35 ST7L38 ST7L39

External interrupt control register (EICR)

EICR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

IS3[1:0] IS2[1:0] IS1[1:0] IS0[1:0]

R/W R/W R/W R/W

Table 15. EICR register description

Bit Bit name Function

ei3 sensitivity

( s )
ct
7:6 IS3[1:0] These bits define the interrupt sensitivity for ei3 (port B0) according
to Table 16
ei2 sensitivity
d u
5:4 IS2[1:0]
r o
These bits define the interrupt sensitivity for ei2 (port B3) according
to Table 16
ei1 sensitivity
e P
3:2 IS1[1:0]
e t
These bits define the interrupt sensitivity for ei1 (port A7) according
to Table 16
l
ei0 sensitivity
s o
1:0 IS0[1:0]
b
These bits define the interrupt sensitivity for ei0 (port A0) according
to Table 16
O
) -
Note: 1
(s
These 8 bits can be written only when the I bit in the CC register is set.

c t
Table 16.
u
Interrupt sensitivity bits
d
ISx1
r o ISx0 External interrupt sensitivity

e P 0 0 Falling edge and low level

let
0 1 Rising edge only
1 0 Falling edge only

s o 1 1 Rising and falling edge

Ob

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 ST7L34 ST7L35 ST7L38 ST7L39 Interrupts

External interrupt selection register (EISR)

Reset value: 0000 0000 (00h)

EISR

7 6 5 4 3 2 1 0

ei3[1:0] ei2[1:0] ei1[1:0] ei0[1:0]

R/W R/W R/W R/W

Table 17. EISR register description

Bit Bit name Function

( s )
ct
ei3 pin selection
These bits are written by software. They select the port B I/O pin

7:6 ei3[1:0]
used for the ei3 external interrupt as follows:
00: I/O pin = No interrupt (reset state)
d u
01: I/O pin = PB0
r o
10: I/O pin = PB1
11: I/O pin = PB2
e P
ei2 pin selection
l e t
s o
These bits are written by software. They select the port B I/O pin
used for the ei2 external interrupt as follows:
5:4 ei2[1:0]
b
00: I/O pin = No interrupt (reset state)

O
01: I/O pin = PB3

) -
10: I/O pin = PB5
11: I/O pin = PB6

c t (sei1 pin selection

These bits are written by software. They select the port A I/O pin

3:2
d u
ei1[1:0]
used for the ei1 external interrupt as follows:
00: I/O pin = No interrupt (reset state)

r o 01: I/O pin = PA4

e P 10: I/O pin = PA5

11: I/O pin = PA6

l e t ei0 pin selection

s o These bits are written by software. They select the port A I/O pin
used for the ei0 external interrupt as follows:

O b 1:0 ei0[1:0] 00: I/O pin = No interrupt (reset state)PA0 (reset state)
01: I/O pin = PA1
10: I/O pin = PA2
11: I/O pin = PA3

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 Power saving modes ST7L34 ST7L35 ST7L38 ST7L39

9 Power saving modes

9.1 Introduction
To give a large measure of flexibility to the application in terms of power consumption, five
main power saving modes are implemented in the ST7 (see Figure 22):
● Slow
● Wait (and Slow-Wait)
● Active halt
● Auto wakeup from halt (AWUFH)
● Halt

( s )
ct
After a reset, the normal operating mode is selected by default (run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (fOSC2).
d u
r o
From run mode, the different power saving modes can be selected by setting the relevant

oscillator status.
e P
register bits or by calling the specific ST7 software instruction whose action depends on the

Figure 22. Power saving mode transitions

l e t
s o
O b High

( s )- Run

c t Slow

d u
r o Wait

e P Slow wait

l e t
o
Active halt

b s Auto wakeup from halt

O Halt

Low

Power consumption

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 ST7L34 ST7L35 ST7L38 ST7L39 Power saving modes

9.2 Slow mode

This mode has two targets:
● To reduce power consumption by decreasing the internal clock in the device
● To adapt the internal clock frequency (fCPU) to the available supply voltage.
Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables
slow mode.
In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked
at this lower frequency.
Note: Slow-wait mode is activated when entering wait mode while the device is already in slow
mode.

( s )
ct
Figure 23. Slow mode clock transition

fOSC/32 fOSC

d u
fCPU

r o
fOSC

e P
l e t
SMS
s o
O b Normal run mode request

) -
c t (s
d u
r o
e P
l e t
s o
O b

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Power saving modes ST7L34 ST7L35 ST7L38 ST7L39

9.3 Wait mode

Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During wait mode, the I bit of the CC register is cleared to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
in wait mode until a reset or an interrupt occurs, causing it to wake up. Then the program
counter branches to the starting address of the interrupt or reset service routine.
Refer to Figure 24: Wait mode flowchart.

Figure 24. Wait mode flowchart

Oscillator On
( s )
ct
Peripherals On
WFI instruction

u
CPU Off
I bit 0

o d
N P r
e t
Reset
e
N
o l Y

s
Interrupt

O b Oscillator On

)-
Peripherals Off
CPU On

t(s
I BIT 0

u c 256 or 4096 CPU clock

o d cycle delay

P r Oscillator On

e t e Peripherals On

l
CPU On

s o I bit X(1)

Ob Fetch reset vector or

service interrupt

1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.

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9.4 Halt mode

The halt mode is the lowest power consumption mode of the MCU. It is entered by executing
the ‘HALT’ instruction when active halt is disabled (see Section 9.5: Active halt mode on
page 61 for more details) and when the AWUEN bit in the AWUCSR register is cleared.
The MCU can exit halt mode on reception of either a specific interrupt (see Table 14:
Interrupt mapping on page 53) or a reset. When exiting halt mode by means of a reset or an
interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is
used to stabilize the oscillator. After the startup delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vector which woke it up (see Figure 26: Halt
mode flowchart on page 60).
When entering halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.

( s )
ct
In halt mode, the main oscillator is turned off, stopping all internal processing, including the

d u
operation of the on-chip peripherals. All peripherals are not clocked except those which
receive their clock supply from another clock generator (such as an external or auxiliary
oscillator).
r o
e P
The compatibility of watchdog operation with halt mode is configured by the ‘WDGHALT’
option bit of the option byte. The HALT instruction, when executed while the watchdog

e t
system is enabled, can generate a watchdog reset (see Section 15.2: Option bytes on
page 215 for more details). l
s o
Figure 25. Halt timing overview

O b
) -
(s
256 or 4096 CPU
Run Halt Run

t
cycle delay

u c
od
Reset or interrupt
HALT
instruction

r
Fetch
[Active halt disabled] vector

e P
l e t
s o
O b

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Power saving modes ST7L34 ST7L35 ST7L38 ST7L39

Figure 26. Halt mode flowchart

HALT instruction
(active Halt disabled)
(AWUCSR.AWUEN=0)

Watchdog
Enable

0 Disable
WDGHALT(1)

Oscillator Off
WATCHDOG
Peripherals(2) Off
RESET
CPU Off
I bit 0

( s )
N
Reset

uct
Y

o d
r
N (3)
Interrupt

Y Oscillator

e P On

let
Peripherals Off
CPU On

o
I bit

s
X(4)

O b 256 or 4096 CPU clock

cycle delays(5)

) -
t ( s Oscillator
Peripherals On
On

c CPU On

du
I bit X(4)

r o
P
Fetch reset vector
or service interrupt

e t e
ol
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.

bs
3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to
Table 14: Interrupt mapping on page 53 for more details.

O 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
5. If the PLL is enabled by option byte, it outputs the clock after a delay of tSTARTUP (see Figure 12 on
page 38).

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 ST7L34 ST7L35 ST7L38 ST7L39 Power saving modes

9.4.1 Halt mode recommendations

● Make sure that an external event is available to wake up the microcontroller from halt
mode.
● When using an external interrupt to wake up the microcontroller, re-initialize the
corresponding I/O as ‘input pull-up with interrupt’ or ‘floating interrupt’ before executing
the HALT instruction. The main reason for this is that the I/O may be incorrectly
configured due to external interference or by an unforeseen logical condition.
● For the same reason, re-initialize the level sensitiveness of each external interrupt as a
precautionary measure.
● The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in program memory with
the value 0x8E.
( s )
●
ct
As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,

u
the user may choose to clear all pending interrupt bits before executing the HALT
d
instruction. This avoids entering other peripheral interrupt routines after executing the
o
interrupt).
P r
external interrupt routine corresponding to the wakeup event (reset or external

e t e
9.5 Active halt mode
o l
b s
Active halt mode is the lowest power consumption mode of the MCU with a real-time clock

- O
(RTC) available. It is entered by executing the ‘HALT’ instruction. The decision to enter either
in active halt or halt mode is given by the LTCSR/ATCSR register status as shown in the
following table:

(s )
Table 18.
c t
LTCSR/ATCSR register status
LTCSR1 TB1IE
uATCSR OVFIE ATCSRCK1 ATCSRCK0

od
Meaning
bit bit bit bit

P r
0 x x 0
Active halt mode disabled

e t e 0 0 x x

o l 1 x x x
Active halt mode enabled

b s x 1 0 1

O The MCU exits in active halt mode on reception of a specific interrupt (see Table 14:
Interrupt mapping on page 53) or a reset.
● When exiting active halt mode by means of a reset, a 256 CPU cycle delay occurs.
After the startup delay, the CPU resumes operation by fetching the reset vector which
woke it up (see Figure 28: Active halt mode flowchart on page 62).
● When exiting active halt mode by means of an interrupt, the CPU immediately resumes
operation by servicing the interrupt vector which woke it up (see Figure 28: Active halt
mode flowchart on page 62).
When entering active halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately (see Figure 28,
Note 2).

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Power saving modes ST7L34 ST7L35 ST7L38 ST7L39

In active halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wakeup time base. All other peripherals are not clocked except those
which receive their clock supply from another clock generator (such as external or auxiliary
oscillator).
Note: As soon as active halt is enabled, executing a HALT instruction while the watchdog is active
does not generate a reset. This means that the device cannot exceed a defined delay in this
power saving mode.

Figure 27. Active halt timing overview

Active 256 or 4096 CPU

Run halt cycle delay(1) Run

( s )
ct
Reset or interrupt
HALT

u
instruction Fetch
[Active halt enabled] vector

o d
1. This delay occurs only if the MCU exits active halt mode by means of a reset.

P r
Figure 28. Active halt mode flowchart

e t e
HALT instruction
o l
Oscillator
Peripherals(1)
On

(active halt enabled)

(AWUCSR.AWUEN = 0)
b s CPU
I bit
Off
Off
0

- O
(s ) N

c t Reset

d u N
Interrupt(2)
Y

r o
P Y Oscillator On
Peripherals(1) Off

e t e CPU
I bit
On
X(3)

o l
bs
256 or 4096 CPU clock
cycle delay

O Oscillator On
Peripherals On
CPU On
I bit X(3)

Fetch reset vector

or service interrupt

1. Peripherals clocked with an external clock source can still be active.

2. Only the RTC1 interrupt and some specific interrupts can exit the MCU from active halt mode. Refer to
Table 14: Interrupt mapping for more details.
3. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.

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9.6 Auto wakeup from halt mode

Auto wakeup from halt (AWUFH) mode is similar to halt mode with the addition of a specific
internal RC oscillator for wakeup (auto wakeup from halt oscillator). Compared to active halt
mode, AWUFH has lower power consumption (the main clock is not kept running but there is
no accurate real-time clock available).
It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR
register has been set.

Figure 29. AWUFH mode block diagram

AWUCK opt bit

AWU RC oscillator 1
To autoreload timer input capture
( s )
ct
32 kHz oscillator
0

fAWU_RC
d u
r o
/64 AWUFH
e P
AWUFH interrupt
divider prescaler/1 .. 255

l e t (ei0 source)

s o
As soon as halt mode is entered and if the AWUEN bit has been set in the AWUCSR

O b
register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output

) -
of this prescaler provides the delay time. When the delay has elapsed, the AWUF flag is set

(s
by hardware and an interrupt wakes up the MCU from halt mode. At the same time, the main

c t
oscillator is immediately turned on and a 256-cycle delay is used to stabilize it. After this
startup delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag

d u
and its associated interrupt are cleared by software reading the AWUCSR register.

r o
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated

e P
by measuring the clock frequency fAWU_RC and then calculating the right prescaler value.
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in run

l e t
mode. This connects fAWU_RC to the input capture of the 12-bit autoreload timer, allowing
the fAWU_RC to be measured using the main oscillator clock as a reference timebase.

s o
O b

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 Power saving modes ST7L34 ST7L35 ST7L38 ST7L39

Similarities with halt mode

The following AWUFH mode behavior is the same as normal halt mode:
● The MCU can exit AWUFH mode by means of any interrupt with exit from halt capability or a reset
(see Section 9.4: Halt mode on page 59).
● When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
● In AWUFH mode, the main oscillator is turned off, stopping all internal processing, including the
operation of the on-chip peripherals. None of the peripherals are clocked except those which receive
their clock supply from another clock generator (such as an external or auxiliary oscillator like the
AWU oscillator).
● The compatibility of watchdog operation with AWUFH mode is configured by the WDGHALT option

Watchdog system is enabled, can generate a watchdog reset.

( s )
bit in the option byte. Depending on this setting, the HALT instruction, when executed while the

Figure 30. AWUF halt timing diagram

uct
o d
r
tAWU

Run mode Halt mode

P
256 or 4096 tCPU

e
Run mode

fCPU
l e t
s o
b
fAWU_RC
Clear

AWUFH interrupt
- O by software

(s )
c t
du
r o
e P
l e t
s o
O b

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 ST7L34 ST7L35 ST7L38 ST7L39 Power saving modes

Figure 31. AWUFH mode flowchart

Halt instruction
(active halt disabled)
(AWUCSR.AWUEN = 1)

Enable
Watchdog

0 Disable
WDGHALT(1)

AWU RC OSC On
Watchdog Main OSC Off
reset Peripherals(2)
CPU
Off
Off

( s )
ct
I[1:0] bits 10

d u
N
Reset
r o
Y

e P
N
Interrupt(3)

l e
AWU RC OSC
t Off
Y
o
Main OSC On

bs
Peripherals Off
CPU On

-O
I[1:0] bits XX(4)

( s ) 256 or 4096 CPU clock

c t cycle delay(5)

d u AWU RC OSC Off

o
Main OSC On

P r Peripherals
CPU
On
On
XX(4)

e
I[1:0] bits

e t
ol
Fetch reset vector

b s or service interrupt

O 1. WDGHALT is an option bit. See Section 15.2: Option bytes on page 215 for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from halt mode (such as external
interrupt). Refer to Table 14: Interrupt mapping on page 53 for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
5. If the PLL is enabled by the option byte, it outputs the clock after an additional delay of tSTARTUP (see
Figure 12: PLL output frequency timing diagram on page 38).

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 Power saving modes ST7L34 ST7L35 ST7L38 ST7L39

Register description

AWUFH control/status register (AWUCSR)

AWUCSR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved Reserved AWUF AWUM AWUEN

- - - - - R/W R/W R/W

Table 19. AWUCSR register description

Bit Bit name Function
( s )
7:3 - Reserved, must be kept cleared

u ct
Auto wakeup flag

o d
This bit is set by hardware when the AWU module generates an
2 AWUF
this bit does not change its value.
r
interrupt and cleared by software on reading AWUCSR. Writing to
P
0: No AWU interrupt occurred
1: AWU interrupt occurred
e te
Auto wakeup measurement
o l
b s
This bit enables the AWU RC oscillator and connects its output to the
input capture of the 12-bit autoreload timer. This allows the timer to
1 AWUM
O
measure the AWU RC oscillator dispersion and then compensate
-
(s )
this dispersion by providing the right value in the AWUPR register.
0: Measurement disabled

c t 1: Measurement enabled

d u Auto wakeup from halt enabled

This bit enables the auto wakeup from halt feature: Once halt mode

r o is entered, the AWUFH wakes up the microcontroller after a time

e P0 AWUEN delay dependent on the AWU prescaler value. It is set and cleared
by software.

l e t 0: AWUFH (auto wakeup from halt) mode disabled

1: AWUFH (auto wakeup from halt) mode enabled

s o
O b

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 ST7L34 ST7L35 ST7L38 ST7L39 Power saving modes

AWUFH prescaler register (AWUPR)

AWUPR Reset value: 1111 1111 (FFh)

7 6 5 4 3 2 1 0

AWUPR[7:0]

R/W

Table 20. AWUPR register description

Bit Bit name Function

7:0 AWUPR[7:0]
Auto wakeup prescaler

( s )
ct
These 8 bits define the AWUPR dividing factor as explained in Table 21

Table 21. AWUPR dividing factor

d u
AWUPR[7:0] Dividing factor
r o
00h Forbidden
e P
01h
l e t 1
...
s o ...
FEh

O b 254

)-
FFh 255

t ( s
In AWU mode, the period that the MCU stays in halt mode (tAWU in Figure 30: AWUF halt timing diagram
on page 64) is defined by
u c
o d 1
t AWU = 64 × AWUPR × -------------------------- + t RCSTRT

r
f AWURC

P
This prescaler register can be programmed to modify the time that the MCU stays in halt mode before
e
l e t
waking up automatically.
Note:

s o If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately

after a HALT instruction or the AWUPR remains unchanged.

O b
Table 22. AWU register map and reset values
Address Register
7 6 5 4 3 2 1 0
(Hex.) label

AWUPR AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0

0049h
Reset value 1 1 1 1 1 1 1 1
AWUCSR
004Ah 0 0 0 0 0 AWUF AWUM AWUEN
Reset value

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 I/O ports ST7L34 ST7L35 ST7L38 ST7L39

10 I/O ports

10.1 Introduction
The I/O ports allow data transfer. An I/O port contains up to eight pins. Each pin can be
programmed independently either as a digital input or digital output. In addition, specific pins
may have several other functions. These functions can include external interrupt, alternate
signal input/output for on-chip peripherals or analog input.

10.2 Functional description

s
A data register (DR) and a data direction register (DDR) are always associated with each
( )
ct
port. The option register (OR), which allows input/output options, may or may not be
implemented. The following description takes into account the OR register. Refer
u
toSection 10.7: Device-specific I/O port configuration on page 73 for device specific
d
information.
r o
Bit x corresponding to pin x of the port.
e P
An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers:

l e t
Figure 32: I/O port general block diagram on page 70 shows the generic I/O block diagram.

10.2.1 Input modes s o

O b
Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital
value from that I/O pin.
) -
t (s
If an OR bit is available, different input modes can be configured by software: Floating or
pull-up. Refer to Section 10.3: I/O port implementation on page 72 for configuration.
c
Note: 1
u
Writing to the DR modifies the latch value but does not change the state of the input pin.
d
2
o
Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.
r
P
External interrupt function
e
l e t
Depending on the device, setting the ORx bit while in input mode can configure an I/O as an
input with interrupt. In this configuration, a signal edge or level input on the I/O generates an

s o interrupt request via the corresponding interrupt vector (eix).Falling or rising edge sensitivity

O b is programmed independently for each interrupt vector. The external interrupt control
register (EICR) or the miscellaneous register controls this sensitivity, depending on the
device.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description in Section 2: Pin description on page 16 and interrupt section).If several I/O
interrupt pins on the same interrupt vector are selected simultaneously, they are logically
combined. For this reason, if one of the interrupt pins is tied low, it may mask the others.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector
automatically clears the request latch. Changing the sensitivity bits clears any pending
interrupts.

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 ST7L34 ST7L35 ST7L38 ST7L39 I/O ports

10.2.2 Output modes

Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the
I/O through the latch. Reading the DR bits returns the previously stored value.
If an OR bit is available, different output modes can be selected by software: Push-pull or
open-drain. Refer to Section 10.3: I/O port implementation on page 72 for configuration.

Table 23. DR value and output pin status

DR Push-pull Open-drain

0 VOL VOL
1 VOH Floating

( s )
ct
10.2.3 Alternate functions

u
Many ST7 I/Os have one or more alternate functions. These may include output signals
d
r
describes which peripheral signals can be input/output to which ports.o
from, or input signals to, on-chip peripherals. Table 2: Device pin description on page 17

e P
A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the

l e t
on-chip peripheral as an output (enable bit in the peripheral’s control register). The
peripheral configures the I/O as an output and takes priority over standard I/O programming.

s o
The I/O’s state is readable by addressing the corresponding I/O data register.

O b
Configuring an I/O as floating enables alternate function input. It is not recommended to
configure an I/O as pull-up as this increases current consumption. Before using an I/O as an
-
alternate input, configure it without interrupt. Otherwise spurious interrupts can occur.
)
output.
c t (s
Configure an I/O as input floating for an on-chip peripheral signal which can be input and

Caution:
u
I/Os which can be configured as both an analog and digital alternate function need special
d
r o
attention. The user must control the peripherals so that the signals do not arrive at the same
time on the same pin. If an external clock is used, only the clock alternate function should be
P
employed on that I/O pin and not the other alternate function.

e
l e t
s o
O b

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 I/O ports ST7L34 ST7L35 ST7L38 ST7L39

Figure 32. I/O port general block diagram

Alternate
Register 1
output VDD P-buffer
access from on-chip peripheral (see table below)
0

Alternate Pull-up
enable bit (see table below

DR VDD

DDR
Pull-up
condition

( s )
Pad

OR
If implemented

u ct
Data bus

OR SEL

o d
N-buffer

P r Diodes

e
(see table below)
DDR SEL

l e t Analog input

o
bs
CMOS
Schmitt
DR SEL
1

- O trigger

( s ) Alternate input
tot on-chip peripheral
External

c t
Combinational

du
Interrupt
Logic From
request (eix)
other

r o
Sensitivity
selection
bits

e P
Table 24.
e t I/O port mode options(1)

s ol Configuration mode Pull-up P-buffer

Diodes

O b Floating with/without interrupt Off

to VDD(2) to VSS

Input Off
Pull-up with/without interrupt On
On
Push-pull On On
Off
Output Open drain (logic level) Off
True open drain NI NI NI(3)
1. Legend: Off = implemented not activated; On = implemented and activated
2. The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VOL is
implemented to protect the device against positive stress.
3. For further details on port configuration, please refer to Table 28: Port configuration (standard ports) and Table 29: Port
configuration (external interrupts) on page 73.

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 ST7L34 ST7L35 ST7L38 ST7L39 I/O ports

Table 25. I/O configuration

Hardware configuration

DR register access
VDD Note 3

Pull-up
RPU condition DR W
register Data bus
Pad R
Input(1)

Alternate input to on-chip

peripheral
From other
pins
External interrupt
source (eix)

)
Interrupt
condition Combinational Polarity
logic selection

( s
ct
Analog input

d u
o
Note 3
VDD

P r DR register access
Open-drain output(2)

RPU

e
let
Pad DR R/W
register Data bus

s o
O b
) -
Note 3 DR register access

t
VDD

( s
c
RPU
Push-pull output(2)

R/W

du
DR
register Data bus
Pad

r o
e P Alternate Alternate output

t
enable bit from on-chip peripheral

ol e 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.

b s 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.

O 3. For true open drain, these elements are not implemented

Analog alternate function

Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled
by the ADC registers) switches the analog voltage present on the selected pin to the
common analog rail, connected to the ADC input.

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I/O ports ST7L34 ST7L35 ST7L38 ST7L39

Analog recommendations
Do not change the voltage level or loading on any I/O while conversion is in progress. Do not
have clocking pins located close to a selected analog pin.

Warning: The analog input voltage level must be within the limits
stated in the absolute maximum ratings.

10.3 I/O port implementation

The hardware implementation on each I/O port depends on the settings in the DDR and OR
( s )
ct
registers and specific I/O port features such as ADC input or open drain.
Switching these I/O ports from one state to another should be done in a sequence that
d u
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 33.

r
Other transitions are potentially risky and should be avoided, since they may presento
unwanted side-effects such as spurious interrupt generation.

e P
Figure 33. Interrupt I/O port state transitions
l e t
s o
01

O b
00 10 11

)-
Input Input Output Output
floating/pull-up floating open-drain push-pull

t ( s
interrupt (reset state)

c
du
XX = DDR, OR

r o
P
e I/O pins
10.4
e t
Unused
ol
bs
Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.8: I/O port
pin characteristics on page 199.

O
10.5 Low-power modes
Table 26. Effect of low power modes on I/O ports
Mode Description

Wait No effect on I/O ports. External interrupts cause the device to exit from wait mode.
Halt No effect on I/O ports. External interrupts cause the device to exit from halt mode.

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 ST7L34 ST7L35 ST7L38 ST7L39 I/O ports

10.6 Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM
instruction).

Table 27. I/O interrupt control/wake-up capability

Interrupt event Event flag Enable control bit Exit from wait Exit from halt

External interrupt on selected DDRx

- Yes Yes
external event ORx

Related documentation

( s )
ct
● SPI communication between ST7 and EEPROM (AN970)
● S/W implementation of I2C bus master (AN1045)
● Software LCD driver (AN1048)
d u
r o
10.7 Device-specific I/O port configuration
e P
l e t
The I/O port register configurations are summarized as follows:

s o
Table 28.

O b
Port configuration (standard ports)
Input (DDR = 0) Output (DDR = 1)
Port
-
Pin name

) OR = 0 OR = 1 OR = 0 OR = 1

Port A
t ( s
PA7:0
Port B
u c PB6:0
Floating Pull-up Open drain Push-pull

o d
P r
On ports where the external interrupt capability is selected using the EISR register, the
configuration is as follows:

e t e
o l Table 29. Port configuration (external interrupts)
Input with interrupt (DDR = 0; EISR ≠ 00)

b s Port Pin name

OR = 0 OR = 1
O Port A PA6:1
Floating Pull-up
Port B PB5:0

Table 30. I/O port register map and reset values

Address (Hex.) Register label 7 6 5 4 3 2 1 0

PADR MSB LSB

0000h
Reset value 1 1 1 1 1 1 1 1
PADDR MSB LSB
0001h
Reset value 0 0 0 0 0 0 0 0

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 I/O ports ST7L34 ST7L35 ST7L38 ST7L39

Table 30. I/O port register map and reset values (continued)
Address (Hex.) Register label 7 6 5 4 3 2 1 0

PAOR MSB LSB

0002h
Reset value 0 1 0 0 0 0 0 0
PBDR MSB LSB
0003h
Reset value 1 1 1 1 1 1 1 1
PBDDR MSB LSB
0004h
Reset value 0 0 0 0 0 0 0 0
PBOR MSB LSB
0005h
Reset value 0 0 0 0 0 0 0 0

( s )
u ct
o d
P r
e te
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

11 On-chip peripherals

11.1 Watchdog timer (WDG)

11.1.1 Introduction
The watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The watchdog circuit generates an MCU reset
upon expiration of a programmed time period, unless the program refreshes the counter’s
contents before the T6 bit is cleared.

11.1.2 Main features

( s )
● Programmable free-running downcounter (64 increments of 16000 CPU cycles)
u ct
● Programmable reset
o d
●
●
Reset (if watchdog activated) when the T6 bit reaches zero
Optional reset on HALT instruction (configurable by option byte) P r
● Hardware watchdog selectable by option byte
e t e
o l
11.1.3 Functional description
b s
The counter value stored in the CR register (bits T[6:0]) is decremented every 16000
O
machine cycles and the length of the timeout period can be programmed by the user in 64
-
increments.

(s )
c t
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin
for typically 30 µs.
d u
r o
Figure 34. Watchdog block diagram

e P Reset

l e t
s o
O b Watchdog control register (CR)

WDGA T6 T5 T4 T3 T2 T1 T0

7-bit downcounter

Clock divider ÷ 16000

fCPU

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. This downcounter is free-running: It counts down, even
if the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see Table 31):
● The WDGA bit is set (watchdog enabled)
● The T6 bit is set to prevent generating an immediate reset
● The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset.
Following a reset, the watchdog is disabled. Once activated, it can be disabled only by a
reset.
The T6 bit can generate a software reset (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction generates a reset.
( s )
.

Table 31. Watchdog timing(1)

u ct
fCPU = 8 MHz
o d
WDG counter code min. (ms)
P r max (ms)

C0h 1

e t e 2
FFh 127

o l 128

CR register.
b s
1. The timing variation shown in Table 31 is due to the unknown status of the prescaler when writing to the

11.1.4 Hardware watchdog option

- O
(s )
If hardware watchdog is selected by the option byte, the watchdog is always active and the

c t
WDGA bit in the CR is not used.

d u
Refer to the option byte description in Section 15.2: Option bytes on page 215.

r o
Using halt mode with the WDG (WDGHALT option)

e P
If halt mode with watchdog is enabled by the option byte (no watchdog reset on HALT

l e t
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

s o
O b
11.1.5 Interrupts
None.

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11.1.6 Register description

Watchdog control register (WDGCR)

WDGCR Reset value: 0111 1111 (7Fh)

7 6 5 4 3 2 1 0

WDGA T[6:0]

R/W R/W

Table 32. WDGCR register description

Bit Bit name Function
( s )
Activation bit (1)

u ct
This bit is set by software and only cleared by hardware after a reset.
7 WDGA When WDGA = 1, the watchdog can generate a reset.
o d
0: Watchdog disabled
1: Watchdog enabled
P r
7-bit counter (MSB to LSB)

e t e
6:0 T[6:0]
l
These bits contain the decremented value. A reset is produced when

o
it rolls over from 40h to 3Fh (T6 becomes cleared).

b s
1. The WDGA bit is not used if the hardware watchdog option is enabled by option byte.

Table 33.
- O
Watchdog timer register map and reset values
Address (Hex.)
(s )
Register label 7 6 5 4 3 2 1 0

c
WDGCRt WDGA T6 T5 T4 T3 T2 T1 T0
002Eh

d u
Reset value 0 1 1 1 1 1 1 1

r o
e P
l e t
s o
O b

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

11.2 Dual 12-bit autoreload timer 3 (AT3)

11.2.1 Introduction
The 12-bit autoreload timer can be used for general-purpose timing functions. It is based on
one or two free-running 12-bit upcounters with an input capture register and four PWM
output channels. There are six external pins:
● 4 PWM outputs
● ATIC/LTIC pin for the input capture function
● BREAK pin for forcing a break condition on the PWM outputs

11.2.2 Main features

( s )
ct
● Single timer or dual timer mode with two 12-bit upcounters (CNTR1/CNTR2) and two
12-bit autoreload registers (ATR1/ATR2)
● Maskable overflow interrupts
d u
● PWM mode
r o
–
–
Generation of four independent PWMx signals

e P
Dead time generation for half-bridge driving mode with programmable dead time
– Frequency 2 kHz to 4 MHz (@ 8 MHz fCPU)
l e t
– Programmable duty-cycles
s o
–
–
Polarity control
Programmable output modes
O b
● Output compare mode
) -
(s
● Input capture mode
–
c t
12-bit input capture register (ATICR)
–
u
Triggered by rising and falling edges
d
–
– r o
Maskable IC interrupt
Long range input capture
●
e P
Break control

l e
● t Flexible clock control

s o
O b

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Figure 35. Single timer mode (ENCNTR2 = 0)

ATIC Edge detection circuit 12-bit input capture

Output compare CMP

interrupt

OE0
PWM0 duty cycle generator PWM0
Dead time
12-bit autoreload register 1
generator OE1

Break function
PWM1 duty cycle generator PWM1
Clock 12-bit upcounter 1
Control DTE bit
OE2
PWM2 duty cycle generator
OE3
( s ) PWM2

ct
1ms from lite timer

PWM3 duty cycle generator PWM3

fCPU

du
BPEN bit

OVF1 interrupt
r o
e P
e t
Figure 36. Dual timer mode (ENCNTR2 = 1)

s ol
ATIC Edge detection circuit 12-bit input capture
O b
) - CMP

(s
Output compare
interrupt

c t
u
12-bit autoreload register 1 OE0
PWM0 duty cycle generator Dead time PWM0

od
generator OE1
PWM1 duty cycle generator PWM1
Break function

Clock
P r12-bit upcounter 1

OVF1 interrupt DTE bit

control
e OVF2 interrupt

let
OE2
12-bit upcounter 2 PWM2 duty cycle generator PWM2

so
OE3
PWM3 duty cycle generator PWM3
fCPU
1ms

O b 12-bit autoreload register 2

BPEN bit

11.2.3 Functional description

PWM mode
This mode allows up to four pulse width modulated signals to be generated on the PWMx
output pins.
PWM frequency

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

The four PWM signals can have the same frequency (fPWM) or can have two different
frequencies. This is selected by the ENCNTR2 bit which enables single timer or dual timer
mode (see Figure 35: Single timer mode (ENCNTR2 = 0) on page 79 and Figure 36: Dual
timer mode (ENCNTR2 = 1) on page 79).
The frequency is controlled by the counter period and the ATR register value. In dual timer
mode, PWM2 and PWM3 can be generated with a different frequency controlled by CNTR2
and ATR2.
fPWM = fCOUNTER/(4096 - ATR)

Following the above formula, if fCOUNTER is 4 MHz, the maximum value of fPWM is 2 MHz
(ATR register value = 4094), the minimum value is 1 kHz (ATR register value = 0).
Duty cycle

( s )
ct
The duty cycle is selected by programming the DCRx registers. These are preload registers.
The DCRx values are transferred in active duty cycle registers after an overflow event if the
corresponding transfer bit (TRANx bit) is set.
d u
r o
The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit controls
the PWMx outputs driven by counter 2.

e P
with the counter.
l e t
PWM generation and output compare are done by comparing these active DCRx values

s o
The maximum available resolution for the PWMx duty cycle is:

b
Resolution = 1/(4096 - ATR)
O
-
Where ATR is equal to 0. With this maximum resolution, 0% and 100% duty cycle can be
)
(s
obtained by changing the polarity.

c t
At reset, the counter starts counting from 0.

d u
When an upcounter overflow occurs (OVF event), the preloaded duty cycle values are

r o
transferred to the active duty cycle registers and the PWMx signals are set to a high level.
When the upcounter matches the active DCRx value, the PWMx signals are set to a low
P
level. To obtain a signal on a PWMx pin, the contents of the corresponding active DCRx
e
Note:
l t
register must be greater than the contents of the ATR register.

e
For ROM devices only: The PWM can be enabled/disabled only in overflow ISR, otherwise

s o the first pulse of PWM can be different from expected one because no force overflow

O b function is present.
The maximum value of ATR is 4094 because it must be lower than the DCR value, which in
this case must be 4095.
Polarity inversion
The polarity bits can be used to invert any of the four output signals. The inversion is
synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2
register is set (reset value). See Figure 37.

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Figure 37. PWM polarity inversion

Inverter
PWMx PWMx pin

PWMxCSR register OPx

DFF
ATCSR2 register TRANx

Counter overflow

The data flip flop (DFF) applies the polarity inversion when triggered by the counter overflow input.
( s )
Output control
u ct
The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR register.
o d
Figure 38. PWM function
P r
4095

e te
Duty cycle
register
o l
(DCRx)

b s
Counter

Autoreload
register
- O
(ATR)

(s )
ct
000
t

u
PWMx output

With OE=1
and OPx=0

o d
With OE=1
and OPx=1
P r
e t e
o l
b s
O

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Figure 39. PWM signal from 0% to 100%duty cycle

fCOUNTER

ATR= FFDh

Counter FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh

With MOD00=1

DCRx=000h
PWMx output

And OPx=0

DCRx=FFDh

DCRx=FFEh
With MOD00=1

)
PWMx output

s
And OPx=1

DCRx=000h

ct (
d u t

r o
Dead time generation
e P
e t
A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for
l
half-bridge driving where PWM signals must not be overlapped. The non-overlapping PWM0/PWM1

s o
signals are generated through a programmable dead time by setting the DTE bit.

O b
Dead time value = DT[6:0] x Tcounter1

) -
DTGR[7:0] is buffered inside so as to avoid deforming the current PWM cycle. The DTGR effect will take
place only after an overflow.
Note: 1
c t (s
Dead time is generated only when DTE = 1 and DT[6:0] ≠ 0. If DTE is set and DT[6:0] = 0,
u
PWM output signals will be at their reset state.
d
2
o
Half-bridge driving is possible only if polarities of PWM0 and PWM1 are not inverted, that is,
r
if OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be
P
generated.
e
l e t
s o
O b

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Figure 40. Dead time generation

Tcounter1

CK_CNTR1

CNTR1 DCR0 DCR0+1 OVF ATR1

counter = DCR0
PWM 0
if DTE = 0

counter = DCR1
PWM 1

( s )
PWM 0
Tdt

u ct
d
if DTE = 1

Tdt
r o
PWM 1

e P
l e t
Tdt = DT[6:0] x Tcounter1

In the above example, when the DTE bit is set:

s o
●
O b
PWM goes low at DCR0 match and goes high at ATR1 + Tdt
●
-
PWM1 goes high at DCR0 + Tdt and goes low at ATR match.
)
(s
With this programmable delay (Tdt), the PWM0 and PWM1 signals which are generated are
not overlapped.
c t
Break function
d u
r o
The break function can be used to perform an emergency shutdown of the application being

P
driven by the PWM signals.

e
l e t
The break function is activated by the external BREAK pin (active low). In order to use the
break pin it must be previously enabled by software setting the BPEN bit in the BREAKCR

s o register.

O b When a low level is detected on the break pin, the BA bit is set and the break function is
activated. In this case, the four PWM signals are stopped.
Software can set the BA bit to activate the break function without using the break pin.
When a break function is activated (BA bit = 1 and BREN1/BREN2 = 1):
● The break pattern (PWM[3:0] bits in the BREAKCR is forced directly on the PWMx
output pins (after the inverter)
● The 12-bit PWM counter CNTR1 is put to its reset value, that is, 00h
● The 12-bit PWM counter CNTR2 is put to its reset value, that is 00h
● ATR1, ATR2, preload and active DCRx are put to their reset values
● The PWMCR register is reset
● Counters stop counting

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

When the break function is deactivated after applying the break (BA bit goes from 1 to 0 by
software):
● The control of the four PWM outputs is transferred to the port registers.

Figure 41. Block diagram of break function

BREAK pin (active low)

BREAKCR register
BA BPEN PWM3 PWM2 PWM1 PWM0

1
PWM0

( s )
ct
PWM1

d u PWM2
PWM0

o
Pr
PWM1 PWM3
PWM2 0
PWM3

e t e
ol
(Inverters) When BA is set:
PWM counter -> reset value

s
ATRx & DCRx -> reset value
PWM Mode -> reset value

O b
-
1. The BREAK pin value is latched by the BA bit

)
c t (s
d u
r o
e P
l e t
s o
O b

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Output compare mode

To use this function, load a 12-bit value in the preload DCRxH and DCRxL registers.
When the 12-bit upcounter CNTR1 reaches the value stored in the active DCRxH and
DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is
generated if the CMPIE bit is set.
The output compare function is always performed on CNTR1 in both single timer mode and
dual timer mode and never on CNTR2. The difference is that in single timer mode the
counter 1 can be compared with any of the four DCR registers and in dual timer mode, the
counter 1 is compared with DCR0 or DCR1.
Note: 1 The output compare function is only available for DCRx values other than 0 (reset value).
2 Duty cycle registers are buffered internally. The CPU writes in preload duty cycle registers
and these values are transferred to active duty cycle registers after an overflow event if the
( s )
ct
corresponding transfer bit (TRAN1 bit) is set. Output compare is done by comparing these
active DCRx values with the counter.

d u
Figure 42. Block diagram of output compare mode (single timer)
r o
DCRx

e P
Preload duty cycle regx

l e t
s o
(ATCSR2) TRAN1

(ATCSR) OVF
O b
) -
t (s
Active duty cycle regx

c
d
CNTR1
u Output compare circuit

r o Counter 1

e P CMP CMPFx (PWMxCSR)

l e t Interrupt request
CMPIE (ATCSR)

s o
O b

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Input capture mode

The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter CNTR1 after a
rising or falling edge is detected on the ATIC pin. When an input capture occurs, the ICF bit is set and the
ATICR register contains the value of the free running upcounter. An IC interrupt is generated if the ICIE
bit is set. The ICF bit is reset by reading the ATICRH/ATICRL register when the ICF bit is set. The ATICR
is a read only register and always contains the free running upcounter value which corresponds to the
most recent input capture. Any further input capture is inhibited while the ICF bit is set.

Figure 43. Block diagram of input capture mode

ATIC 12-bit input capture register

ATICR
IC interrupt request

( s )
ct
ATCSR

ICF ICIE CK1 CK0

d u
r o
fLTIMER

e P
t
(1 ms
timebase
@ 8 MHz)

fCPU CNTR1
12-bit upcounter1

o l e
Off ATR1
b s
12-bit autoreload register

- O
Figure 44. Input capture timing diagram
(s )
c t
fCOUNTER

d u
Counter1
r o
P
01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah

ATIC pin

e t e
o l Interrupt ATICR read Interrupt

b s ICF flag

O xxh 04h 09h

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Long input capture

Pulses that last between 8 µs and 2 s can be measured with an accuracy of 4µs if fOSC =
8 MHz under the following conditions:
● The 12-bit AT3 timer is clocked by the lite timer (RTC pulse: CK[1:0] = 01 in the ATCSR
register)
● The ICS bit in the ATCSR2 register is set so that the LTIC pin is used to trigger the AT3
timer capture.
● The signal to be captured is connected to LTIC pin
● Input capture registers LTICR, ATICRH and ATICRL are read
This configuration allows to cascade the lite timer and the 12-bit AT3 timer to get a 20-bit
input capture value. Refer to Figure 45.

( s )
ct
Figure 45. Long range input capture block diagram

LTICR
d u
8-bit input capture register
r o
8 LSB bits

e P
fOSC/32 8-bit timebase counter1

l e t
s o Lite timer

O b 12-bit ARTIMER
20
cascaded

) - ATR1 bits

(s
12-bit autoreload register

ICS
c t
fLTIMER
fcpu
CNTR1
12-bit upcounter1

u Off

od
LTIC
ATICR
1

Pr
ATIC 12-bit input capture register 12 MSB bits
0

e t e
ol
Since the input capture flags (ICF) for both timers (AT3 timer and LT timer) are set when
signal transition occurs, software must mask one interrupt by clearing the corresponding

b s ICIE bit before setting the ICS bit.

O If the ICS bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the
input capture signal because of different values on LTIC and ATIC. To avoid this situation, it
is recommended to do the following:
● First, reset both ICIE bits
● Then set the ICS bit
● Reset both ICF bits
● Then set the ICIE bit of desired interrupt

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Both timers are used to compute a pulse length with long input capture feature. The
procedure is not straight-forward and is as follows:
● At the first input capture on the rising edge of the pulse, we assume that values in the
registers are as follows:
– LTICR = LT1
– ATICRH = ATH1
– ATICRL = ATL1
– Hence ATICR1 [11:0] = ATH1 & ATL1
– Refer to Figure 46.
● At the second input capture on the falling edge of the pulse, we assume that the values
in the registers are as follows:
– LTICR = LT2

( s )
ct
– ATICRH = ATH2
–
–
ATICRL = ATL2
Hence ATICR2 [11:0] = ATH2 & ATL2
d u
Now pulse width P between first capture and second capture is: r o
e P
P = decimal (F9 – LT1 + LT2 + 1) * 0.004ms + decimal (ATICR2 - ATICR1 – 1) * 1ms

l e t
Figure 46. Long range input capture timing diagram
s o
fOSC/32
O b
TB counter1 F9h 00h LT1
) - F9h 00h ___ ___ ___ LT2 ___ ___

CNTR1 ___
c t (s
ATH1 & ATL1 ___ ATH2 & ATL2

d u
LTIC

r o
LTICR

e P 00h LT1 LT2

l e t
ATICRH 0h ATH1 ATH2

s o
O b ATICRL 00h ATL1 ATL2

ATICR = ATICRH[3:0] & ATICRL[7:0]

11.2.4 Low power modes

Table 34. Effect of low power modes on AT3 timer

Mode Description

Slow The input frequency is divided by 32

Wait No effect on AT timer

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ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Table 34. Effect of low power modes on AT3 timer (continued)

Active halt AT timer halted except if CK0 = 1, CK1 = 0 and OVFIE = 1
Halt AT timer halted

11.2.5 Interrupts

Table 35. AT3 interrupt control/wake-up capability

Interrupt Event Enable Exit Exit Exit from
event(1) flag control bit from wait from Halt active halt

Overflow event OVF1 OVFIE1 Yes(2)

AT3 IC event ICF ICIE Yes No

( s
No)
ct
CMP event CMPFx CMPIE

d u
1. The CMP and AT3 IC events are connected to the same interrupt vector. The OVF event is mapped on a
separate vector (see Section 8: Interrupts). They generate an interrupt if the enable bit is set in the ATCSR
register and the interrupt mask in the CC register is reset (RIM instruction).
2. Only if CK0 = 1 and CK1 = 0 (fCOUNTER = fLTIMER)
r o
e P
11.2.6 Register description
l e t
Timer control status register (ATCSR)
s o
ATCSR
O b Reset value: 0x00 0000 (x0h)
7 6 5
) - 4 3 2 1 0

Reserved ICF

ct (s
ICIE CK[1:0] OVF1 OVFIE1 CMPIE

du
- R/W R/W R/W R/W R/W R/W

r o
Table 36.
P ATCSR register description

ete
Bit Bit name Function

ol
7 - Reserved, must be kept cleared

bs
Input capture flag
This bit is set by hardware and cleared by software by reading the

O 6 ICF ATICR register (a read access to ATICRH or ATICRL clears this flag).
Writing to this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
IC interrupt enable
This bit is set and cleared by software.
5 ICIE
0: Input capture interrupt disabled
1: Input capture interrupt enabled

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On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Table 36. ATCSR register description (continued)

Bit Bit name Function

Counter clock selection

These bits are set and cleared by software and cleared by hardware
after a reset. They select the clock frequency of the counter as follows/
4:3 CK[1:0] 00: Counter clock selection = off
01: Counter clock selection = fLTIMER (1ms timebase @ 8 MHz)
10: Counter clock selection = fCPU
11: Counter clock selection = off
Overflow flag
This bit is set by hardware and cleared by software by reading the
TCSR register. It indicates the transition of the counter1 CNTR1 from
2 OVF1
FFh to ATR1 value.

( s )
ct
0: No counter overflow occurred
1: Counter overflow occurred
Overflow interrupt enable
d u
1 OVFIE1 reset. o
This bit is read/write by software and cleared by hardware after a
r
0: Overflow interrupt disabled

e P
1: Overflow interrupt enabled
Compare interrupt enable
l e t
s o
This bit is read/write by software and cleared by hardware after a
0 CMPIE
CMPFx bit is set.
O b
reset. It can be used to mask the interrupt generated when any of the

0: Output compare interrupt disabled

) -
1: Output compare interrupt enabled

c t (s
Counter register 1 high (CNTR1H)

d u
CNTR1H
r o Reset value: 0000 0000 (00h)

e P
15 14 13 12 11 10 9 8

let
Reserved Reserved Reserved Reserved CNTR1[11:8]

s o - - - - R

Ob Counter register 1 low (CNTR1L)

CNTR1L Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

CNTR1[7:0]

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Table 37. CNTR1H and CNTR1L register descriptions

Bit Bit name Function

15:12 - Reserved, must be kept cleared

Counter value
This 12-bit register is read by software and cleared by hardware after
a reset. The counter CNTR1 increments continuously as soon as a
counter clock is selected. To obtain the 12-bit value, software should
read the counter value in two consecutive read operations. The
11:0 CNTR1[11:0] CNTR1H register can be incremented between the two reads, and in
order to be accurate when fTIMER = fCPU, the software should take
this into account when CNTR1L and CNTR1H are read. If CNTR1L
is close to its highest value, CNTR1H could be incremented before it

s )
is read. When a counter overflow occurs, the counter restarts from

(
ct
the value specified in the ATR1 register.

d u
r o
e P
l e t
s o
O b
) -
c t (s
d u
r o
e P
l e t
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On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Autoreload register high (ATR1H)

ATR1H Reset value: 0000 0000 (00h)

15 14 13 12 11 10 9 8

Reserved Reserved Reserved Reserved ATR1[11:8]

- - - - R/W

Autoreload register low (ATR1L)

ATR1L Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1
( s )0

ATR1[7:0]
u ct
R/W
o d
P r
Table 38.
Bit
ATR1H and ATR1L register descriptions
Bit name
e t e
l
Function

15:12 -
s
Reserved, must be kept cleared
o
O b
Autoreload register 1
This is a 12-bit register which is written by software. The ATR1
11:0 ATR1[11:0]
-
register value is automatically loaded into the upcounter CNTR1
)
(s
when an overflow occurs. The register value is used to set the PWM

c t frequency.

d u
PWM output control register (PWMCR)

r o
e P
PWMCR Reset value: 0000 0000 (00h)

let
7 6 5 4 3 2 1 0

Reserved OE3 Reserved OE2 Reserved OE1 Reserved OE0

s o
Ob - R/W - R/W - R/W - R/W

Table 39. PWMCR register description

Bit Bit name Function

7, 5, 3, 1 - Reserved, must be kept cleared

PWMx output enable
These bits are set and cleared by software and cleared by hardware
after a reset.
6, 4, 2, 0 OE[3:0]
0: PWM mode disabled. PWMx output alternate function disabled
(I/O pin free for general purpose I/O)
1: PWM mode enabled

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

PWMx control status register (PWMxCSR)

PWMxCSR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved Reserved Reserved OPx CMPFx

- - - - - - R/W R/W

Table 40. PWMxCSR register description

Bit Bit name Function

7:2 - Reserved, must be kept cleared

( s )
ct
PWMx output polarity

1 OPx u
This bit is read/write by software and cleared by hardware after a

d
reset. This bit selects the polarity of the PWM signal.
0: The PWM signal is not inverted
1: The PWM signal is inverted
r o
PWMx compare flag
e P
l e t
This bit is set by hardware and cleared by software by reading the
PWMxCSR register. It indicates that the upcounter value matches
0 CMPFx
o
the active DCRx register value.
s
b
0: Upcounter value does not match DCRx value
1: Upcounter value matches DCRx value
O
) -
c t (s
d u
r o
e P
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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Break control register (BREAKCR)

BREAKCR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

Reserved Reserved BA BPEN PWM[3:0]

- - R/W R/W R/W

Table 41. BREAKCR register description

Bit Bit name Function

7:6 - Reserved, must be kept cleared

( s )
ct
Break active

5 BA and set by hardware when the break pin is low. Itu

This bit is read/write by software, cleared by hardware after reset

d
activates/deactivates the break function.
0: Break not active
r o
1: Break active

e P
Break pin enable

l e t
This bit is read/write by software and cleared by hardware after
4 BPEN reset.
s o
b
0: Break pin disabled
1: Break pin enabled
O
) -
Break pattern
These bits are read/write by software and cleared by hardware after
3:0 PWM[3:0]

c t(s a reset. They are used to force the four PWMx output signals into a
stable state when the break function is active and corresponding

d u OEx bit is set.

r o
e P
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PWMx duty cycle register high (DCRxH)

DCRxH Reset value: 0000 0000 (00h)

15 14 13 12 11 10 9 8

Reserved Reserved Reserved Reserved DCRx[11:8]

- - - - R/W

PWMx duty cycle register low (DCRxL)

DCRxL Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1
( s0)
DCRx[7:0]
u ct
R/W
o d
P r
Table 42.
Bit
DCRxH and DCRxL register descriptions
Bit name
e te
l
Function

15:12 -
s
Reserved, must be kept cleared
o
O b
PWMx duty cycle value
This 12-bit value is written by software. It defines the duty cycle of

11:0 DCRx[11:0]
) -
the corresponding PWM output signal (see Figure 38: PWM function

(s
on page 81). In PWM mode (OEx = 1 in the PWMCR register) the

c t DCRx[11:0] bits define the duty cycle of the PWMx output signal
(see Figure 38). In output compare mode, they define the value to be

d u compared with the 12-bit upcounter value.

r o
e P
l e t
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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Input capture register high (ATICRH)

ATICRH Reset value: 0000 0000 (00h)

15 14 13 12 11 10 9 8

Reserved Reserved Reserved Reserved ICR[11:8]

- - - - R

Input capture register low (ATICRL)

ATICRL Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1
( s0)
ICR[7:0]
u ct
R
o d
P r
Table 43.
Bit
ATICRH and ATICRL register descriptions
Bit name
e t e
l
Function

15:12 -
s o
Reserved, must be kept cleared

O b
Input capture data
This is a 12-bit register which is readable by software and cleared by
11:0 ICR[11:0]
) -
hardware after a reset. The ATICR register contains the captured

(s
value of the 12-bit CNTR1 register when a rising or falling edge

c t occurs on the ATIC or LTIC pin (depending on ICS). Capture will only
be performed when the ICF flag is cleared.

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Timer control register2 (ATCSR2)

ATCSR2 Reset value: 0000 0011 (03h)

7 6 5 4 3 2 1 0

Reserved Reserved ICS OVFIE2 OVF2 ENCNTR2 TRAN2 TRAN1

- - R/W R/W R/W R/W R/W R/W

Table 44. ATCSR2 register description

Bit Bit name Function

7:6 - Reserved, must be kept cleared

( s )
ct
Input capture shorted

5 ICS use the LTIC pin for long input capture. u

This bit is read/write by software. It allows the AT timer CNTR1 to

d
0: ATIC for CNTR1 input capture
1: LTIC for CNTR1 input capture
r o
Overflow interrupt 2 enable
e P
4 OVFIE2 of counter 2.
l t
This bit is read/write by software and controls the overflow interrupt
e
o
0: Overflow interrupt disabled
s
Overflow flag
O b
1: Overflow interrupt enabled

) -
This bit is set by hardware and cleared by software by reading the
ATCSR2 register. It indicates the transition of the counter 2 from

(s
3 OVF2
FFFh to ATR2 value.

c t 0: No counter overflow occurred

u 1: Counter overflow occurred

r od Enable counter 2
This bit is read/write by software and switches the second counter

e P
2 ENCNTR2 CNTR2. If this bit is set, PWM2/3 is generated using CNTR2
0: CNTR2 stopped

l e t 1: CNTR2 starts running

o
bs
Transfer enable 2
This bit is read/write by software, cleared by hardware after each

O 1 TRAN2
completed transfer and set by hardware after reset. It controls the
transfers on CNTR2. It allows the value of the preload DCRx
registers to be transferred to the active DCRx registers after the next
overflow event. The OPx bits are transferred to the shadow OPx bits
in the same way.
Note: Only DCR2/3 can be controlled using this bit

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Table 44. ATCSR2 register description (continued)

Bit Bit name Function

Transfer enable 1
This bit is read/write by software, cleared by hardware after each
completed transfer and set by hardware after reset. It controls the
0 TRAN1 transfers on CNTR1. It allows the value of the preload DCRx
registers to be transferred to the active DCRx registers after the next
overflow event. The OPx bits are transferred to the shadow OPx bits
in the same way.

Autoreload register2 high (ATR2H)

( s )
ATR2H
ct
Reset value: 0000 0000 (00h)

u
15 14 13 12 11 10

o d 9 8

Reserved

-
Reserved

-
Reserved

-
Reserved

- P r ATR2[11:8]

R/W

e t e
Autoreload register2 low (ATR2L)
o l
b s
ATR2L
O Reset value: 0000 0000 (00h)

)-
7 6 5 4 3 2 1 0

t ( s ATR2[7:0]

u c R/W

o d
Pr
Table 45. ATR2H and ATR2L register descriptions
Bit Bit name Function

e t e
15:12 - Reserved, must be kept cleared

s ol Autoreload register 2

O b 11:0 ATR2[11:0]
This is a 12-bit register which is written by software. The ATR2
register value is automatically loaded into the upcounter CNTR2
when an overflow of CNTR2 occurs. The register value is used to set
the PWM2/PWM3 frequency when ENCNTR2 is set.

Dead time generator register (DTGR)

DTGR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

DTE DT[6:0]

R/W R/W

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Table 46. DTGR register description

Bit Bit name Function

Dead time enable

This bit is read/write by software. It enables a dead time generation
7 DTE on PWM0/PWM1.
0: No dead time insertion
1: Dead time insertion enabled
Dead time value
These bits are read/write by software. They define the dead time
6:0 DT[6:0] inserted between PWM0/PWM1. Dead time is calculated as follows:
Dead time = DT[6:0] x Tcounter1

( s )
u ct
o d
P r
e t e
o l
b s
- O
(s )
c t
d u
r o
e P
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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Table 47. Register map and reset values

Add Register
7 6 5 4 3 2 1 0
(Hex.) label

ATCSR ICF ICIE CK1 CK0 OVF1 OVFIE1 CMPIE

0D 0
Reset value 0 0 0 0 0 0 0
CNTR1H CNTR1_11 CNTR1_10 CNTR1_9 CNTR1_8
0E 0 0 0 0
Reset value 0 0 0 0
CNTR1L CNTR1_7 CNTR1_6 CNTR1_5 CNTR1_4 CNTR1_3 CNTR1_2 CNTR1_1 CNTR1_0
0F
Reset value 0 0 0 0 0 0 0 0
ATR1H ATR11 ATR10 ATR9 ATR8
10 0 0 0 0
Reset value 0 0 0 0
ATR1L ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1
( s )
ATR0
11
Reset value 0 0 0 0 0 0 0

c t 0

12
PWMCR
Reset value
0
OE3
0
0
OE2
0
0
OE1
0
d u0
OE0
0
PWM0CSR
r o OP0 CMPF0
13
Reset value
0 0 0 0 0

e P 0
0 0

14
PWM1CSR
Reset value
0 0 0 0

l
0
e t 0
OP1
0
CMPF1
0

15
PWM2CSR
Reset value
0 0 0

b
0
so 0 0
OP2
0
CMPF2
0

16
PWM3CSR
Reset value
0 0 0
- O 0 0 0
OP3
0
CMPF3
0

17
DCR0H
0 0
(s )
0 0
DCR11 DCR10 DCR9 DCR8
Reset value

c t 0 0 0 0

18
DCR0L
Reset value
DCR7
0
d u
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0

19
DCR1H
0r o 0 0 0
DCR11 DCR10 DCR9 DCR8

e P
Reset value 0 0 0 0

let
DCR1L DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
1A
Reset value 0 0 0 0 0 0 0 0

so
DCR2H DCR11 DCR10 DCR9 DCR8
1B 0 0 0 0

O b1C
Reset value
DCR2L
Reset value
DCR7
0
DCR6
0
DCR5
0
DCR4
0 0
0
DCR3
0
DCR2
0
0
DCR1
0
0
DCR0
0
DCR3H DCR11 DCR10 DCR9 DCR8
1D 0 0 0 0
Reset value 0 0 0 0
DCR3L DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
1E
Reset value 0 0 0 0 0 0 0 0
ATICRH ICR11 ICR10 ICR9 ICR8
1F 0 0 0 0
Reset value 0 0 0 0
ATICRL ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
20
Reset value 0 0 0 0 0 0 0 0
ATCSR2 ICS OVFIE2 OVF2 ENCNTR2 TRAN2 TRAN1
21 0 0
Reset value 0 0 0 0 1 1

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Table 47. Register map and reset values (continued)

Add Register
7 6 5 4 3 2 1 0
(Hex.) label

BREAKCR BA BPEN PWM3 PWM2 PWM1 PWM0

22 0 0
Reset value 0 0 0 0 0 0
ATR2H ATR11 ATR10 ATR9 ATR8
23 0 0 0 0
Reset value 0 0 0 0
ATR2L ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
24
Reset value 0 0 0 0 0 0 0 0
DTGR DTE DT6 DT5 DT4 DT3 DT2 DT1 DT0
25
Reset value 0 0 0 0 0 0 0 0

( s )
11.3 Lite timer 2 (LT2)
u ct
11.3.1 Introduction
o d
P r
The lite timer is used for general-purpose timing functions. It is based on two free-running 8-bit
upcounters and an 8-bit input capture register.

e t e
11.3.2 Main features
o l
● Real-time clock (RTC)
b s
–
O
One 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 MHz fOSC)
-
–
)
One 8-bit upcounter with autoreload and programmable timebase period from 4µs to 1.024ms

(s
in 4µs increments (@ 8 MHz fOSC)
–
c t
2 maskable timebase interrupts
● Input capture
d u
–
o
8-bit input capture register (LTICR)
r
–
P
Maskable interrupt with wakeup from halt mode capability

e
l e t
s o
O b

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Figure 47. Lite timer 2 block diagram

fOSC/32
LTTB2
LTCNTR
Interrupt request
LTCSR2
8-bit timebase counter 2
0 0 0 0 0 0 TB2IE TB2F

8
LTARR
fLTIMER
To 12-bit AT timer
8-bit autoreload register

( s )
/2 1

u ct
8-bit timebase counter 1
fLTIMER
0 Timebase

o d
1 or 2 ms
(@ 8 MHz
fOSC)
P r
LTICR
8

e t e
8-bit
o l
LTIC
input capture register

b s
LTCSR1

- O
(s
ICIE
) ICF TB TB1IE TB1F

c t
u
od
LTTB1 interrupt request

P r LTIC interrupt request

e t e
o l
b s
O

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

11.3.3 Functional description

Timebase counter 1
The 8-bit value of counter 1 cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of fOSC/32. An overflow event occurs when the
counter rolls over from F9h to 00h. If fOSC = 8 MHz, then the time period between two
counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR1 register.
When counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is
generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1
register.

Timebase counter 2
( s )
Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR

u ct
register. After an MCU reset, it increments at a frequency of fOSC/32 starting from the value

d
stored in the LTARR register. A counter overflow event occurs when the counter rolls over
o
P r
from FFh to the LTARR reload value. Software can write a new value at anytime in the
LTARR register, this value will be automatically loaded in the counter when the next overflow
occurs.

e t e
o l
When counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an
interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software
reading the LTCSR2 register.
b s
Input capture
- O
(s )
The 8-bit input capture register is used to latch the free-running upcounter (counter 1) 1
after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the

c t
ICF bit is set and the LTICR register contains the value of counter 1. An interrupt is

u
generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.

d
r o
The LTICR is a read-only register and always contains the data from the last input capture.
Input capture is inhibited if the ICF bit is set.

e P
l e t
Figure 48. Input capture timing diagram

s o 4µs
(@ 8 MHz fOSC)

O b fCPU

fOSC/32
Cleared
by S/W
reading
8-bit counter 1 01h 02h 03h 04h 05h 06h 07h LTIC register

LTIC pin

ICF flag

LTICR register xxh 04h 07h

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11.3.4 Low power modes

Table 48. Effect of low power modes on lite timer 2

Mode Description

No effect on lite timer

Slow
(this peripheral is driven directly by fOSC/32)
Wait
No effect on lite timer
Active halt
Halt Lite timer stops counting

Table 49. Lite timer 2 interrupt control/wake-up capability(1)

( s )
ct
Exit from
Interrupt event Event flag Enable control bit Exit from wait Exit from halt

u
active halt

d
Timebase 1 event TB1F TB1IE

r o
Yes
Timebase 2 event
IC event
TB2F
ICF
TB2IE
ICIE
Yes

e P No
No

l e t
1. The TBxF and ICF interrupt events are connected to separate interrupt vectors (see Section 8: Interrupts).

in the CC register is reset (RIM instruction).

s o
They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask

O b
) -
c t (s
d u
r o
e P
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11.3.5 Register description

Lite timer control/status register 2 (LTCSR2)

LTCSR2 Reset value: 0x00 0000 (x0h)

7 6 5 4 3 2 1 0

Reserved Reserved Reserved Reserved Reserved Reserved TB2IE TB2F

- - - - - - R/W R/W

Table 50. LTCSR2 register description

Bit Bit name Function
( s )
7:2 - Reserved, must be kept cleared

u ct
Timebase 2 interrupt enable

o d
1 TB2IE
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabledP r
This bit is set and cleared by software.

Timebase 2 interrupt flag

e t e
l
This bit is set by hardware and cleared by software reading the
o
0 TB2F
s
LTCSR register. Writing to this bit has no effect.

b
0: No counter 2 overflow

O
1: A counter 2 overflow has occurred

-
(s )
Lite timer autoreload register (LTARR)

c t
LTARR
u Reset value: 0000 0000 (00h)

od
7 6 5 4 3 2 1 0

P r AR[7:0]

e
let
R/W

s o Table 51. LTARR register description

Ob Bit Bit name Function

Counter 2 reload value

These bits are read/write by software. The LTARR value is
7:0 AR[7:0]
automatically loaded into counter 2 (LTCNTR) when an overflow
occurs.

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On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Lite timer counter 2 (LTCNTR)

LTCNTR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

CNT[7:0]

Table 52. LTCNTR register description

Bit Bit name Function

Counter 2 reload value

( s )
ct
7:0 CNT[7:0] This register is read by software. The LTARR value is automatically
loaded into counter 2 (LTCNTR) when an overflow occurs.

d u
Lite timer control/status register (LTCSR1)
r o
LTCSR1
e P Reset value: 0x00 0000 (x0h)
7 6 5 4 3
l e t 2 1 0

o
bs
ICIE ICF TB TB1IE TB1F Reserved Reserved Reserved

R/W R/W R/W

- OR/W R/W - - -

Table 53.
s )
LTCSR1 register description
(
Bit Bit name
c t Function

d u Interrupt enable

o
Pr
This bit is set and cleared by software.
7 ICIE
0: Input capture (IC) interrupt disabled
1: Input capture (IC) interrupt enabled

e t e Input capture flag

o l This bit is set by hardware and cleared by software by reading the

b s 6 ICF
LTICR register. Writing to this bit does not change the bit value.
0: No input capture

O 1: An input capture has occurred

Note: After an MCU reset, software must initialize the ICF bit by
reading the LTICR register
Timebase period selection
This bit is set and cleared by software.
5 TB
0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8 MHz)
Timebase interrupt enable
This bit is set and cleared by software.
4 TB1IE
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled

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ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Table 53. LTCSR1 register description (continued)

Bit Bit name Function

Timebase interrupt flag

This bit is set by hardware and cleared by software reading the
3 TB1F LTCSR register. Writing to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
2:0 - Reserved, must be kept cleared

Lite timer input capture register (LTICR)

LTICR
( s )
Reset value: 0000 0000 (00h)
7 6 5 4 3 2

u
1
ct 0

ICR[7:0]

o d
R
P r
Table 54. LTICR register description
e t e
Bit Bit name
o l Function

b s
Input capture value

7:0 ICR[7:0] O
These bits are read by software and cleared by hardware after a

-
reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-

(s )counter is captured when a rising or falling edge occurs on the LTIC

t
pin.

u c
Table 55.
d
Lite timer register map and reset values
o
Address

P
(Hex.) rRegister
label
7 6 5 4 3 2 1 0

e
let
LTCSR2 TB2IE TB2F
08
Reset value 0 0 0 0 0 0 0 0

s o 09
LTARR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

Ob 0A
Reset value
LTCNTR
0
CNT7
0
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
Reset value 0 0 0 0 0 0 0 0
LTCSR1 ICIE ICF TB TB1IE TB1F
0B 0 0 0
Reset value 0 x 0 0 0
LTICR ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
0C
Reset value 0 0 0 0 0 0 0 0

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

11.4 Serial peripheral interface (SPI)

11.4.1 Introduction
The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves or a
system in which devices may be either masters or slaves.

11.4.2 Main features

● Full duplex synchronous transfers (on three lines)
● Simplex synchronous transfers (on two lines)
● Master or slave operation

( s )
ct
● 6 master mode frequencies (fCPU/4 max.)
● fCPU/2 max. slave mode frequency (see note below)
● SS management by software or hardware
d u
● Programmable clock polarity and phase
r o
● End of transfer interrupt flag

e P
Note:
● Write collision, master mode fault and overrun flags

l e t
In slave mode, continuous transmission is not possible at maximum frequency due to the

s o
software overhead for clearing status flags and to initiate the next transmission sequence.

11.4.3 General description

O b
) -
Figure 49: Serial peripheral interface block diagram on page 109 shows the serial peripheral

–
c (s
interface (SPI) block diagram. There are three registers:
t
SPI control register (SPICR)
–
u
SPI control/status register (SPICSR)
d
–
o
SPI data register (SPIDR)
r
P
The SPI is connected to external devices through four pins:

e
let
– MISO: master in/slave out data
– MOSI: master out/slave In data

so
– SCK: Serial clock out by SPI masters and input by SPI slaves

O b – SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master
communicate with slaves individually and to avoid contention on the data lines.
Slave SS inputs can be driven by standard I/O ports on the master device.

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Figure 49. Serial peripheral interface block diagram

Data/address bus

Read
SPIDR

Interrupt request
Read buffer

MOSI

7 SPICSR 0
MISO 8-bit shift register
SPIF WCOL OVR MODF 0 SOD SSM SSI

Write
( s )
ct
SOD
bit 1

d u SS
0
SCK SPI state control

r o
e P
let
7 SPICR 0

so
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Master control

O b
) -
Serial clock generator

SS

c t (s
d u
Functional description
r o
P
A basic example of interconnections between a single master and a single slave is illustrated in

e
l e t
Figure 50: Single master/single slave application on page 110.
The MOSI pins are connected together and the MISO pins are connected together. In this way data are
o
transferred serially between master and slave (most significant bit first).
s
O b
The communication is always initiated by the master. When the master device transmits data to a slave
device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin.
This implies full duplex communication with both data out and data in synchronized with the same clock
signal (which is provided by the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this case only
simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 53: Data clock timing diagram
on page 114) but master and slave must be programmed with the same timing mode.

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Figure 50. Single master/single slave application

Master Slave

MSbit LSbit MSbit LSbit

MISO MISO
8-bit shift register 8-bit shift register

MOSI MOSI

SPI clock SCK SCK

generator
SS SS
+5 V
Not used if SS is managed
by software
( s )
u ct
o d
Slave select management
P r
e te
As an alternative to using the SS pin to control the slave select signal, the application can
choose to manage the slave select signal by software. This is configured by the SSM bit in

o l
the SPICSR register (see Figure 52: Hardware/software slave select management on
page 111).
b s
In software management, the external SS pin is free for other application uses and the

- O
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In master mode:

(s )
–
t
SS internal must be held high continuously
c
In slave mode:
d u
r o
There are two cases depending on the data/clock timing relationship (see Figure 51:
Generic SS timing diagram on page 111):

e P
If CPHA = 1 (data latched on second clock edge):

l e t – SS internal must be held low during the entire transmission. This implies that in

s o single slave applications the SS pin either can be tied to VSS, or made free for
standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in

O b the in the SPICSR register)

If CPHA = 0 (data latched on first clock edge):
– SS internal must be held low during byte transmission and pulled high between
each byte to allow the slave to write to the shift register. If SS is not pulled high, a
write collision error occurs when the slave writes to the shift register (see Write
collision error (WCOL) on page 115).

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Figure 51. Generic SS timing diagram

MOSI/MISO Byte 1 Byte 2 Byte 3

Master SS

Slave SS
(if CPHA = 0)

Slave SS
(if CPHA = 1)

Figure 52. Hardware/software slave select management

( s )
SSM bit

u ct
SSI bit
o d
r
1
SS internal
SS external pin 0

e P
Master mode operation l e t
s o
b
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
O
Note:
-
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
)
(s
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).

t
How to operate the SPI in master mode
c
u
To operate the SPI in master mode, perform the following steps in order:
d
1.
o
Write to the SPICR register:
r
e
–
–P Select the clock frequency by configuring the SPR[2:0] bits.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.

l e t Figure 53: Data clock timing diagram on page 114 shows the four possible
configurations.
o
bs
Note: The slave must have the same CPOL and CPHA settings as the master
2. Write to the SPICSR register:
O – Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: 1 MSTR and SPE bits remain set only if SS is high).
2 If the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not
taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.

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Master mode transmit sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A read to the SPIDR register
Note:
s )
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
(
ct
register is read.

Slave mode operation

d u
r o
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
e P
1.
–
l e t
Write to the SPICSR register to perform the following actions:
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits

s o
(see Figure 53: Data clock timing diagram on page 114).
Note:
– O b
The slave must have the same CPOL and CPHA settings as the master.
Manage the SS pin as described in Slave select management on page 110 and

) -
Figure 51: Generic SS timing diagram on page 111. If CPHA = 1 SS must be held

(s
low continuously. If CPHA = 0 SS must be held low during byte transmission and

t
pulled up between each byte to let the slave write in the shift register.
c
2.
u
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI

d
I/O functions.

r o
P
Slave mode transmit sequence

e
l e t
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.

s o The transmit sequence begins when the slave device receives the clock signal and the most

O b significant bit of the data on its MOSI pin.

When data transfer is complete:
– The SPIF bit is set by hardware.
– An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A write or a read to the SPIDR register

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Note: 1 While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
2 The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an overrun condition (see Overrun condition
(OVR) on page 115).

11.4.4 Clock phase and clock polarity

Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (see Figure 53: Data clock timing diagram on page 114).
Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).

s
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
( )
ct
capture clock edge.

d u
Figure 53: Data clock timing diagram on page 114 shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or

r o
slave timing diagram where the SCK pin, the MISO pin and the MOSI pin are directly
connected between the master and the slave device.

e P
Note:
resetting the SPE bit.
l e t
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by

s o
O b
) -
c t (s
d u
r o
e P
l e t
s o
O b

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Figure 53. Data clock timing diagram

CPHA = 1

SCK
(CPOL = 1)

SCK
(CPOL = 0)

MISO
(from master) MSbit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSbit

MOSI
MSbit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSbit
(from slave)

( s )
SS
(to slave)

u ct
o d
Capture strobe

CPHA = 0 P r
e t e
l
SCK
(CPOL = 1)

s o
SCK
(CPOL = 0)
O b
) -
(s
MISO
(from master) MSbit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSbit

c t
MOSI
u
od
(from slave) MSbit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSbit

SS
(to slave)
P r
e t e
o l
Capture strobe

b s
O1. This figure should not be used as a replacement for parametric information. Refer to Section 13: Electrical characteristics.

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11.4.5 Error flags

Master mode fault (MODF)
Master mode fault occurs when the master device’s SS pin is pulled low.
When a master mode fault occurs:
– The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is
set.
– The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
– The MSTR bit is reset, thus forcing the device into slave mode.
Clearing the MODF bit is done through a software sequence:
1. A read access to the SPICSR register while the MODF bit is set.
( s )
2. A write to the SPICR register.

u ct
Note: 1
d
To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high

o
during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their
original state during or after this clearing sequence.
P r
2
except in the MODF bit clearing sequence.
e t e
Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set

3
o l
In a slave device, the MODF bit can not be set, but in a multimaster configuration the device

4
can be in slave mode with the MODF bit set.
b s
The MODF bit indicates that there might have been a multimaster conflict and allows
O
software to handle this using an interrupt routine and either perform a reset or return to an
-
application default state.

(s )
Overrun condition (OVR)
c t
d u
An overrun condition occurs when the master device has sent a data byte and the slave
device has not cleared the SPIF bit issued from the previously transmitted byte.

r o
When an overrun occurs:
●
e P
The OVR bit is set and an interrupt request is generated if the SPIE bit is set.

l e t
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A

s o read to the SPIDR register returns this byte. All other bytes are lost.

O b The OVR bit is cleared by reading the SPICSR register.

Write collision error (WCOL)

A write collision occurs when the software tries to write to the SPIDR register while a data
transfer is taking place with an external device. When this happens, the transfer continues
uninterrupted and the software write will be unsuccessful.
Write collisions can occur both in master and slave mode. See also Slave select
management on page 110.
Note: A ‘read collision’ will never occur since the received data byte is placed in a buffer in which
access is always synchronous with the CPU operation.
The WCOL bit in the SPICSR register is set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

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Clearing the WCOL bit is done through a software sequence (see Figure 54).

Figure 54. Clearing the WCOL bit (write collision flag) software sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st step Read SPICSR

Result
SPIF = 0
2nd step Read SPIDR
WCOL = 0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st step Read SPICSR

( s )
ct
Result

Read SPIDR WCOL = 0

u
2nd step

1. Writing to the SPIDR register instead of reading it does not reset the WCOL bit.
o d
Single master and multimaster configurations
P r
There are two types of SPI systems:
e t e
● Single master system
o l
● Multimaster system
Single Master System b s
- O
A typical single master system may be configured using a device as the master and four
)
devices as slaves (see Figure 55: Single master/multiple slave configuration on page 117).

(s
t
The master device selects the individual slave devices by using four pins of a parallel port to
c
d u
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to be

r o
inputs at that time, thus disabling the slave devices.
Note: P
To prevent a bus conflict on the MISO line, the master allows only one active slave device
e
l e t
during a transmission.

s o For more security, the slave device may respond to the master with the received data byte.
Then the master will receive the previous byte back from the slave device if all MISO and

O b MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Multimaster system
A multimaster system may also be configured by the user. Transfer of master control could
be implemented using a handshake method through the I/O ports or by an exchange of
code messages through the serial peripheral interface system.
The multimaster system is principally handled by the MSTR bit in the SPICR register and
the MODF bit in the SPICSR register.

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Figure 55. Single master/multiple slave configuration

SS SS SS SS
SCK SCK SCK SCK

Slave device Slave device Slave device Slave device

MOSI MISO MOSI MISO MOSI MISO MOSI MISO

MOSI

SCK
MISO

( s )
ct
Ports

Master
device

d u
5V SS

r o
e P
11.4.6 Low power modes
l e t
Table 56. Effect of low power modes on SPI
s o
Mode

O b Description

Wait
No effect on SPI

) -
SPI interrupt events cause the device to exit from wait mode.

c t (s
SPI registers are frozen
In halt mode, the SPI is inactive. SPI operation resumes when the device is

Halt
d u
woken up by an interrupt with ‘exit from Halt mode’ capability. The data received
is subsequently read from the SPIDR register when the software is running

r o (interrupt vector fetching). If several data are received before the wakeup event,
then an overrun error is generated. This error can be detected after the fetch of

e P the interrupt routine that woke up the device.

l e t
Using the SPI to wake up the device from halt mode

s o
O b In slave configuration, the SPI is able to wake up the device from halt mode through a SPIF
interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from halt mode, if the SPI remains in slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from halt mode state to normal
state. If the SPI exits from slave mode, it returns to normal state immediately.
Caution: The SPI can wake up the device from halt mode only if the slave select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the device enters halt mode. So, if
slave selection is configured as external (see Slave select management on page 110), make
sure the master drives a low level on the SS pin when the slave enters halt mode.

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11.4.7 Interrupts

Table 57. SPI interrupt control/wake-up capability(1)

Interrupt event Event flag Enable control bit Exit from wait Exit from halt

SPI end of transfer event SPIF Yes

Master mode fault event MODF SPIE Yes
No
Overrun error OVR
1. The SPI interrupt events are connected to the same interrupt vector (see Section 8: Interrupts). They
generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the CC register
is reset (RIM instruction).

11.4.8 Register description

( s )
SPI control register (SPICR)
u ct
o d
SPICR
7 6 5 4 3
P r 2
Reset value: 0000 xxxx (0xh)
1 0

e
let
SPIE SPE SPR2 MSTR CPOL CPHA SPR[1:0]

so
R/W R/W R/W R/W R/W R/W R/W

Table 58. SPICR register description

O b
Bit Bit name
) - Function

ct (s
Serial peripheral interrupt enable
This bit is set and cleared by software.
7
d uSPIE 0: Interrupt is inhibited

r o 1: An SPI interrupt is generated whenever an end of transfer

event, master mode fault or overrun error occurs (SPIF = 1,

e P MODF = 1 or OVR = 1 in the SPICSR register)

let
Serial peripheral output enable
This bit is set and cleared by software. It is also cleared by hardware

s o 6 SPE
when, in master mode, SS = 0 (see Master mode fault (MODF) on
page 115). The SPE bit is cleared by reset, so the SPI peripheral is

Ob not initially connected to the external pins.

0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Divider enable
This bit is set and cleared by software and is cleared by reset. It is
used with the SPR[1:0] bits to set the baud rate (see bits [1:0]
5 SPR2 below).
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: The SPR2 bit has no effect in slave mode

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Table 58. SPICR register description (continued)

Bit Bit name Function

Master mode
This bit is set and cleared by software. It is also cleared by hardware
when, in master mode, SS = 0 (see Master mode fault (MODF) on
4 MSTR page 115).
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input
to an output and the functions of the MISO and MOSI pins are
reversed.
Clock polarity
This bit is set and cleared by software. This bit determines the idle

s )
state of the serial clock. The CPOL bit affects both the master and

(
ct
slave modes.
3 CPOL
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state

d u
Note: If CPOL is changed at the communication byte boundaries, the

r o
SPI must be disabled by resetting the SPE bit.
Clock phase

e P
2 CPHA
l t
This bit is set and cleared by software.

e
0: The first clock transition is the first data capture edge

s o
1: The second clock transition is the first capture edge
Note: The slave must have the same CPOL and CPHA settings as the
master.

O b
) -
Serial clock frequency
These bits are set and cleared by software. Used with the SPR2 bit,

c t (s they select the baud rate of the SPI serial clock SCK output by the
SPI in master mode:

1:0
d u
SPR[1:0]
100: serial clock = fCPU/4
000: serial clock = fCPU/8

r o 001: serial clock = fCPU/16

110: serial clock = fCPU/32

e P 010: serial clock = fCPU/64

011: serial clock = fCPU/128

l e t Note: These 2 bits have no effect in slave mode.

s o
O b

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SPI control/status register (SPICSR)

SPICSR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

SPIF WCOL OVR MODF Reserved SOD SSM SSI

R R R R - R/W R/W R/W

Table 59. SPICSR register description

Bit Bit name Function

Serial peripheral data transfer flag

( s )
ct
This bit is set by hardware when a transfer has been completed. An
interrupt is generated if SPIE = 1 in the SPICR register. It is cleared

by a write or a read to the SPIDR register).

d u
by a software sequence (an access to the SPICSR register followed
7 SPIF
r o
0: Data transfer is in progress or the flag has been cleared

completed
e P
1: Data transfer between the device and an external device has been

l e t
Note: While the SPIF bit is set, all writes to the SPIDR register are
inhibited until the SPICSR register is read.

s
Write collision status o
O b
This bit is set by hardware when a write to the SPIDR register is
made during a transmit sequence. It is cleared by a software
6 WCOL
-
sequence (see Figure 54: Clearing the WCOL bit (write collision flag)

)
software sequence on page 116).

c t (s 0: No write collision occurred

1: A write collision has been detected

d u SPI overrun error

r o This bit is set by hardware when the byte currently being received in
the shift register is ready to be transferred into the SPIDR register

e P5 OVR while SPIF = 1 (see Overrun condition (OVR) on page 115). An

interrupt is generated if SPIE = 1 in SPICR register. The OVR bit is

l e t cleared by software reading the SPICSR register.

0: No overrun error

s o 1: Overrun error detected

O b Mode fault flag

This bit is set by hardware when the SS pin is pulled low in master
mode (see Master mode fault (MODF) on page 115). An SPI
interrupt can be generated if SPIE = 1 in the SPICR register. This bit
4 MODF
is cleared by a software sequence (an access to the SPICSR
register while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
3 - Reserved, must be kept cleared.

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Table 59. SPICSR register description (continued)

Bit Bit name Function

SPI output disable

This bit is set and cleared by software. When set, it disables the
alternate function of the SPI output (MOSI in master mode/MISO in
2 SOD
slave mode).
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
SS management
This bit is set and cleared by software. When set, it disables the
alternate function of the SPI SS pin and uses the SSI bit value
1 SSM instead. See Slave select management on page 110.
0: Hardware management (SS managed by external pin)

( s )
ct
1: Software management (internal SS signal controlled by SSI bit.
External SS pin free for general-purpose I/O)
SS internal mode
d u
r o
This bit is set and cleared by software. It acts as a ‘chip select’ by
controlling the level of the SS slave select signal when the SSM bit is
0 SSI
set.

e P
0 : Slave selected
1 : Slave deselected
l e t
s o
SPI data I/O register (SPIDR)

O b
)-
SPIDR Reset value: undefined
7 6
t (
5
s 4 3 2 1 0

u c D[7:0]

o d R/W

P r
The SPIDR register is used to transmit and receive data on the serial bus. In a master

te
device, a write to this register initiates transmission/reception of another byte.
e
Note:
o
1 l During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift

b s register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.

O 2 While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.

Warning: A write to the SPIDR register places data directly into the
shift register for transmission.

A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see Figure 49: Serial peripheral interface block diagram on page 109).

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Table 60. SPI register map and reset values

Address (Hex.) Register label 7 6 5 4 3 2 1 0

SPIDR MSB LSB

0031h
Reset Value x x x x x x x x
SPICR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0032h
Reset Value 0 0 0 0 x x x x
SPICSR SPIF WCOL OVR MODF SOD SSM SSI
0033h
Reset Value 0 0 0 0 0 0 0 0

11.5 LINSCI serial communication interface (LIN master/slave)

( s )
11.5.1 Introduction
u ct
o d
The serial communications interface (SCI) offers a flexible means of full-duplex data
exchange with external equipment requiring an industry standard NRZ asynchronous serial

systems. P r
data format. The SCI offers a very wide range of baud rates using two baud rate generator

te
The LIN-dedicated features support the LIN (local interconnect network) protocol for both
e
master and slave nodes.
o l
b s
This chapter is divided into SCI Mode and LIN mode sections. For information on general
SCI communications, refer to the SCI mode section. For LIN applications, refer to both the
SCI mode and LIN mode sections.
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

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11.5.2 SCI features

● Full duplex, asynchronous communications
● NRZ standard format (mark/space)
● Independently programmable transmit and receive baud rates up to 500 K baud
● Programmable data word length (8 or 9 bits)
● Receive buffer full, transmit buffer empty and end of transmission flags
● 2 receiver wake-up modes:
– Address bit (MSB)
– Idle line
● Muting function for multiprocessor configurations
● Separate enable bits for transmitter and receiver

( s )
ct
● Overrun, noise and frame error detection
● 6 interrupt sources
– Transmit data register empty
d u
– Transmission complete
r o
– Receive data register full
e P
–
–
Idle line received
Overrun error
l e t
– Parity interrupt
s o
● Parity control:
O b
–
–
Transmits parity bit

) -
Checks parity of received data byte
●
t (s
Reduced power consumption mode

c
11.5.3 LIN features
d u
●
r o
LIN master

e
–
P 13-bit LIN synch break generation

let
● LIN slave
– Automatic header handling

s o – Automatic baud rate resynchronization based on recognition and measurement of

Ob –
the LIN synch field (for LIN slave nodes)
Automatic baud rate adjustment (at CPU frequency precision)
– 11-bit LIN synch break detection capability
– LIN Parity check on the LIN identifier field (only in reception)
– LIN error management
– LIN header timeout
– Hot plugging support

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

11.5.4 General description

The interface is externally connected to another device by two pins:
● TDO: Transmit data output. When the transmitter is disabled, the output pin returns to
its I/O port configuration. When the transmitter is enabled and nothing is to be
transmitted, the TDO pin is at high level.
● RDI: Receive data input is the serial data input. Oversampling techniques are used for
data recovery by discriminating between valid incoming data and noise.
Through these pins, serial data is transmitted and received as characters comprising:
● An Idle line prior to transmission or reception
● A start bit
●
●
A data word (8 or 9 bits) least significant bit first
A stop bit indicating that the character is complete
( s )
This interface uses three types of baud rate generator:
u ct
● A conventional type for commonly-used baud rates

o d
●
r
An extended type with a prescaler offering a very wide range of baud rates even with
non-standard oscillator frequencies
P
●
e
A LIN baud rate generator with automatic resynchronization

e t
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Figure 56. SCI block diagram (in conventional baud rate generator mode)

Write Read (Data register) SCIDR

Transmit data register (TDR) Received data register (RDR)

TDO

Transmit shift register Receive Shift Register

RDI
SCICR1
SC WA
R8 T8 M PCE PS PIE

)
ID KE

( s
u ct
Transmit control
Wake up
unit Receiver control

o d Receiver clock

SCICR2 P r SCISR

e
let
TIE TC
IE RIE ILIE TE RE RW SBK TD TC RD ID OR NF FE PE
U RE RF LE LHE

s o
SCI interrupt control

O b
Transmitter clock

) -
t ( s Transmitter rate

c
control

du
fCPU /16 /PR
SCIBRR

r o SC SC SC SC
P1 P0 T2 T1
SC
T0
SC SC SC
R2 R1 R0

e P
l e t Receiver rate
control

so
Conventional baud rate generator

O b
11.5.5 SCI mode - functional description
Conventional baud rate generator mode
The block diagram of the serial control interface in conventional baud rate generator mode is
shown in Figure 56.
It uses four registers:
● 2 control registers (SCICR1 and SCICR2)
● A status register (SCISR)
● A baud rate register (SCIBRR)

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Extended prescaler mode

Two additional prescalers are available in extended prescaler mode. They are shown in
Figure 58: SCI baud rate and extended prescaler block diagram on page 131.
● An extended prescaler receiver register (SCIERPR)
● An extended prescaler transmitter register (SCIETPR)

Serial data format

Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see Figure 57).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.

( s )
ct
An idle character is interpreted as a continuous logic high level for 10 (or 11) full bit times.
A break character is a character with a sufficient number of low level bits to break the normal
data format followed by an extra “1” bit to acknowledge the start bit.
d u
r o
Figure 57. Word length programming

e P
9-bit word length (M bit is set)

l e t
Data character

s o Possible
parity bit Next
Next data character
Start
bit Bit0 Bit1 Bit2 Bit3
b
Bit4

O
Bit5 Bit6 Bit7 Bit8 Stop
bit
start
bit

)- Idle line Start

Bit

t ( s
u c Break character Extra
’1’
Start
bit

o d
P r 8-bit word length (M bit is reset)
Possible

e t e Start
Data character parity bit Next
start
Next data character

l
Stop
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 bit
bit

s o
O b Idle line Start
bit

Start
Extra bit
Break character
’1’

Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.

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Character transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this
mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 56).
Procedure
● Select the M bit to define the word length.
● Select the desired baud rate using the SCIBRR and the SCIETPR registers.
● Set the TE bit to send a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones (idle
line) as first transmission.
● Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
( s )
1.
2.
An access to the SCISR register
A write to the SCIDR register
u ct
o d
The TDRE bit is set by hardware and it indicates:
● The TDR register is empty
P r
● The data transfer is beginning

e t e
●
l
The next data can be written in the SCIDR register without overwriting the previous
data
o
b s
This flag generates an interrupt if the TIE bit is set and the I[|1:0] bits are cleared in the CCR
register.

- O
When a transmission is taking place, a write instruction to the SCIDR register stores the

(s )
data in the TDR register and which is copied in the shift register at the end of the current
transmission.
c t
d u
When no transmission is taking place, a write instruction to the SCIDR register places the
data directly in the shift register, the data transmission starts, and the TDRE bit is

r o
immediately set.

P
When a character transmission is complete (after the stop bit) the TC bit is set and an
e
l e t
interrupt is generated if the TCIE is set and the I[1:0] bits are cleared in the CCR register.
Clearing the TC bit is performed by the following software sequence:
o
bs
1. An access to the SCISR register
2. A write to the SCIDR register
O
Note: The TDRE and TC bits are cleared by the same software sequence.
Break characters
Setting the SBK bit loads the shift register with a break character. The break character
length depends on the M bit (see Figure 57: Word length programming on page 126).
As long as the SBK bit is set, the SCI sends break characters to the TDO pin. After clearing
this bit by software, the SCI inserts a logic 1 bit at the end of the last break character to
guarantee the recognition of the start bit of the next character.
Idle line
Setting the TE bit drives the SCI to send a preamble of 10 (M = 0) or 11 (M = 1) consecutive
‘1’s (idle line) before the first character.

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

In this case, clearing and then setting the TE bit during a transmission sends a preamble
(idle line) after the current word. Note that the preamble duration (10 or 11 consecutive ‘1’s
depending on the M bit) does not take into account the stop bit of the previous character.
Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte
in the SCIDR.

Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9
bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception

s )
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this

(
ct
mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the
received shift register (see Figure 56: SCI block diagram (in conventional baud rate
generator mode) on page 125).
d u
Procedure
r o
●
●
Select the M bit to define the word length.

e P
Select the desired baud rate using the SCIBRR and the SCIERPR registers.
●
l e t
Set the RE bit, this enables the receiver which begins searching for a start bit.
When a character is received:
s o
●
b
The RDRF bit is set. It indicates that the content of the shift register is transferred to the
RDR
O
●
-
An interrupt is generated if the RIE bit is set and the I[1:0] bits are cleared in the CCR
)
(s
register
●
t
The error flags can be set if a frame error, noise or an overrun error has been detected
c
during reception

d u
Clearing the RDRF bit is performed by the following software sequence done by:
1.
r o
An access to the SCISR register
2.
e P
A read to the SCIDR register

l e t
The RDRF bit must be cleared before the end of the reception of the next character to avoid

s o an overrun error.

O b Idle line
When an idle line is detected, there is the same procedure as a data received character plus
an interrupt if the ILIE bit is set and the I[|1:0] bits are cleared in the CCR register.
Overrun error
An overrun error occurs when a character is received when RDRF has not been reset. Data
can not be transferred from the shift register to the TDR register as long as the RDRF bit is
not cleared.

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When an overrun error occurs:

● The OR bit is set
● The RDR content will not be lost
● The shift register will be overwritten
● An interrupt is generated if the RIE bit is set and the I[|1:0] bits are cleared in the CCR
register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise.

( s )
ct
When noise is detected in a character:
● The NF bit is set at the rising edge of the RDRF bit
● Data is transferred from the Shift register to the SCIDR register
d u
●
r o
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt

e P
operation.
l e t
The NF bit is reset by a SCISR register read operation followed by a SCIDR register read

Framing error
s o
A framing error is detected when:
O b
●
-
The stop bit is not recognized on reception at the expected time, following either a

)
desynchronization or excessive noise.
● A break is received

c t (s
When the framing error is detected:
●
d u
the FE bit is set by hardware
●
r o
Data is transferred from the shift register to the SCIDR register
●

e P
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.

l e t
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read

s o operation.

O b Break character
When a break character is received, the SCI handles it as a framing error. To differentiate a
break character from a framing error, it is necessary to read the SCIDR. If the received value
is 00h, it is a break character. Otherwise it is a framing error.

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Conventional baud rate generation

The baud rates for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
fCPU fCPU
Tx = Rx =
(16*PR)*TR (16*PR)*RR

where:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits)
All these bits are in the Baud rate register (SCIBRR) on page 139.
( s )
ct
Example: If fCPU is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and
u
receive baud rates are 38400 baud.

o d
Note:
r
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
P
Extended baud rate generation
e t e
o l
The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value

compatibility. b s
prescaler, whereas the conventional baud rate generator retains industry standard software

- O
The extended baud rate generator block diagram is described in Figure 58: SCI baud rate
)
and extended prescaler block diagram on page 131.

(s
c t
The output clock rate sent to the transmitter or to the receiver will be the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
d u
Note:
r o
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value

P
other than zero.

e
l e t
The baud rates are calculated as follows:

s o Tx =
fCPU
Rx =
fCPU

16*ERPR*(PR*RR)

O b where:
16*ETPR*(PR*TR)

ETPR = 1, ..., 255 (see SCIETPR register on page 140)

ERPR = 1, ..., 255 (see SCIERPR register on page 140)

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Figure 58. SCI baud rate and extended prescaler block diagram

Transmitter clock
Extended prescaler transmitter rate control

SCIETPR

Extended transmitter prescaler register

SCIERPR

Extended receiver prescaler register

( s
Receiver clock )
ct
Extended prescaler receiver rate control

Extended prescaler

d u
ro
e P
l e t
s o
O b
) -
fCPU
c t (s
d u
r o Transmitter rate control

/16

e P /PR

let
SCIBRR

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

s o
Ob Receiver rate control

Conventional baud rate generator

Receiver muting and wake-up feature

In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI
service overhead for all non-addressed receivers.
The non-addressed devices may be placed in sleep mode by means of the muting function.

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Setting the RWU bit by software puts the SCI in sleep mode:
All the reception status bits cannot be set.
All the receive interrupts are inhibited.
A muted receiver may be woken up in one of the following ways:
● by idle line detection if the WAKE bit is reset,
● by address mark detection if the WAKE bit is set.
Idle line detection
The receiver wakes up by idle line detection when the receive line has recognized an idle
line. Then the RWU bit is reset by hardware but the IDLE bit is not set.
This feature is useful in a multiprocessor system when the first characters of the message
determine the address and when each message ends by an idle line: As soon as the line
( s )
ct
becomes idle, every receiver is awakened and the first characters of the message are
analysed which indicates the addressed receiver. The receivers which are not addressed

d u
set the RWU bit to enter in mute mode. Consequently, they will not read the next characters
constituting the next part of the message. At the end of the message, an idle line is sent by

r o
the transmitter: this wakes up every receiver which are ready to analyse the addressing
characters of the new message.

e P
Address mark detection
l e t
In such a system, the inter-characters space must be smaller than the idle time.

s o
The receiver wakes up by address mark detection when it receives a ‘1’ as the most

O b
significant bit of a word, thus indicating that the message is an address. The reception of
this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which
-
allows the receiver to receive this word normally and to use it as an address word.
)
t (s
This feature is useful in a multiprocessor system when the most significant bit of each
character (except for the break character) is reserved for address detection. As soon as the
c
d u
receivers receive an address character (most significant bit = ’1’), the receivers are woken
up. The receivers which are not addressed set RWU bit to enter in mute mode.

message. r o
Consequently, they will not treat the next characters constituting the next part of the

e P
l e t
Parity control
Hardware byte parity control (generation of parity bit in transmission and parity checking in

s o reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the

O b character format defined by the M bit, the possible SCI character formats are as listed in
Table 61.
Note: In case of wake-up by an address mark, the MSB bit of the data is taken into account and
not the parity bit

Table 61. Character formats(1)

M bit PCE bit Character format
0 | SB | 8 bit data | STB |
0
1 | SB | 7-bit data | PB | STB |
0 | SB | 9-bit data | STB |
1
1 | SB | 8-bit data | PB | STB |
1. Legend: SB = start bit, STB = stop bit, PB = parity bit

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Even parity
The parity bit is calculated to obtain an even number of ‘1s’ inside the character made of the
7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit will be 0 if even parity is selected
(PS bit = 0).
Odd parity
The parity bit is calculated to obtain an odd number of ‘1s’ inside the character made of the
7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit will be 1 if odd parity is selected
(PS bit = 1).
Transmission mode

( s )
ct
If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted
but is changed by the parity bit.

d u
Reception mode
r o
P
If the PCE bit is set then the interface checks if the received data byte has an even number
of ‘1s’ if even parity is selected (PS = 0) or an odd number of ‘1s’ if odd parity is selected
e
generated if PCIE is set in the SCICR1 register.
l e t
(PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is

s o
11.5.6 Low power modes
O b
Table 62.
-
Effect of low power modes on SCI

)
(s
Mode Description

c t
No effect on SCI
Wait

d u
SCI interrupts cause the device to exit from wait mode

r o SCI registers are frozen

Halt

e P In halt mode, the SCI stops transmitting/receiving until halt mode is

exited

l e t
s o
11.5.7 Interrupts

O b Table 63. SCI interrupt control/wake-up capability

Interrupt event Event flag Enable control bit Exit from wait Exit from halt

Transmit data register empty TDRE TIE

Transmission complete TC TCIE
Received data ready to be read RDRF
Overrun error or LIN synch RIE
OR/LHE Yes No
error detected
Idle line detected IDLE ILIE
Parity error PE PIE
LIN header detection LHDF LHIE

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

The SCI interrupt events are connected to the same interrupt vector (see Section 8:
Interrupts).
These events generate an interrupt if the corresponding enable control bit is set and the
interrupt mask in the CC register is reset (RIM instruction).

11.5.8 SCI mode registers

Status register (SCISR)

SCISR Reset value: 1100 0000 (C0h)

7 6 5 4 3 2 1 0

TDRE TC RDRF IDLE OR(1) NF(1) FE(1)

( s )
PE(1)

R R R R R R

u
R
ct R

d
1. This bit has a different function in LIN mode, please refer to the LIN mode register description

o
Table 64. SCISR register description
P r
Bit Bit name

e t e
Function

Transmit data register empty

o l
b s
This bit is set by hardware when the content of the TDR register has
been transferred into the shift register. An interrupt is generated if the
7 TDRE

- O
TIE bit = 1 in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register followed by a write to the

(s )
SCIDR register).
0: Data is not transferred to the shift register

c t 1: Data is transferred to the shift register

d u Transmission complete
This bit is set by hardware when transmission of a character

r o containing data is complete. An interrupt is generated if TCIE = 1 in

e P6 TC
the SCICR2 register. It is cleared by a software sequence (an access
to the SCISR register followed by a write to the SCIDR register).

l e t 0: Transmission is not complete

1: Transmission is complete

s o Note: TC is not set after the transmission of a preamble or a break.

O b Received data ready flag

This bit is set by hardware when the content of the RDR register has
been transferred to the SCIDR register. An interrupt is generated if
5 RDRF RIE = 1 in the SCICR2 register. It is cleared by a software sequence
(an access to the SCISR register followed by a read to the SCIDR
register).
0: Data are not received
1: Received data are ready to be read

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Table 64. SCISR register description (continued)

Bit Bit name Function

Idle line detect

This bit is set by hardware when an idle line is detected. An interrupt
is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR register followed by a
4 IDLE read to the SCIDR register).
0: No idle line is detected
1: Idle line is detected
Note: The IDLE bit is not set again until the RDRF bit is set (i.e. a new
idle line occurs).
Overrun error

s )
This bit is set by hardware when the word currently being received in
(
ct
the shift register is ready to be transferred into the RDR register
while RDRF = 1. An interrupt is generated if RIE = 1 in the SCICR2
3 OR u
register. It is cleared by a software sequence (an access to the
d
SCISR register followed by a read to the SCIDR register).
0: No overrun error
r o
1: Overrun error is detected

e P
Note: When the IDLE bit is set the RDR register content is not lost but

l e t
the shift register is overwritten.
Noise flag

s o
This bit is set by hardware when noise is detected on a received

O b
character. It is cleared by a software sequence (an access to the
SCISR register followed by a read to the SCIDR register).
2 NF
-
0: No noise is detected

)
1: Noise is detected

c t (s
Note: The NF bit does not generate an interrupt as it appears at the
same time as the RDRF bit which itself generates an interrupt.

u
od
Framing error
This bit is set by hardware when a de-synchronization, excessive

P r noise or a break character is detected. It is cleared by a software

sequence (an access to the SCISR register followed by a read to the

e t e 1 FE
SCIDR register).
0: No framing error is detected

o l 1: Framing error or break character is detected

b s Note: The FE bit does not generate an interrupt as it appears at the

same time as the RDRF bit which itself generates an interrupt.

O If the word currently being transferred causes both frame error

and overrun error, it is transferred and only the OR bit is set.
Parity error
This bit is set by hardware when a parity error occurs (if the PCE bit
is set) in receiver mode. It is cleared by a software sequence (a read
0 PE to the status register followed by an access to the SCIDR data
register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Control register 1 (SCICR1)

SCICR1 Reset value: x000 0000 (x0h)

7 6 5 4 3 2 1 0

R8 T8 SCID M WAKE PCE(1) PS PIE

R/W R/W R/W R/W R/W R/W R/W R/W

1. This bit has a different function in LIN mode, please refer to the LIN mode register description

Table 65. SCICR1 register description

Bit Bit name Function

( s )
ct
Receive data bit 8
7 R8
This bit is used to store the 9th bit of the received word when M = 1.
Transmit data bit 8
d u
6 T8
r o
This bit is used to store the 9th bit of the transmitted word when
M = 1.

e P
e t
Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped at
l
5 SCID
s o
the end of the current byte transfer in order to reduce power
consumption.This bit is set and cleared by software.
0: SCI enabled

O b
1: SCI prescaler and outputs disabled

-
Word length
)
(s
This bit determines the word length. It is set or cleared by software.
4 M
c t 0: 1 Start bit, 8 data bits, 1 stop bit
1: 1 Start bit, 9 data bits, 1 stop bit

d u Note: The M bit must not be modified during a data transfer (both

r o transmission and reception).

e P Wake up method
This bit determines the SCI wake up method, it is set or cleared by

l e t 3 WAKE
software.
0: Idle line

s o 1: Address mark
Note: If the LINE bit is set, the WAKE bit is deactivated and replaced

O b by the LHDM bit.

Parity control enable
This bit is set and cleared by software. It selects the hardware parity
control (generation and detection for byte parity, detection only for
2 PCE
LIN parity).
0: Parity control disabled
1: Parity control enabled

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Table 65. SCICR1 register description (continued)

Bit Bit name Function

Parity selection
This bit selects the odd or even parity when the parity
generation/detection is enabled (PCE bit set). It is set and cleared by
1 PS
software. The parity is selected after the current byte.
0: Even parity
1: Odd parity
Parity interrupt enable
This bit enables the interrupt capability of the hardware parity control
when a parity error is detected (PE bit set). The parity error involved
0 PIE can be a byte parity error (if bit PCE is set and bit LPE is reset) or a
LIN parity error (if bit PCE is set and bit LPE is set).

( s )
ct
0: Parity error interrupt disabled
1: Parity error interrupt enabled

d u
Control register 2 (SCICR2)
r o
e P
SCICR2
7 6 5 4
l3
e t 2
Reset value: 0000 0000 (00h)
1 0

TIE TCIE RIE ILIE

s o TE RE RWU (1) SBK(1)

R/W R/W R/W

O b
R/W R/W R/W R/W R/W

-
1. This bit has a different function in LIN mode, please refer to the LIN mode register description
)
Table 66.
c t (s
SCICR2 register description
Bit
d u
Bit name Function

r o Transmitter interrupt enable

e P7 TIE
This bit is set and cleared by software.
0: Interrupt is inhibited

l e t 1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR

register

o
bs
Transmission complete interrupt enable
This bit is set and cleared by software.

O 6 TCIE 0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TC = 1 in the SCISR
register
Receiver interrupt enable
This bit is set and cleared by software.
5 RIE 0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in
the SCISR register
Idle line interrupt enable
This bit is set and cleared by software.
4 ILIE 0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR
register

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Table 66. SCICR2 register description (continued)

Bit Bit name Function

Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
3 TE
Note: During transmission, an ‘0’ pulse on the TE bit (‘0’ followed by
‘1’) sends a preamble (idle line) after the current word.
When TE is set there is a 1 bit-time delay before the
transmission starts.
Receiver enable
2 RE This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled in the SCISR register
( s )
ct
1: Receiver is enabled and begins searching for a start bit
Receiver wake up

d u
This bit determines if the SCI is in mute mode or not. It is set and

r o
cleared by software and can be cleared by hardware when a wake
up sequence is recognized.
0: Receiver in active mode
e P
1 RWU
1: Receiver in mute mode

l e t
Note: Before selecting mute mode (by setting the RWU bit), the SCI

s o
must first receive a data byte, otherwise it cannot function in
mute mode with wakeup by idle line detection.

O b
In address mark detection wake up configuration (WAKE bit =
1) the RWU bit cannot be modified by software while the RDRF

) - bit is set.

c t (sSend break
This bit set is used to send break characters. It is set and cleared by

u software.

od
0 SBK 0: No break character is transmitted

P r 1: Break characters are transmitted

Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter sends a
BREAK word at the end of the current word.

e t e
o l Data register (SCIDR)

b s Contains the received or transmitted data character, depending on whether it is read from or

O written to.

SCIDR Reset value: undefined

7 6 5 4 3 2 1 0

DR[7:0]

R/W

The data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).

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The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 56: SCI block diagram (in conventional baud rate generator mode)
on page 125).
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 56).

Baud rate register (SCIBRR)

SCIBRR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

SCP[1:0] SCT[2:0] SCR[2:0]

R/W R/W R/W

( s )
u ct
Note:
d
When LIN slave mode is disabled, the SCIBRR register controls the conventional baud rate
generator.
o
Table 67. SCIBRR register description P r
Bit Bit name
e t e
Function

First SCI prescaler

o l
b s
These 2 prescaling bits allow several standard clock division ranges:
00: PR prescaling factor = 1
7:6 SCP[1:0]
O
01: PR prescaling factor = 3
-
10: PR prescaling factor = 4

(s )
11: PR prescaling factor = 13

ct
SCI transmitter rate divisor

d u These 3 bits, in conjunction with the SCP1 and SCP0 bits define the
total division applied to the bus clock to yield the transmit rate clock

r o in conventional baud rate generator mode:

000: TR dividing factor = 1

e P5:3 SCT[2:0] 001: TR dividing factor = 2

l e t 010: TR dividing factor = 4

011: TR dividing factor = 8

s o 100: TR dividing factor = 16

101: TR dividing factor = 32

O b 110: TR dividing factor = 64

111: TR dividing factor = 128
SCI receiver rate divider
These 3 bits, in conjunction with the SCP[1:0] bits define the total
division applied to the bus clock to yield the receive rate clock in
conventional baud rate generator mode:
000: RR dividing factor = 1
2:0 SCR[2:0] 001: RR dividing factor = 2
010: RR dividing factor = 4
011: RR dividing factor = 8
100: RR dividing factor = 16
101: RR dividing factor = 32
110: RR dividing factor = 64
111: RR dividing factor = 128

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On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Extended receive prescaler division register (SCIERPR)

SCIERPR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

ERPR[7:0]

R/W

Table 68. SCIERPR register description

Bit Bit name Function

8-bit extended receive prescaler register

( s )
ct
The extended baud rate generator is activated when a value different
from 00h is stored in this register. Therefore the clock frequency
7:0 ERPR[7:0]

d u
issued from the 16 divider (see Figure 58: SCI baud rate and
extended prescaler block diagram on page 131) is divided by

r o
the binary factor set in the SCIERPR register (in the range 1 to 255).

P
The extended baud rate generator is not active after a reset.

e
l
Extended transmit prescaler division register (SCIETPR)
e t
s o
SCIETPR
7 6 5
O4
b 3 2
Reset value: 0000 0000 (00h)
1 0

) - ETPR[7:0]

ct (s R/W

d u
Table 69.
r o
SCIETPR register description

e P
Bit Bit name Function

let
8-bit extended transmit prescaler register
The extended baud rate generator is activated when a value different

s o from 00h is stored in this register. Therefore the clock frequency

issued from the 16 divider (see Figure 58: SCI baud rate and

Ob 7:0 ETPR[7:0] extended prescaler block diagram on page 131) is divided by

the binary factor set in the SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not used after a reset.
Note: In LIN slave mode, the conventional and extended baud rate
generators are disabled.

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11.5.9 LIN mode - functional description.

The block diagram of the serial control interface, in LIN slave mode is shown in Figure 60:
SCI block diagram in LIN slave mode on page 143.
It uses six registers:
● 3 control registers: SCICR1, SCICR2 and SCICR3
● 2 status registers: SCISR register and LHLR register mapped at the SCIERPR address
● A baud rate register: LPR mapped at the SCIBRR address and an associated fraction
register LPFR mapped at the SCIETPR address
The bits dedicated to LIN are located in the SCICR3. Refer to the register descriptions in
Section 11.5.10: LIN mode register description for the definitions of each bit.

Entering LIN mode

( s )
ct
To use the LINSCI in LIN mode the following configuration must be set in SCICR3 register:
u
● Clear the M bit to configure 8-bit word length.

o d
●

Master
Set the LINE bit.

P r
te
To enter master mode the LSLV bit must be reset In this case, setting the SBK bit will send
e
13 low bits.
o l
b s
Then the baud rate can programmed using the SCIBRR, SCIERPR and SCIETPR registers.
In LIN master mode, the conventional and/or extended prescaler define the baud rate (as in
standard SCI mode)
- O
Slave

(s )
t
Set the LSLV bit in the SCICR3 register to enter LIN slave mode. In this case, setting the
c
d u
SBK bit will have no effect.
In LIN slave mode the LIN baud rate generator is selected instead of the conventional or

r o
extended prescaler. The LIN baud rate generator is common to the transmitter and the
P
receiver.

e
l e t
Then the baud rate can be programmed using LPR and LPRF registers.
Note:

s o It is mandatory to set the LIN configuration first before programming LPR and LPRF,
because the LIN configuration uses a different baud rate generator from the standard one.

O b LIN transmission
In LIN mode the same procedure as in SCI mode has to be applied for a LIN transmission.
To transmit the LIN header the proceed as follows:
● First set the SBK bit in the SCICR2 register to start transmitting a 13-bit LIN synch
break
● Reset the SBK bit
● Load the LIN synch field (0x55) in the SCIDR register to request synch field
transmission
● Wait until the SCIDR is empty (TDRE bit set in the SCISR register)
● Load the LIN message Identifier in the SCIDR register to request Identifier
transmission.

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Figure 59. LIN characters

8-bit word length (M bit is reset)

Data character Next data character

Next
Start Stop start
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 bit bit

Idle line Start

bit
LIN synch field
LIN synch break = 13 low bits
Extra Start
‘1’ bit

LIN synch field Next

Start Bit0
bit
Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
bit
start
Bit7 Stop bit

( s )
Measurement for baud rate autosynchronization

u ct
o d
P r
e t e
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

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ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Figure 60. SCI block diagram in LIN slave mode

Write Read Data register (SCIDR)

Transmit data register (TDR) Received data register (RDR)

TDO

Transmit shift register Receive shift register

RDI
SCICR1
R8 T8 SC/ M
ID
WA/ PCE PS PIE
KE

( s )
u ct
Wake
o d
Transmit control up
unit

P r
Receiver control
Receiver
clock

SCICR2

e t e SCISR
TIE TCIE RIE ILIE TE RE RW/ SBK
U
o l TD/ TC RD/ ID/ OR/ NF FE PE
RE RF LE LHE

b s
SCI interrupt control

- O
(s ) Transmitter clock

c t
u
od
fCPU SCICR3
LD/ LI/ LSLV LA/ LH/ LSF

Pr
UM NE SE LHDM LHIE DF
LIN slave baud rate
auto synchronization unit

e t e SCIBRR

o l LPR7 LPR0 Conventional baud rate

generator and

b s extended prescaler
0

O fCPU /LDIV /16 1

LIN slave baud rate generator

LIN reception
In LIN mode the reception of a byte is the same as in SCI mode but the LINSCI has features
for handling the LIN header automatically (identifier detection) or semi-automatically (synch
break detection) depending on the LIN header detection mode. The detection mode is
selected by the LHDM bit in the SCICR3.

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Additionally, an automatic resynchronization feature can be activated to compensate for any

clock deviation, for more details please refer to LIN baud rate on page 148.
LIN header handling by a slave
Depending on the LIN header detection method the LINSCI will signal the detection of a LIN
header after the LIN synch break or after the Identifier has been successfully received.
Note: 1 It is recommended to combine the header detection function with mute mode. Putting the
LINSCI in mute mode allows the detection of headers only and prevents the reception of any
other characters.
2 This mode can be used to wait for the next header without being interrupted by the data
bytes of the current message in case this message is not relevant for the application.
Synch break detection (LHDM = 0)
When a LIN synch break is received:
( s )
●
ct
The RDRF bit in the SCISR register is set. It indicates that the content of the shift
u
register is transferred to the SCIDR register, a value of 0x00 is expected for a break.
●
o d
The LHDF flag in the SCICR3 register indicates that a LIN synch break field has been

●
detected.
P r
An interrupt is generated if the LHIE bit in the SCICR3 register is set and the I[1:0] bits
are cleared in the CCR register.
e t e
● Then the LIN synch field is received and measured.
o l
–
s
If automatic resynchronization is enabled (LASE bit = 1), the LIN synch field is not
b
transferred to the shift register: There is no need to clear the RDRF bit.
– O
If automatic resynchronization is disabled (LASE bit = 0), the LIN synch field is
-
set.
(s )
received as a normal character and transferred to the SCIDR register and RDRF is

Note:
c t
In LIN slave mode, the FE bit detects all frame error which does not correspond to a break.

d u
Identifier detection (LHDM = 1):

r o
This case is the same as the previous one except that the LHDF and the RDRF flags are set

e P
only after the entire header has been received (this is true whether automatic
resynchronization is enabled or not). This indicates that the LIN Identifier is available in the

l e t
SCIDR register.
Note:
s o During LIN synch field measurement, the SCI state machine is switched off and no
characters are transferred to the data register.

O b LIN slave parity

In LIN slave mode (LINE and LSLV bits are set) LIN parity checking can be enabled by
setting the PCE bit.
In this case, the parity bits of the LIN identifier field are checked. The identifier character is
recognized as the third received character after a break character (included). See Figure 61:
LIN header on page 145.

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Figure 61. LIN header

Parity bits

LIN synch LIN synch Identifier

break field field

The bits involved are the two MSB positions (7th and 8th bits if M = 0; 8th and 9th bits if
M = 0) of the identifier character. The check is performed as specified in Figure 62 by the
LIN specification.

( s )
Figure 62. LIN identifier

u ct
Parity bits Stop bit
o d
r
Start bit
Identifier bits
ID0 ID1 ID2 ID3 ID4 ID5 P0 P1

e P
Identifier field

l e t
s o
P0 = ID0 ⊕ ID1 ⊕ ID2 ⊕ ID4
P1 = ID1 ⊕ ID3 ⊕ ID4 ⊕ ID5
M=0

O b
LIN error detection
) -
LIN header error flag

c t (s
The LIN header error flag indicates that an invalid LIN header has been detected.

d u
When a LIN header error occurs:
●
r o
The LHE flag is set
●

e P
An interrupt is generated if the RIE bit is set and the I[1:0] bits are cleared in the CCR

l e t register.
If autosynchronization is enabled (LASE bit = 1), this can mean that the LIN synch field is

s o corrupted, and that the SCI is in a blocked state (LSF bit is set). The only way to recover is to

O b reset the LSF bit and then to clear the LHE bit.
● The LHE bit is reset by an access to the SCISR register followed by a read of the
SCIDR register.
LHE/OVR error conditions
When auto resynchronization is disabled (LASE bit = 0), the LHE flag detects:
● That the received LIN synch field is not equal to 55h.
● That an overrun occurred (as in standard SCI mode)
● Furthermore, if LHDM is set it also detects that a LIN header reception timeout
occurred (only if LHDM is set).

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

When the LIN auto-resynchronization is enabled (LASE bit = 1), the LHE flag detects:
● That the deviation error on the synch field is outside the LIN specification which allows
up to ± 15.5% of period deviation between the slave and master oscillators.
● A LIN header reception timeout occurred. If THEADER > THEADER_MAX then the LHE flag
is set. Refer to Figure 63 (only if LHDM is set to 1).
● An overflow during the synch field measurement, which leads to an overflow of the
divider registers. If LHE is set due to this error then the SCI goes into a blocked state
(LSF bit is set).
● That an overrun occurred on Fields other than the Synch Field (as in standard SCI
mode)
Deviation error on the synch field

s
The deviation error is checked by comparing the current baud rate (relative to the slave

( )
ct
oscillator) with the received LIN synch field (relative to the master oscillator). Two checks are
performed in parallel:
●
d u
The first check is based on a measurement between the first falling edge and the last

o
falling edge of the synch field. Let us refer to this period deviation as D:
r
If the LHE flag is set, it means that D > 15.625%

e P
If LHE flag is not set, it means that D < 16.40625%

l e t
If 15.625% ≤ D < 16.40625%, then the flag can be either set or reset depending on the

s o
dephasing between the signal on the RDI line and the CPU clock.
●
b
The second check is based on the measurement of each bit time between both edges

O
of the synch field. This checks that each of these bit times is large enough compared to
-
the bit time of the current baud rate.
)
c t
LIN header time-out error (s
When LHE is set due to this error then the SCI goes into a blocked state (LSF bit is set).

d u
When the LIN identifier field detection method is used (by configuring LHDM to 1) or when

r o
LIN auto-resynchronization is enabled (LASE bit = 1), the LINSCI automatically monitors the

e P
THEADER_MAX condition given by the LIN protocol.
If the entire header (up to and including the STOP bit of the LIN identifier field) is not

l e t
received within the maximum time limit of 57 bit times then a LIN header error is signalled

s o and the LHE bit is set in the SCISR register.

O b Figure 63. LIN header reception timeout

LIN synch LIN synch Identifier

break field field

THEADER

The time-out counter is enabled at each break detection. It is stopped in the following
conditions:

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ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

1. A LIN Identifier field has been received

2. An LHE error occurred (other than a timeout error)
3. A software reset of LSF bit (transition from high to low) occurred during the analysis of
the LIN synch field
4. If LHE bit is set due to this error during the LIN synchr field (if LASE bit = 1) then the
SCI goes into a blocked state (LSF bit is set)
If LHE bit is set due to this error during fields other than LIN synch field or if LASE bit is reset
then the current received header is discarded and the SCI searches for a new break field.
Note on LIN header time-out limit
According to the LIN specification, the maximum length of a LIN header which does not
cause a timeout is equal to 1.4 * (34 + 1) = 49 TBIT_MASTER. TBIT_MASTER refers to the
master baud rate.
( s )
u ct
When checking this timeout, the slave node is desynchronized for the reception of the LIN
break and synch fields. Consequently, a margin must be allowed, taking into account the
d
worst case: This occurs when the LIN identifier lasts exactly 10 TBIT_MASTER periods. In this
o
P r
case, the LIN break and synch fields lasts 49 - 10 = 39 TBIT_MASTER periods.
Assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. This

t e
leads to a maximum allowed header length of: 39 x (1/0.845) TBIT_MASTER + 10TBIT_MASTER

e
o l
= 56.15 TBIT_SLAVE. A margin is provided so that the time-out occurs when the header
length is greater than 57 TBIT_SLAVE periods. If it is less than or equal to 57 TBIT_SLAVE
periods, then no timeout occurs.
b s
LIN header length

- O
Even if no timeout occurs on the LIN header, it is possible to have access to the effective LIN

(s )
header length (THEADER) through the LHL register. This allows monitoring at software level

t
the TFRAME_MAX condition given by the LIN protocol.
c
u
This feature is only available when LHDM bit = 1 or when LASE bit = 1.
d
o
Mute mode and errors
r
e P
In mute mode when LHDM bit = 1, if an LHE error occurs during the analysis of the LIN
synch field or if a LIN header time-out occurs then the LHE bit is set but it does not wake up

l e t
from mute mode. In this case, the current header analysis is discarded. If needed, the
software has to reset LSF bit. Then the SCI searches for a new LIN header.
o
bs
In mute mode, if a framing error occurs on a data (which is not a break), it is discarded and
the FE bit is not set.
O When LHDM bit = 1, any LIN header which respects the following conditions causes a wake-
up from mute mode:
● A valid LIN break field (at least 11 dominant bits followed by a recessive bit)
● A valid LIN synch field (without deviation error)
● A LIN identifier field without framing error. Note that a LIN parity error on the LIN
identifier field does not prevent wake-up from mute mode.
● No LIN header time-out should occur during header reception.

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Figure 64. LIN synch field measurement

TCPU = CPU period

TBR = Baud rate period
SM = Synch measurement register (15 bits)
TBR = 16.LP.TCPU
TBR

LIN synch break LIN synch field

Start Next
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 start
Bit7 bit
Extra Stop
’1’ bit
Measurement = 8.TBR = SM.tCPU

LPR(n) LPR(n+1)

LPR = TBR/(16.TCPU) = rounding (SM/128)

( s )
LIN baud rate
u ct
o d
automatic resynchronization as described below.
P r
Baud rate programming is done by writing a value in the LPR prescaler or performing an

Automatic resynchronization

e t e
l
To automatically adjust the baud rate based on measurement of the LIN synch field:
o
●
s
Write the nominal LIN prescaler value (usually depending on the nominal baud rate) in
the LPFR/LPR registers
b
●
O
Set the LASE bit to enable the auto synchronization unit
-
(s )
When auto synchronization is enabled, after each LIN synch break, the time duration
between five falling edges on RDI is sampled on fCPU and the result of this measurement is

c t
stored in an internal 15-bit register called SM (not user accessible) (see Figure 64). Then

d u
the LDIV value (and its associated LPFR and LPR registers) are automatically updated at
the end of the fifth falling edge. During LIN synch field measurement, the SCI state machine

r o
is stopped and no data is transferred to the data register.

P
LIN slave baud rate generation
e
l e t
In LIN mode, transmission and reception are driven by the LIN baud rate generator
Note:
s o LIN master mode uses the extended or conventional prescaler register to generate the baud

O b rate.
If LINE bit = 1 and LSLV bit = 1 then the conventional and extended baud rate generators
are disabled The baud rate for the receiver and transmitter are both set to the same value,
depending on the LIN slave baud rate generator:
fCPU
Tx = Rx =
(16*LDIV)

where:
LDIV is an unsigned fixed point number. The mantissa is coded on 8 bits in the LPR register
and the fraction is coded on 4 bits in the LPFR register.
If LASE bit = 1 then LDIV is automatically updated at the end of each LIN synch field.

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Three registers are used internally to manage the auto-update of the LIN divider (LDIV):
● LDIV_NOM (nominal value written by software at LPR/LPFR addresses)
● LDIV_MEAS (results of the field synch measurement)
● LDIV (used to generate the local baud rate)
The control and interactions of these registers, explained in Figure 65 and Figure 66,
depend on the LDUM bit setting (LIN divider update method).
Note: As explained in Figure 65 and Figure 66, LDIV can be updated by two concurrent actions: a
transfer from LDIV_MEAS at the end of the LIN sync field and a transfer from LDIV_NOM
due to a software write of LPR. If both operations occur at the same time, the transfer from
LDIV_NOM has priority.

Figure 65. LDIV read/write operations when LDUM = 0

( s )
ct
Write LPR Write LPFR

d u
o
LDIV_NOM LIN sync field
MANT(7:0) FRAC(3:0)

P r measurement

e t e
Write LPR
o l
s MANT(7:0) FRAC(3:0) LDIV_MEAS

O b Update
at end of

) - synch field

ct (s
MANT(7:0) FRAC(3:0) LDIV Baud rate generation

d u
r o Read LPR Read LPFR

e P
l e t
s o
O b

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Figure 66. LDIV read/write operations when LDUM = 1

Write LPR Write LPFR

LIN sync field

MANT(7:0) FRAC(3:0) LDIV_NOM
measurement

RDRF = 1
MANT(7:0) FRAC(3:0) LDIV_MEAS

Update

)
at end of
synch field

( s
MANT(7:0) FRAC(3:0) LDIV
u
Baud rate generation ct
o d
Read LPR Read LPFR
P r
LINSCI clock tolerance
e t e
o l
LINSCI clock tolerance when unsynchronized

b s
When LIN slaves are unsynchronized (meaning no characters have been transmitted for a
O
relatively long time), the maximum tolerated deviation of the LINSCI clock is ±15%.
-
new reception occurs.
(s )
If the deviation is within this range then the LIN synch break is detected properly when a

c t
This is made possible by the fact that masters send 13 low bits for the LIN synch break,

d u
which can be interpreted as 11 low bits (13 bits -15% = 11.05) by a ‘fast’ slave and then

r o
considered as a LIN synch break. According to the LIN specification, a LIN synch break is
valid when its duration is greater than tSBRKTS = 10. This means that the LIN synch break
P
must last at least 11 low bits.
e
Note:
l e t
If the period desynchronization of the slave is +15% (slave too slow), the character ‘00h’
which represents a sequence of 9 low bits must not be interpreted as a break character (9

s o bits + 15% = 10.35). Consequently, a valid LIN synch break must last at least 11 low bits.

O b LINSCI clock tolerance when synchronized

When synchronization has been performed, following reception of a LIN synch break, the
LINSCI, in LIN mode, has the same clock deviation tolerance as in SCI mode, which is
explained below:
During reception, each bit is oversampled 16 times. The mean of the 8th, 9th and 10th
samples is considered as the bit value.
Consequently, the clock frequency should not vary more than 6/16 (37.5%) within one bit.
The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one
start bit, 1 data byte, 1 stop bit), the clock deviation should not exceed 3.75%.

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ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Clock deviation causes

The causes which contribute to the total deviation are:
– DTRA: Deviation due to transmitter error.
Note: The transmitter can be either a master or a slave (in case of a slave listening to the
response of another slave)
– DMEAS: Error due to the LIN synch measurement performed by the receiver
– DQUANT: Error due to the baud rate quantization of the receiver
– DREC: Deviation of the local oscillator of the receiver. This deviation can occur
during the reception of one complete LIN message assuming that the deviation
has been compensated at the beginning of the message.
– DTCL: Deviation due to the transmission line (generally due to the transceivers)

( s )
ct
All the deviations of the system should be added and compared to the LINSCI clock
tolerance:
DTRA + DMEAS +DQUANT + DREC + DTCL < 3.75%
d u
r o
Figure 67. Bit sampling in reception mode

e P
RDI line
l e t
s o
Sampled values

Sample
1 2 3 4 5 6
O7
b 8 9 10 11 12 13 14 15 16

-
clock

(s )
c t 6/16

u 7/16 7/16

r od One bit time

e P
l e t
Error due to LIN synch measurement
The LIN synch field is measured over eight bit times.
o
bs
This measurement is performed using a counter clocked by the CPU clock. The edge
detections are performed using the CPU clock cycle.
O This leads to a precision of 2 CPU clock cycles for the measurement which lasts 16*8*LDIV
clock cycles.
Consequently, this error (DMEAS) is equal to: 2/(128*LDIVMIN).
LDIVMIN corresponds to the minimum LIN prescaler content, leading to the maximum baud
rate, taking into account the maximum deviation of +/-15%.

Error due to baud rate quantization

The baud rate can be adjusted in steps of 1/(16 * LDIV). The worst case occurs when the
“real” baud rate is in the middle of the step.
This leads to a quantization error (DQUANT) equal to 1/(2*16*LDIVMIN).

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Impact of clock deviation on maximum baud rate

The choice of the nominal baud rate (LDIVNOM) will influence both the quantization error
(DQUANT) and the measurement error (DMEAS). The worst case occurs for LDIVMIN.
Consequently, at a given CPU frequency, the maximum possible nominal baud rate
(LPRMIN) should be chosen with respect to the maximum tolerated deviation given by the
equation:
DTRA + 2 / (128*LDIVMIN) + 1 / (2*16*LDIVMIN)
+ DREC + DTCL < 3.75%
Example:
A nominal baud rate of 20 Kbits/s at TCPU = 125ns (8 MHz) leads to LDIVNOM = 25d
LDIVMIN = 25 - 0.15*25 = 21.25
( s )
DMEAS = 2 / (128*LDIVMIN) * 100 = 0.00073%
u ct
DQUANT = 1 / (2*16*LDIVMIN) * 100 = 0.0015%.
o d
LIN slave systems
P r
te
For LIN slave systems (the LINE and LSLV bits are set), receivers wake up by LIN synch
break or LIN identifier detection (depending on the LHDM bit).
e
Hot plugging feature for LIN slave nodes
o l
b s
In LIN slave mute mode (the LINE, LSLV and RWU bits are set) it is possible to hot plug to a

- O
network during an ongoing communication flow. In this case the SCI monitors the bus on the
RDI line until 11 consecutive dominant bits have been detected and discards all the other
bits received.

(s )
11.5.10
c t
LIN mode register description

d u
Status register (SCISR)
r o
e P
SCISR Reset value: 1100 0000 (C0h)

let
7 6 5 4 3 2 1 0

so
TDRE TC RDRF IDLE LHE NF FE PE

O b RO RO RO RO RO RO RO RO

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Table 70. SCISR register description(1)

Bit Name Function

Transmit data register empty

This bit is set by hardware when the content of the TDR register has been transferred
into the shift register. An interrupt is generated if the TIE = 1 in the SCICR2 register. It
7 TDRE is cleared by a software sequence (an access to the SCISR register followed by a
write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Transmission complete
This bit is set by hardware when transmission of a character containing data is

6 TC
a software sequence (an access to the SCISR register followed by a write to the
( )
complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by

s
ct
SCIDR register).
0: Transmission is not complete
1: Transmission is complete
d u
o
Note: TC is not set after the transmission of a preamble or a break.
r
Received data ready flag

e P
This bit is set by hardware when the content of the RDR register has been transferred

5 RDRF
l t
to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is
e
cleared by a software sequence (an access to the SCISR register followed by a read
to the SCIDR register).
s o
0: Data is not received
b
1: Received data are ready to be read
O
Idle line detected

) -
This bit is set by hardware when an idle line is detected. An interrupt is generated if

4 IDLE
c (s
the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to
t
the SCISR register followed by a read to the SCIDR register).

d u
0: No idle line is detected
1: idle line is detected

r o
Note: The IDLE bit is not set again until the RDRF bit has been set itself (that is, a new

e P idle line occurs).

l e t LIN header error

During LIN header this bit signals three error types:

s o The LIN synch field is corrupted and the SCI is blocked in LIN synch state (LSF
bit = 1).

O b A timeout occurred during LIN header reception.

An overrun error was detected on one of the header field (see OR bit description in
Status register (SCISR) on page 134).
3 LHE An interrupt is generated if RIE = 1 in the SCICR2 register. If blocked in the LIN synch
state, the LSF bit must first be reset (to exit LIN synch field state and then to be able to
clear LHE flag). Then it is cleared by the following software sequence: An access to
the SCISR register followed by a read to the SCIDR register.
0: No LIN header error
1: LIN header error detected
Note: Apart from the LIN header this bit signals an overrun error as in SCI mode, (see
description in Status register (SCISR) on page 134).

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Table 70. SCISR register description(1) (continued)

Bit Name Function

Noise flag
In LIN master mode (LINE bit = 1 and LSLV bit = 0) this bit has the same function as in
2 NF
SCI mode, please refer to Status register (SCISR) on page 134.
In LIN slave mode (LINE bit = 1 and LSLV bit = 1) this bit has no meaning.
Framing error
In LIN slave mode, this bit is set only when a real framing error is detected (if the stop
bit is dominant (0) and at least one of the other bits is recessive (1). It is not set when
a break occurs, the LHDF bit is used instead as a break flag (if the LHDM bit = 0). It is
1 FE
cleared by a software sequence (an access to the SCISR register followed by a read
to the SCIDR register).
0: No framing error

( s )
ct
1: Framing error detected
Parity error

d u
This bit is set by hardware when a LIN parity error occurs (if the PCE bit is set) in

0 PE r o
receiver mode. It is cleared by a software sequence (a read to the status register

in the SCICR1 register.

e P
followed by an access to the SCIDR data register). An interrupt is generated if PIE = 1

0: No LIN parity error

1: LIN parity error detected
l e t
s o
1. Bits 7:4 have the same function as in SCI mode, please refer to Status register (SCISR) on page 134.

Control register 1 (SCICR1)

O b
) -
SCICR1
7 6
c t (s
5 4 3 2
Reset value: x000 0000 (x0h)
1 0

u
od
R8 T8 SCID M WAKE PCE Reserved PIE

Pr
R/W R/W R/W R/W R/W R/W - R/W

e t e
Table 71. SCICR1 register description(1)
l
so
Bit Name Function

O b 7 R8
Receive data bit 8
This bit is used to store the 9th bit of the received word when M = 1.
Transmit data bit 8
6 T8
This bit is used to store the 9th bit of the transmitted word when M = 1.
Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and cleared
5 SCID
by software.
0: SCI enabled
1: SCI prescaler and outputs disabled

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Table 71. SCICR1 register description(1) (continued)

Bit Name Function

Word length
This bit determines the word length. It is set or cleared by software.
0: 1 start bit, 8 data bits, 1 stop bit
4 M
1: 1 start bit, 9 data bits, 1 stop bit
Note: The M bit must not be modified during a data transfer (both transmission and
reception).
Wake-up method
This bit determines the SCI wake-up method. It is set or cleared by software.
3 WAKE 0: Idle line
1: Address mark
Note: If the LINE bit is set, the WAKE bit is deactivated and replaced by the LHDM bit.
( s )
Parity control enable

u ct
This bit is set and cleared by software. It selects the hardware parity control for LIN
2 PCE
identifier parity check.
o d
0: Parity control disabled
1: Parity control enabled
P r
e t e
When a parity error occurs, the PE bit in the SCISR register is set.
1 - Reserved, must be kept cleared

o l
Parity interrupt enable

b s
This bit enables the interrupt capability of the hardware parity control when a parity

0 PIE O
error is detected (PE bit set). The parity error involved can be a byte parity error (if bit

-
PCE is set and bit LPE is reset) or a LIN parity error (if bit PCE is set and bit LPE is
set).

(s )
0: Parity error interrupt disabled

t
1: Parity error interrupt enabled
c
page 136.
d u
1. Bits 7:3 and bit 0 have the same function as in SCI mode; please refer to Control register 1 (SCICR1) on

r o
P
Control register 2 (SCICR2)

e
l e t
SCICR2 Reset value: 0000 0000 (00h)

o
bs
7 6 5 4 3 2 1 0

TIE TCIE RIE ILIE TE RE RWU SBK

O R/W R/W R/W R/W R/W R/W R/W R/W

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Table 72. SCICR2 register description(1)

Bit Name Function

Transmitter interrupt enable

This bit is set and cleared by software.
7 TIE
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register
Transmission complete interrupt enable
This bit is set and cleared by software.
6 TCIE
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register
Receiver interrupt enable

5 RIE
This bit is set and cleared by software.

( s )
ct
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register
Idle line interrupt enable
d u
4 ILIE
This bit is set and cleared by software.
r o
0: Interrupt is inhibited
P
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register
e
Transmitter enable
l e t
0: Transmitter is disabled
s o
This bit enables the transmitter. It is set and cleared by software.

3 TE 1: Transmitter is enabled

O b
Note: During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a

) -
preamble (idle line) after the current word.
When TE is set, there is a 1 bit-time delay before the transmission starts.

t
Receiver enable
c (s
2 RE

d u
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled in the SCISR register

r o
1: Receiver is enabled and begins searching for a start bit

e P Receiver wake-up
This bit determines if the SCI is in mute mode or not. It is set and cleared by software

l e t and can be cleared by hardware when a wake-up sequence is recognized.

0: Receiver in active mode
o
bs
1: Receiver in mute mode
1 RWU
Note: Mute mode is recommended for detecting only the header and avoiding the

O reception of any other characters. For more details please refer to LIN reception
on page 143.
In LIN slave mode, when RDRF is set, the software can not set or clear the RWU
bit.
Send break
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted
0 SBK
1: Break characters are transmitted
Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter sends a BREAK word at
the end of the current word.
1. Bits 7:2 have the same function as in SCI mode; please refer to Control register 2 (SCICR2) on page 137.

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Control register 3 (SCICR3)

SCICR3 Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

LDUM LINE LSLV LASE LHDM LHIE LHDF LSF

R/W R/W R/W R/W R/W R/W R/W R/W

Table 73. SCICR3 register description

Bit Name Function

LIN divider update method

( s )
ct
This bit is set and cleared by software and is also cleared by hardware (when
RDRF = 1). It is only used in LIN slave mode. It determines how the LIN divider
can be updated by software.
0: LDIV is updated as soon as LPR is written
d u
r o
(if no auto synchronization update occurs at the same time)
7 LDUM
P
1: LDIV is updated at the next received character (when RDRF = 1)
after a write to the LPR register
e
e t
Note: If no write to LPR is performed between the setting of LDUM bit and the
l
reception of the next character, LDIV is updated with the old value.

s o
After LDUM has been set, it is possible to reset the LDUM bit by software.

LIN mode enable bits

O b
In this case, LDIV can be modified by writing into LPR/LPFR registers.

) -
These bits configure the LIN mode:

(s
0x: LIN mode disabled

c t
10: LIN master mode
11: LIN slave mode

u
The LIN master configuration enables sending of LIN synch breaks (13 low
d
r obits) using the SBK bit in the SCICR2 register.
The LIN slave configuration enables:

P
6:5 LINE, LSLV

e
The LIN slave baud rate generator. The LIN divider (LDIV) is then represented by

l e t the LPR and LPFR registers. The LPR and LPFR registers are read/write
accessible at the address of the SCIBRR register and the address of the

s o SCIETPR register.
Management of LIN headers

O b LIN synch break detection (11-bit dominant)

LIN wake-up method (see LHDM bit) instead of the normal SCI wake-up method
Inhibition of break transmission capability (SBK has no effect)
LIN parity checking (in conjunction with the PCE bit)
LIN auto synch enable
This bit enables the auto synch unit (ASU). It is set and cleared by software. It is
4 LASE only usable in LIN slave mode.
0: Auto synch unit disabled
1: Auto synch unit enabled

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Table 73. SCICR3 register description (continued)

Bit Name Function

LIN header detection method

This bit is set and cleared by software. It is only usable in LIN slave mode. It
enables the header detection method. In addition if the RWU bit in the SCICR2
3 LHDM register is set, the LHDM bit selects the wake-up method (replacing the WAKE
bit).
0: LIN synch break detection method
1: LIN identifier field detection method
LIN header interrupt enable
This bit is set and cleared by software. It is only usable in LIN slave mode.
2 LHIE
0: LIN header interrupt is inhibited
1: An SCI interrupt is generated whenever LHDF = 1
( s )
LIN header detection flag

u ct
This bit is set by hardware when a LIN header is detected and cleared by a

d
software sequence (an access to the SCISR register followed by a read of the

o
0: No LIN header detected
1: LIN header detected P r
SCICR3 register). It is only usable in LIN slave mode.

1 LHDF

t e
Note: The header detection method depends on the LHDM bit:
e
l
- If LHDM = 0, a header is detected as a LIN synch break

o
b s
- If LHDM = 1, a header is detected as a LIN Identifier, meaning that a LIN
synch break field + a LIN synch field + a LIN identifier field have been

-
LIN synch field state O
consecutively received.

(s )
This bit indicates that the LIN synch field is being analyzed. It is only used in LIN

c t
slave mode. In auto synchronization mode (LASE bit = 1), when the SCI is in the
LIN synch field state it waits or counts the falling edges on the RDI line.
0 LSF

d u
It is set by hardware as soon as a LIN synch break is detected and cleared by
hardware when the LIN synch field analysis is finished (see Figure 68). This bit

r o can also be cleared by software to exit LIN Synch state and return to idle mode.

e P 0: The current character is not the LIN synch field

1: LIN synch field state (LIN synch field undergoing analysis)

l e t
s o Figure 68. LSF bit set and clear

O b 11 dominant bits Parity bits

LSF bit

LIN synch LIN synch Identifier

break field field

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

LIN divider registers

LDIV is coded using the two registers LPR and LPFR. In LIN slave mode, the LPR register is
accessible at the address of the SCIBRR register and the LPFR register is accessible at the
address of the SCIETPR register.

LIN prescaler register (LPR)

LPR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

LPR[7:0]

R/W

( s )
Table 74. LPR register description
u ct
Bit Name Function
o d
7:0 LPR[7:0]
LIN prescaler (mantissa of LDIV)
P r
These 8 bits define the value of the mantissa of the LDIV (see Table 75).

e t e
Table 75. LIN mantissa rounded values
o l
LPR[7:0]
b s Rounded mantissa (LDIV)

00h
- O SCI clock disabled
01h

(s ) 1

ct
... ...

du
FEh 254
FFh 255

r o
Caution:
e P
LPR and LPFR registers have different meanings when reading or writing to them.

e t
Consequently bit manipulation instructions (BRES or BSET) should never be used to modify

ol
the LPR[7:0] bits, or the LPFR[3:0] bits.

b s LIN prescaler fraction register (LPFR)

O LPFR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

Reserved LPFR[3:0]

- R/W

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On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Table 76. LPFR register description

Bit Name Function

7:4 - Reserved, must be kept cleared

Fraction of LDIV
These 4 bits define the fraction of the LDIV (see Table 77).
Note: When initializing LDIV, the LPFR register must be written first. Then, the
3:0 LPFR[3:0] write to the LPR register effectively updates LDIV and so the clock
generation.
In LIN slave mode, if the LPR[7:0] register is equal to 00h, the transceiver
and receiver input clocks are switched off.

Table 77. LDIV fractions

( s )
LPFR[3:0] Fraction (LDIV)

u ct
0h 0

o d
1h
...
1/16

P
...
r
e
let
Eh 14/16
Fh

s o 15/16

Examples of LDIV coding

O b
Example 1: LPR = 27d and LPFR = 12d

) -
This leads to:
Mantissa (LDIV) = 27d
t ( s
u c
Fraction (LDIV) = 12/16 = 0.75d

d
Therefore LDIV = 27.75d
o
P r
Example 2: LDIV = 25.62d
This leads to:
e
let
LPFR = rounded(16*0.62d) = rounded(9.92d) = 10d = Ah
LPR = mantissa (25.620d) = 25d = 1Bh

s o Example 3: LDIV = 25.99d

Ob This leads to:

LPFR = rounded(16*0.99d) = rounded(15.84d) = 16d
The carry must be propagated to the mantissa: LPR = mantissa (25.99) +
1 = 26d = 1Ch.

LIN header length register (LHLR)

LHLR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

LHL[7:0]

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ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Note: In LIN slave mode when LASE = 1 or LHDM = 1, the LHLR register is accessible at the
address of the SCIERPR register. Otherwise this register is always read as 00h.

Table 78. LHLR register description

Bit Name Function

LIN header length

This is a read-only register, which is updated by hardware if one of the following
conditions occurs:
After each break detection, it is loaded with ‘FFh’
If a timeout occurs on THEADER, it is loaded with 00h
After every successful LIN header reception (at the same time as the setting of
7:0 LHL[7:0]
LHDF bit), it is loaded with a value (LHL) which gives access to the number of
bit times of the LIN header length (THEADER).

( s )
ct
LHL register coding is as follows:
THEADER_MAX = 57

u
LHL (7:2) represents the mantissa of (57 - THEADER) (see Table 79)
d
o
LHL (1:0) represents the fraction (57 - THEADER) (see Table 80)

r
Table 79. LIN header mantissa values
e P
LHL[7:2]
l e
Mantissa (57 - THEADER) t Mantissa (THEADER)

o
bs
0h 0 57
1h 1 56
...
- O ... ...
39h

( s ) 56 1
3Ah
c t 57 0

du
3Bh 58 Never occurs

ro
... ... ...

e P 3Eh 62 Never occurs

let
3Fh 63 Initial value

s o Table 80. LIN header fractions

Ob LHL[1:0]

0h
Fraction (57 - THEADER)

0
1h 1/4
2h 1/2
3h 3/4

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On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Examples of LHL coding:

Example 1: LHL = 33h = 001100 11b
LHL(7:3) = 1100b = 12d
LHL(1:0) = 11b = 3d
This leads to:
Mantissa (57 - THEADER) = 12d
Fraction (57 - THEADER) = 3/4 = 0.75
Therefore:
(57 - THEADER) = 12.75d and THEADER = 44.25d
Example 2:
57 - THEADER = 36.21d
LHL(1:0) = rounded(4*0.21d) = 1d
( s )
LHL(7:2) = Mantissa (36.21d) = 36d = 24h
u ct
Therefore LHL(7:0) = 10010001 = 91h

o d
Example 3:
57 - THEADER = 36.90d
P r
LHL(1:0) = rounded(4*0.90d) = 4d

e t e
The carry must be propagated to the matissa:
LHL(7:2) = Mantissa (36.90d) + 1 = 37d
o l
Therefore LHL(7:0) = 10110000 = A0h
b s
Table 81.
-
LINSCI1 register map and reset values O
Addr. (Hex.) Register name
(s
7 ) 6 5 4 3 2 1 0

40
SCISR
c t
TDRE TC RDRF IDLE OR/LHE NF FE PE
Reset value

du 1 1 0 0 0 0 0 0

41
SCIDR
Reset value
r o DR7
-
DR6
-
DR5
-
DR4
-
DR3
-
DR2
-
DR1
-
DR0
-

e P
SCIBRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
42

l e t LPR (LIN slave mode)

Reset value
LPR7
0
LPR6
0
LPR5
0
LPR4
0
LPR3
0
LPR2
0
LPR1
0
LPR0
0

o
bs
SCICR1 R8 T8 SCID M WAKE PCE PS PIE
43
Reset value x 0 0 0 0 0 0 0

O 44
SCICR2
Reset value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
SCICR3 NP LINE LSLV LASE LHDM LHIE LHDF LSF
45
Reset value 0 0 0 0 0 0 0 0
SCIERPR ERPR7 ERPR6 ERPR5 ERPR4 ERPR3 ERPR2 ERPR1 ERPR0
46 LHLR (LIN slave mode) LHL7 LHL6 LHL5 LHL4 LHL3 LHL2 LHL1 LHL0
Reset value 0 0 0 0 0 0 0 0
SCITPR ETPR7 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0
47 LPFR (LIN slave mode) LDUM 0 0 0 LPFR3 LPFR2 LPFR1 LPFR0
Reset value 0 0 0 0 0 0 0 0

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 ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Table 81. LINSCI1 register map and reset values (continued)

Addr. (Hex.) Register name 7 6 5 4 3 2 1 0

SCISR TDRE TC RDRF IDLE OR/LHE NF FE PE

40
Reset value 1 1 0 0 0 0 0 0
SCIDR DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
41
Reset value - - - - - - - -

11.6 10-bit A/D converter (ADC)

11.6.1 Introduction
The on-chip analog to digital converter (ADC) peripheral is a 10-bit, successive
( s )
u ct
approximation converter with internal sample and hold circuitry. This peripheral has up to
seven multiplexed analog input channels (refer to device pinout description) that allow the

d
peripheral to convert the analog voltage levels from up to seven different sources.
o
controlled through a control/status register.
P r
The result of the conversion is stored in a 10-bit data register. The A/D converter is

e t e
11.6.2 Main features
o l
●
●
10-bit conversion
b
Up to 7 channels with multiplexed input
s
●
-
Linear successive approximation O
●
)
Data register (DR) which contains the results

(s
●
●
c t
Conversion complete status flag
On/off bit (to reduce consumption)

d u
The block diagram is shown in Figure 69: ADC block diagram on page 164.

r o
11.6.3
P
Functional description
e
l e t Analog power supply

s o VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to

O b Section 2: Pin description) they are internally connected to the VDD and VSS pins.
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Figure 69. ADC block diagram

Div 4
1
fADC
fCPU Div 2
0
0
1
Slow bit

SPE AD
EOC ED ON 0 0 CH2 CH1 CH0 ADCCSR

AIN0 Hold control

( s )
ct
AIN1 RADC
Analog to digital

u
Analog
converter

d
mux

AINx CADC
r o
e P
ADCDRH D9 D8

l e t
D7 D6 D5 D4 D3 D2

o
bs
AMP SL AMP
ADCDRL 0 0 0 CAL OW SEL D1 D0

Digital A/D conversion result

- O
( s )
The conversion is monotonic, meaning that the result never decreases if the analog input
t
does not decrease and never increases if the analog input does not increase.
c
u
If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the
d
r o
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
P
If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the
e
l e t
conversion result in the ADCDRH and ADCDRL registers is 00 00h.

s o The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Section 13:

O b Electrical characteristics.
RAIN is the maximum recommended impedance for an analog input signal. If the impedance
is too high, this results in a loss of accuracy due to leakage and sampling not being
completed in the allotted time.

A/D conversion
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to
Section 10: I/O ports. Using these pins as analog inputs does not affect the ability of the port
to be read as a logic input.
In the ADCCSR register, select the CH[2:0] bits to assign the analog channel to convert.

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ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

ADC conversion mode

In the ADCCSR register, set the ADON bit to enable the A/D converter and to start the
conversion. From this time on, the ADC performs a continuous conversion of the selected
channel.
When a conversion is complete:
– The EOC bit is set by hardware
– The result is in the ADCDR registers
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
2. Read ADCDRL

( s )
ct
3. Read ADCDRH. This clears EOC automatically
To read only 8 bits, perform the following steps:
d u
1.
2.
Poll EOC bit
Read ADCDRH. This clears EOC automatically r o
e P
11.6.4 Low-power modes
l e t
Note:
o
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced

s
power consumption when no conversion is needed and between single shot conversions
.

Table 82.
O b
Effect of low power modes on the A/D converter
Mode
) - Description

Wait
t (s
No effect on A/D converter

c
d u
A/D converter disabled
After wakeup from halt mode, the A/D converter requires a stabilization time
Halt

r o tSTAB (Section 13: Electrical characteristics) before accurate conversions can be

e P performed.

11.6.5
l e t
Interrupts
o
bs
None.

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

11.6.6 Register description

Control/status register (ADCCSR)

ADCCSR Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

EOC SPEED ADON Reserved Reserved CH[2:0]

R R/W R/W - - R/W

Table 83. ADCCSR register description

Bit Bit name Function
( s )
End of conversion

u ct
This bit is set by hardware. It is cleared by software reading the
7 EOC ADCDRH register.

o d
0: Conversion is not complete
1: Conversion complete
P r
ADC clock selection

e t e
This bit is set and cleared by software. It is used together with the
6 SPEED
l
SLOW bit to configure the ADC clock speed. Refer to Table 86: ADC
o
b s
clock configuration on page 167 concerning the SLOW bit
description of the ADCDRL register.

- O
A/D converter on
This bit is set and cleared by software.
5 ADON

(s ) 0: A/D converter is switched off

1: A/D converter is switched on
4:3 -
c t Reserved, must be kept cleared.

u
od
Channel selection
These bits are set and cleared by software. They select the analog

P r input to convert:
000: channel pin = AIN0

e t e 001: channel pin = AIN1

010: channel pin = AIN2

o l 2:0 CH[2:0]
011: channel pin = AIN3

b s 100: channel pin = AIN4

101: channel pin = AIN5

O 110: channel pin = AIN6

Note: The number of channels is device dependent. Refer to
Section 2: Pin description.

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ST7L34 ST7L35 ST7L38 ST7L39 On-chip peripherals

Data register high (ADCDRH)

ADCDRH Reset value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

D[9:2]

Table 84. ADCDRH register description

Bit Bit name Function

7:0 D[9:2] MSB of analog converted value

( s )
Control and data register low (ADCDRL)
u ct
o d
ADCDRL
7 6 5 4 3 P r2
Reset value: 0000 0000 (00h)
1 0

Reserved Reserved Reserved Reserved SLOW

e t eReserved D[1:0]

- - - -
o l
R/W - R/W

b s
Table 85. ADCDRL register description
- O
Bit Bit name

(s ) Function

ct
7:5 - Reserved, must be kept cleared

du
4 - Reserved, must be kept cleared

ro
Slow mode
This bit is set and cleared by software. It is used together with the

e P3 SLOW
SPEED bit to configure the ADC clock speed as shown in Table 86:

l e t 2 -
ADC clock configuration on page 167
Reserved, must be kept cleared

o
bs
1:0 D[1:0] LSB of converted analog value

O Table 86. ADC clock configuration(1)

fADC SLOW SPEED

fCPU/2 0 0
fCPU 0 1
fCPU/4 1 x
1. Max fADC allowed = 4 MHz (see Section 13.11: 10-bit ADC characteristics on page 210)

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 On-chip peripherals ST7L34 ST7L35 ST7L38 ST7L39

Table 87. ADC register map and reset values

Address Register
7 6 5 4 3 2 1 0
(Hex.) label

ADCCSR EOC SPEED ADON 0 0 CH2 CH1 CH0

0034h
Reset value 0 0 0 0 0 0 0 0
ADCDRH D9 D8 D7 D6 D5 D4 D3 D2
0035h
Reset value 0 0 0 0 0 0 0 0
ADCDRL 0 0 0 0 SLOW 0 D1 D0
0036h
Reset value 0 0 0 0 0 0 x x

( s )
u ct
o d
P r
e te
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

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 ST7L34 ST7L35 ST7L38 ST7L39 Instruction set

12 Instruction set

12.1 ST7 addressing modes

The ST7 core features 17 different addressing modes which can be classified in seven main
groups (see Table 88).

Table 88. CPU addressing mode groups

Addressing mode Example

Inherent nop
Immediate ld A,#$55

( s )
ct
Direct ld A,$55
Indexed ld A,($55,X)

d u
Indirect ld A,([$55],X)

r o
Relative
Bit operation
jrne loop
bset byte,#5
e P
l e t
s o
The ST7instruction set is designed to minimize the number of bytes required per instruction.
To do so, most of the addressing modes may be subdivided in two sub-modes called long
and short:
O b
●
-
Long addressing mode is more powerful because it can use the full 64 Kbyte address

)
space, however it uses more bytes and more CPU cycles.
●

c t (s
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All

d u
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

r o
The ST7 assembler optimizes the use of long and short addressing modes.

e P
l e t
s o
O b

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 Instruction set ST7L34 ST7L35 ST7L38 ST7L39

Table 89. CPU addressing mode overview

Mode Syntax Destination/s Pointer Pointer Length

ource address size (bytes)
Inherent nop +0
Immediate ld A,#$55 +1
Short Direct ld A,$10 00..FF +1
Long Direct ld A,$1000 0000..FFFF +2
+ 0 (with X
register)
No offset Direct Indexed ld A,(X) 00..FF
+1 (with Y

Short Direct Indexed ld A,($10,X) 00..1FE

( s
+1 )
register)

Long Direct Indexed ld A,($1000,X) 0000..FFFF

u ct +2
Short Indirect ld A,[$10] 00..FF 00..FF

o d byte +2

Pr
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF
e t e 00..FF word +2

l
so
PC-
Relative Direct jrne loop +1
128/PC+127(1)

Relative Indirect jrne [$10]

O b PC-
128/PC+127(1)
00..FF byte +2

Bit Direct
) -
bset $10,#7 00..FF +1
Bit Indirect

ct (s bset [$10],#7 00..FF 00..FF byte +2

du
Bit Direct Relative btjt $10,#7,skip 00..FF +2
Bit

r oIndirect Relative btjt [$10],#7,skip 00..FF 00..FF byte +3

P
1. At the time the instruction is executed, the program counter (PC) points to the instruction following JRxx.

e
e t
s ol
O b

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12.1.1 Inherent
All inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.

Table 90. Inherent instructions

Inherent instruction Function

NOP No operation
TRAP S/W interrupt
WFI Wait for interrupt (low power mode)
HALT Halt oscillator (lowest power mode)
RET Subroutine return
( s )
IRET Interrupt subroutine return

u ct
SIM Set interrupt mask

o d
RIM
SCF
Reset interrupt mask
Set carry flag
P r
RCF Reset carry flag
e t e
RSP
o l
Reset stack pointer
LD
b s
Load
CLR
O Clear

)-
PUSH/POP Push/pop to/from the stack
INC/DEC
t ( s Increment/decrement
TNZ

u c Test negative or zero

CPL, NEG

o d 1 or 2 complement

Pr
MUL Byte multiplication
SLL, SRL, SRA, RLC, RRC Shift and rotate operations

t
SWAP
e e Swap nibbles

o l
b s
12.1.2 Immediate

O Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte
contains the operand value.

Table 91. Immediate instructions

Immediate instruction Function

LD Load
CP Compare
BCP Bit compare
AND, OR, XOR Logical operations
ADC, ADD, SUB, SBC Arithmetic operations

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Instruction set ST7L34 ST7L35 ST7L38 ST7L39

12.1.3 Direct
In direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two sub-modes:
● Direct instructions (short)
The address is a byte, thus requires only one byte after the opcode, but only allows
00 - FF addressing space.
● Direct instructions (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires two
bytes after the opcode.

12.1.4 Indexed (no offset, short, long)

( s )
ct
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three sub-modes:
d u
● Indexed (no offset)
r o
P
There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing
e
●
space.
Indexed (short)
l e t
s o
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE

●
addressing space.
Indexed (long)
O b
-
The offset is a word, thus allowing 64 Kbyte addressing space and requires two bytes
)
(s
after the opcode.

12.1.5 Indirect (short, long) c t

d u
r o
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
P
The pointer address follows the opcode. The indirect addressing mode consists of two sub-
e
l e t
modes:
● Indirect (short)
o
bs
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF
addressing space, and requires 1 byte after the opcode.

O ● Indirect (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte
addressing space, and requires 1 byte after the opcode.

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 ST7L34 ST7L35 ST7L38 ST7L39 Instruction set

12.1.6 Indirect indexed (short, long)

This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two sub-modes:
● Indirect indexed (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE
addressing space, and requires 1 byte after the opcode.
● Indirect indexed (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte
addressing space, and requires 1 byte after the opcode.
( s )
Table 92.
ct
Instructions supporting direct, indexed, indirect and indirect indexed
u
addressing modes

o d
LD
Long and short instructions

Load P r Function

CP Compare
e t e
AND, OR, XOR
o l
Logical operations
ADC, ADD, SUB, SBC
b sArithmetic addition/subtraction operations
BCP

- O Bit compare

Table 93.
(s )
Short instructions and functions

c t
Short instructions only Function
u
od
CLR Clear

Pr
INC, DEC Increment/decrement
TNZ Test negative or zero

e t e
CPL, NEG 1 or 2 complement

s ol BSET, BRES Bit operations

O b BTJT, BTJF
SLL, SRL, SRA, RLC, RRC
Bit test and jump operations
Shift and rotate operations
SWAP Swap nibbles
CALL, JP Call or jump subroutine

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Instruction set ST7L34 ST7L35 ST7L38 ST7L39

12.1.7 Relative mode (direct, indirect)

This addressing mode is used to modify the PC register value, by adding an 8-bit signed
offset to it.

Table 94. Relative mode instructions (direct and indirect)

Available relative direct/indirect instructions Function

JRxx Conditional jump

CALLR Call relative

The relative addressing mode consists of two sub-modes:

● Relative (direct)

( s )
ct
The offset follows the opcode
● Relative (indirect)
The offset is defined in memory, of which the address follows the opcode.
d u
r o
12.2 Instruction groups
e P
l e t
The ST7 family devices use an instruction set consisting of 63 instructions. The instructions

s o
may be subdivided into 13 main groups as illustrated in Table 95.

Table 95. Instruction groups

O b
)-
Load and transfer LD CLR

t(s
Stack operation PUSH POP RSP

uc
Increment/decrement INC DEC

od
Compare and tests CP TNZ BCP

Pr
Logical operations AND OR XOR CPL NEG
Bit operation BSET BRES

e t e
Conditional bit test and branch BTJT BTJF

o l Arithmetic operations ADC ADD SUB SBC MUL

b s Shift and rotates SLL SRL SRA RLC RRC SWAP SLA

O Unconditional jump or call

Conditional branch
JRA
JRxx
JRT JRF JP CALL CALLR NOP RET

Interruption management TRAP WFI HALT IRET

Condition code flag modification SIM RIM SCF RCF

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 ST7L34 ST7L35 ST7L38 ST7L39 Instruction set

12.2.1 Using a prebyte

The instructions are described with one to four bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:

PC-2 End of previous instruction

PC-1 Prebyte
PC Opcode
PC+1
( s )
Additional word (0 to 2) according to the number of bytes required to compute
the effective address

u ct
These prebytes enable instructions in Y as well as indirect addressing modes to be

o d
implemented. They precede the opcode of the instructions in X or the instructions using
direct addressing mode. The prebytes are:
P r
PDY 90
t e
Replaces an X based instruction using immediate, direct, indexed, or inherent
e
addressing mode by a Y one
o l
PIX 92
s
Replaces an instruction using direct, direct bit, or direct relative addressing mode
b
by an instruction using the corresponding indirect addressing mode

- O
It also changes an instruction using X indexed addressing mode to an instruction

)
using indirect X indexed addressing mode

(s
PIY 91
t
Replaces an instruction using X indirect indexed addressing mode by a Y one

c
12.2.2
d
Illegal opcode reset u
r o
In order to provide the device with enhanced robustness against unexpected behavior, a
P
system of illegal opcode detection is implemented. If a code to be executed does not

e
l e t
correspond to any opcode or prebyte value, a reset is generated. This, combined with the
watchdog, allows the detection and recovery from an unexpected fault or interference.

s
Note:
o A valid prebyte associated with a valid opcode forming an unauthorized combination does

O b not generate a reset.

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Instruction set ST7L34 ST7L35 ST7L38 ST7L39

Table 96. Instruction set overview

Mnemo. Description Function/example Dst Src H I N Z C

ADC Add with carry A=A+M+C A M H N Z C

ADD Addition A=A+M A M H N Z C
AND Logical and A=A.M A M N Z
BCP Bit compare A, memory tst (A . M) A M N Z
BRES Bit reset bres Byte, #3 M
BSET Bit set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M

( s )
C
CALL Call subroutine
c t
CALLR Call subroutine relative
d u
ro
CLR Clear reg, M 0 1
CP Arithmetic compare tst(Reg - M) reg M

e P N Z C

let
CPL One complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt
s o 0
IRET Interrupt routine return Pop CC, A, X, PC
O b H I N Z C
INC Increment inc X

) - reg, M N Z
JP Absolute jump
s
jp [TBL.w]

t (
JRA
JRT
Jump relative always
Jump relative
u c
o d
Pr
JRF Never jump jrf *
JRIH Jump if ext. interrupt = 1
JRIL

e t e
Jump if ext. interrupt = 0

ol
JRH Jump if H = 1 H=1?

bs
JRNH Jump if H = 0 H=0?

O
JRM
JRNM
Jump if I = 1
Jump if I = 0
I=1?
I=0?
JRMI Jump if N = 1 (minus) N=1?
JRPL Jump if N = 0 (plus) N=0?
JREQ Jump if Z = 1 (equal) Z=1?
JRNE Jump if Z = 0 (not equal) Z=0?
JRC Jump if C = 1 C=1?
JRNC Jump if C = 0 C=0?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=

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ST7L34 ST7L35 ST7L38 ST7L39 Instruction set

Table 96. Instruction set overview (continued)

Mnemo. Description Function/example Dst Src H I N Z C

JRUGT Jump if (C + Z = 0) Unsigned >

JRULE Jump if (C + Z = 1) Unsigned <=
LD Load dst <= src reg, M M, reg N Z
MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0
NEG Negate (2's compl) neg $10 reg, M N Z C
NOP No operation
OR OR operation A=A+M A M N Z

POP Pop from the stack

pop reg reg M

( s )
ct
pop CC CC M H I N Z C
PUSH Push onto the stack push Y M reg, CC

d u
RCF Reset carry flag C=0
ro 0
RET Subroutine return

e P
RIM
RLC
Enable interrupts
Rotate left true C
I=0
C <= Dst <= C reg, M
l e t 0
N Z C

o
bs
RRC Rotate right true C C => Dst => C reg, M N Z C
RSP Reset stack pointer S = Max allowed
SBC Subtract with carry A=A-M-C
- O A M N Z C

)
t(s
SCF Set carry flag C=1 1
SIM Disable interrupts I=1 1
SLA Shift left arithmetic
u c
C <= Dst <= 0 reg, M N Z C
d
ro
SLL Shift left logic C <= Dst <= 0 reg, M N Z C
SRL

e P
Shift right logic 0 => Dst => C reg, M 0 Z C

let
SRA Shift right arithmetic Dst7 => Dst => C reg, M N Z C
SUB Subtraction A=A-M A M N Z C

s
SWAP o SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z

Ob
TNZ
TRAP
Test for neg & zero
S/W trap
tnz lbl1
S/W interrupt 1
N Z

WFI Wait for Interrupt 0

XOR Exclusive OR A = A XOR M A M N Z

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

13 Electrical characteristics

13.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

13.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).

( s )
Data based on characterization results, design simulation and/or technology characteristics

u ct
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3σ).
o d
13.1.2 Typical values
P r
t e
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V (for the
e
o l
4.5 V ≤ VDD ≤ 5.5 V voltage range) and VDD = 3.3 V (for the 3 V ≤ VDD ≤ 3.6 V voltage
range). They are given only as design guidelines and are not tested.

b s
13.1.3 Typical curves
- O
not tested.
(s )
Unless otherwise specified, all typical curves are given only as design guidelines and are

c t
13.1.4 Loading capacitor
d u
o
The loading conditions used for pin parameter measurement are shown in Figure 70.
r
P
Figure 70. Pin loading conditions
e
l e t
s o ST7 pin

O b CL

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 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

13.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 71.

Figure 71. Pin input voltage

ST7 pin

VIN

( s )
13.2 Absolute maximum ratings
u ct
o d
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage

P r
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

e t e
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

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Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

13.2.1 Voltage characteristics

Table 97. Voltage characteristics

Symbol Ratings Maximum value Unit

VDD - VSS Supply voltage 7.0

V
(1)(2)
VIN Input voltage on any pin VSS - 0.3 to VDD + 0.3
VESD(HBM) Electrostatic discharge voltage (human body model) See Section 13.7.3: Absolute
maximum ratings (electrical
VESD(MM) Electrostatic discharge voltage (machine model) sensitivity) on page 198
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted program counter). To guarantee safe operation, this connection must be made through a pull-up

s )
or pull-down resistor (typical: 4.7 kΩ for RESET, 10 kΩ for I/Os). Unused I/O pins must be tied in the same

(
ct
way to VDD or VSS according to their reset configuration.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

d u
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain

o
pads, there is no positive injection current and the corresponding VIN maximum must always be respected

r
13.2.2 Current characteristics
e P
Table 98. Current characteristics
l e t
o
bs
Symbol Ratings Maximum value Unit

IVDD
IVSS
- O
Total current into VDD power lines (source)(1)
Total current out of VSS ground lines (sink)(1)
150
150

( s )
Output current sunk by any standard I/O and control pin 20 mA
IIO
c t
Output current sunk by any high sink I/O pin 40

d u
Output current source by any I/Os and control pin - 25

o
Pr
Injected current on RESET pin ±5
IINJ(PIN) (2)(3) Injected current on OSC1 and OSC2 pins ±5 mA

e t e Injected current on any other pin (4)

±5

o l ΣIINJ(PIN)(2) Total injected current (sum of all I/O and control pins)(4) ± 20 mA

b s 1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.

O 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
3. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents
throughout the device including the analog inputs. To avoid undesirable effects on the analog functions,
care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the
analog voltage is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6 mA. In addition, it is recommended to inject
the current as far as possible from the analog input pins.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.

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 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

13.2.3 Thermal characteristics

Table 99. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150 °C

Maximum junction temperature (see Table 129: Thermal characteristics on
TJ
page 214)

( s )
u ct
o d
P r
e t e
o l
b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

13.3 Operating conditions

13.3.1 General operating conditions

TA = -40 to +125 °C unless otherwise specified.

Table 100. General operating conditions

Symbol Parameter Conditions Min. Max. Unit

fOSC = 16 MHz max.

VDD Supply voltage 3.0 5.5 V
TA = -40°C to TA max.
VDD = 3 to 3.3 V 0 8.8 MHz
fCLKIN External clock frequency on CLKIN pin
VDD = 3.3 to 5.5 V 0 16

( s ) MHz

ct
A suffix version +85
TA Ambient temperature range -40 °C
C suffix version

d u +125

r o
Figure 72. fCLKIN maximum operating frequency vs VDD supply voltage

e P
fCLKIN [MHz]
l e t Functionality guaranteed
in this area (unless
otherwise stated in the

s o tables of parametric data)

Refer to Section 13.3.4:

16

O b Internal RC oscillator and

PLL for PLL operating
range
Functionality
not guaranteed

) -
(s
in this area

8.8

c t
4

d u
1
0
r o Supply voltage [V]

e P 2.0 2.7 3.0 3.3 3.5 4.0 4.5 5.0 5.5

e t
1. For further information on clock management block diagram for fCLKIN description, refer to Figure 13: Clock management

l
block diagram on page 40.

s o
O b

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ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

The RC oscillator and PLL characteristics are temperature-dependent.

Table 101. Operating conditions (tested for TA = -40 to +125 °C) @ VDD = 4.5 to 5.5 V
Flash ROM
Symbol Parameter Conditions Unit
Min. Typ. Max. Min. Typ. Max.

RCCR = FF (reset value),

630 630
Internal RC oscillator TA = 25 °C, VDD = 5 V
fRC(1) kHz
frequency RCCR = RCCR0(2),
930 1000 1050 TBD 1000 TBD
TA = -40 to 125 °C, VDD = 5 V
RC resolution VDD = 5 V -1 +1 TBD TBD

ACCRC Accuracy of internal

TA = -40 to +125 °C,
VDD = 5 V
-3 +5 TBD
( s )
TBD
%

ct
RC oscillator with
RCCR = RCCR0(2)(3) TA = -40 to +125 °C,

du
-4.5 +6.5 TBD TBD
VDD = 4.5 V to 5.5 V(4)

r o
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.
2. See Section 7.1: Internal RC oscillator adjustment on page 37

e P
t
3. Minimum value is obtained for hot temperature and maximum value is obtained for cold temperature

e
ol
4. Data based on characterization results, not tested in production

b s
Table 102. Operating conditions (tested for TA = -40 to +125 °C) @ VDD = 4.5 to 5.5 V

O
)-
Flash and ROM
Symbol Parameter Conditions Unit

t ( s Min. Typ. Max.

IDD(RC)

u c
RC oscillator current consumption
TA = 25 °C, VDD = 5 V
600(1)(2)
10(3)
µA
tsu(RC)
d
RC oscillator setup time

o
µs

Pr
fPLL x8 PLL input clock 1 MHz
tLOCK PLL lock time(4) 2

ete
ms
tSTAB PLL stabilization time(4) 4

ACCPLL
ol x8 PLL accuracy
fCLKIN/2 or fRC = 1 MHz
0.2(5)

bs
@ TA = -40 to +125 °C %
JITPLL PLL jitter (ΔfCPU/fCPU) 1(6)

OIDD(PLL) PLL current consumption TA = 25 °C 550(2) µA

1. Measurement made with RC calibrated at 1 MHz
2. Data based on characterization results, not tested in production
3. See Section 7.1: Internal RC oscillator adjustment on page 37
4. After the LOCKED bit is set ACCPLL is maximum 10% until tSTAB has elapsed. See Figure 12: PLL output frequency timing
diagram on page 38.
5. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy
6. Guaranteed by design

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Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

Figure 73. Typical accuracy with RCCR = RCCR0 vs. VDD = 4.5 to 5.5 V and
temperature

3.00%

2.50%

2.00%

1.50% -45°C
Accuracy (%)

0°C

1.00% 25°C
90°C
110°C
0.50% 130°C

0.00%

( s )
-0.50%

u ct
-1.00%

o d
4.5 5
VDD (V)

P r 5.5

Figure 74. fRC vs. VDD and temperature for calibrated RCCR0
e t e
RCCR0 Typical behavior
o l
1.1
b s
- O
1.05

(s )
c t
u -45°C'
Frequency (MHz)

d
0°C'
25°C'
1

r o 90°C'
110°C'

e P 130°C'

let
0.95

s o
Ob 0.9
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
VDD supply (V)
4.7 4.9 5.1 5.3 5.5 5.7 5.9

Table 103. Operating conditions (tested for TA = -40 to +125 °C) @ VDD = 3.0 to 3.6 V
Flash ROM
Symbol Parameter Conditions Unit
Min. Typ. Max. Min. Typ. Max.

RCCR = FF (reset value),

630 630
Internal RC oscillator TA = 25 °C, VDD = 3.3 V
fRC(1) kHz
frequency RCCR = RCCR(2),
970 1000 1050 TBD 1000 TBD
TA = -40 to +125 °C, VDD = 3.3 V

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 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

Table 103. Operating conditions (tested for TA = -40 to +125 °C) @ VDD = 3.0 to 3.6 V
Flash ROM
Symbol Parameter Conditions Unit
Min. Typ. Max. Min. Typ. Max.

RC resolution VDD = 3.3 V -1 +1 TBD TBD

TA = -40 to +125 °C,
Accuracy of internal V = 3.3 V -3 +5 TBD TBD
ACCRC DD %
RC oscillator with
RCCR = RCCR0(2)(3) TA = -40 to +125 °C, -4 +6 TBD TBD
VDD = 3.0 V to 3.6 V(4)
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.
2. See Section 7.1: Internal RC oscillator adjustment on page 37.

( s )
ct
3. Minimum value is obtained for hot temperature and max. value is obtained for cold temperature.
4. Data based on characterization results, not tested in production.

d u
Table 104. Operating conditions (tested for TA = -40 to +125 °C) @ VDD = 3.0 to 3.6 V(1)
r o
Parameter(1) Conditions
e P Flash and ROM

l e t Min. Typ. Max.

RC oscillator current
o
bs
IDD(RC) 500(2) µA
consumption TA = 25 °C, VDD = 3.3 V
10(2)
tsu(RC) RC oscillator setup time
1. Data based on characterization results, not tested in production.
- O µs

2. Measurement made with RC calibrated at 1 MHz.

( s )
c t
temperature
d u
Figure 75. Typical accuracy with RCCR = RCCR1 vs. VDD = 3 to 3.6 V and

r o
e P 1.50%

l e t
o
1.00%

b s
O 0.50% -45°C
Accuracy (%)

0°C
25°C
90°C
110°C
0.00% 130°C

-0.50%

-1.00%
3 3.3 3.6
VDD (V)

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

Figure 76. fRC vs. VDD and temperature for calibrated RCCR1

RCCR1 Typical behavior

1.1

1.05

-45°C'
Frequency (MHz)

0°C'
25°C'
1
90°C'
110°C'

( s ) 130°C'

0.95

u ct
o d
0.9
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
P
5.1
r 5.3 5.5 5.7 5.9
VDD supply (V)

e t e
o l
Figure 77. PLL x 8 output vs. CLKIN frequency

b s
11.00
- O
)
Output Frequency (MHz)

(s
9.00

c t 7.00 5.5

u 5

od
5.00 4.5

Pr
4
3.00

ete
1.00
0.85 0.9 1 1.5 2 2.5

o l External Input Clock Frequency (MHz)

b s 1. fOSC = fCLKIN/2*PLL8

O13.3.2 Operating conditions with low voltage detector (LVD)

TA = -40 to +125 °C, unless otherwise specified

Table 105. Operating conditions with low voltage detector

Symbol Parameter Conditions(1) Min. Typ. Max. Unit

Reset release threshold

VIT+(LVD) High threshold 3.60(2) 4.15 4.50
(VDD rise)
V
Reset generation threshold High threshold
VIT-(LVD) 3.40 3.95 4.40(2)
(VDD fall)

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 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

Table 105. Operating conditions with low voltage detector

Symbol Parameter Conditions(1) Min. Typ. Max. Unit

Vhys LVD voltage threshold hysteresis VIT+(LVD)-VIT-(LVD) 200 mV

10000
VtPOR VDD rise time rate(3)(4) 20(2) (2) µs/V

tg(VDD) Filtered glitch delay on VDD Not detected by the LVD 150(5) ns
IDD(LVD) LVD/AVD current consumption 200 µA
1. LVD functionality guaranteed only within the VDD operating range specified in Section 13.3.1: General
operating conditions on page 182.
2. Not tested in production.

s )
3. Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on
and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the

(
ct
MCU.
4. Use of LVD with capacitive power supply: With this type of power supply, if power cuts occur in the

d
circuit example in Figure 97: RESET pin protection when LVD is disabled on page 206.u
application, it is recommended to pull VDD down to 0 V to ensure optimum restart conditions. Refer to

5. Based on design simulation.

r o
e P
l e t
s o
O b
) -
c t (s
d u
r o
e P
l e t
s o
O b

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

13.3.3 Auxiliary voltage detector (AVD) thresholds

TA = -40 to +125°C, unless otherwise specified

Table 106. Auxiliary voltage detector (AVD) thresholds

Symbol Parameter Conditions(1) Min. Typ. Max. Unit

1 = >0 AVDF flag toggle threshold

VIT + (AVD) High threshold 3.85(2) 4.45 4.90
(VDD rise)
V
0 = >1 AVDF flag toggle threshold
VIT - (AVD) High threshold 3.80 4.40 4.85(2)
(VDD fall)
Vhys AVD voltage threshold hysteresis VIT + (AVD) - VIT - (AVD) 150 mV

ΔVIT-
Voltage drop between AVD flag set
and LVD reset activation
VDD fall 0.45
( s ) V

c t
1. LVD functionality guaranteed only within the VDD operating range specified in Figure 70: Pin loading
conditions on page 178

d u
2. Not tested in production

r o
13.3.4 Internal RC oscillator and PLL
e P
e t
ol
The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by
option byte).

Table 107. Internal RC oscillator and PLL

b s
O
)-
Symbol Parameter Conditions Min. Typ. Max. Unit

t(s
Internal RC Oscillator operating Refer to operating
VDD(RC) 3.0 5.5
voltage range of VDD with TA,

uc
Figure 70: Pin V
loading conditions on

od
VDD(x8PLL) x8 PLL operating voltage 3.6 5.5
page 178

P r
e t e
o l
b s
O

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 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

13.4 Supply current characteristics

The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To
obtain the total device consumption, the two current values must be added (except for halt
mode for which the clock is stopped).

13.4.1 Supply current

TA = -40 to +125°C, unless otherwise specified

Table 108. Supply current

Symbol Parameter Conditions

fCPU = 8 MHz(2)
Typ. Max.

( s ) Unit

ct
Supply current in run mode 6 9
Supply current in wait mode fCPU = 8 MHz(3) 2.4 4

du
(1)
IDD mA
Supply current in slow mode fCPU = 250 kHz(4) 0.7 1.1
Supply current in slow wait mode fCPU = 250 kHz(5)
r o 0.6 1

e P
-40°C ≤ TA ≤ +85°C 10
Supply current in halt mode(6)
t
IDD (1)
<1 µA
-40°C ≤ TA ≤ +125°C
l e 50

so
Supply current in AWUFH -40°C ≤ TA ≤ +85°C 50
IDD (1)
20 µA
mode(7)(8)(9)

IDD Supply current in active halt mode

O b (1)
-40°C ≤ TA ≤ +125°C
-40°C ≤ TA ≤ +125°C 0.7
300
1 mA
1. VDD = 5.5 V
) -
t (s
2. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all

c
peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

d u
3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock
input (CLKIN) driven by external square wave, LVD disabled.

r o
4. Slow mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave,

P
LVD disabled.

e
t
5. Slow-wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static
value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square

o l e wave, LVD disabled.

6. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on

b s characterization results, tested in production at VDD max. and fCPU max.

7. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max.

O and fCPU max.

8. This consumption refers to the Halt period only and not the associated run period which is software
dependent.
9. If low consumption is required, AWUFH mode is recommended.

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

Figure 78. Typical IDD in run mode vs. fCPU

8MHz
7.0
6.0 4MHz

D
5.0 1MHz

Idd (mA)
TB
4.0
3.0
2.0
1.0
0.0
2.4 2.7 3.3 4 5 6
Vdd (V)

( s )
ct
Figure 79. Typical IDD in slow mode vs. fCPU

1000.00 8MHz

d u
800.00 4MHz

r o
P
Idd (µA)

600.00 1MHz

400.00 D
t e
TB
200.00

0.00
o l e
bs
2.4 2.7 3.3 4 5 6
Vdd (V)

- O
s
Figure 80. Typical IDD in wait mode vs. fCPU
( )
c t
d u 2.5
8MHz

4MHz

o 2.0

Pr
1MHz
Idd (mA)

1.5
1.0

e t e 0.5

l 0.0

so
2.4 2.7 3.3 4 5 6
Vdd (V)

O b

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ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

Figure 81. Typical IDD in slow-wait mode vs. fCPU

8MHz
800.00
700.00 4MHz
600.00 1MHz
500.00

Idd (µA)
400.00
300.00
200.00
100.00
0.00
2.4 2.7 3.3 4 5 6
Vdd (V)

( s )
ct
Figure 82. Typical IDD vs. temperature at VDD = 5 V and fCLKIN = 16 MHz

6.00

d u
5.00

r RUN o
4.00

e P WAIT
Idd (mA)

t
SLOW
3.00

2.00
l e SLOW-WAIT
D
1.00
s o
TB

0.00
-45
O b 25 90 110

) - Temperature (°C)

c t (s
u
Figure 83. Typical IDD vs. temperature and VDD at fCLKIN = 16 MHz

d
r o 6.00

e P 5.00

let
Idd RUN (mA)

4.00
5
3.00 3.3

s o 2.00
2.7

Ob 1.00

0.00
-45 25 90 130
Temperature (°C)

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

13.4.2 On-chip peripherals

Table 109. On-chip peripherals

Symbol Parameter Conditions Typ. Unit

fCPU = 4 MHz VDD = 3.0 V 150

IDD(AT) 12-bit autoreload timer supply current(1)
fCPU = 8 MHz VDD = 5 V 1000
fCPU = 4 MHz VDD = 3.0 V 50
IDD(SPI) SPI supply current(2) µA
fCPU = 8 MHz VDD = 5 V 200
VDD = 3.0 V 250
IDD(ADC) ADC supply current when converting(3) fADC = 4 MHz
VDD = 5 V
LINSCI supply current when
1100

( s )
ct
IDD(LINSCI) fCPU = 8 MHz VDD = 5.0V 650 µA
transmitting(4)

running in PWM mode at fCPU = 8 MHz.

d u
1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer

r o
2. Data based on a differential IDD measurement between reset configuration and a permanent SPI master
communication (data sent equal to 55h).

e P
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.

l e t
4. Data based on a differential IDD measurement between LINSCI running at maximum speed configuration

pad toggling consumption.

s o
(500 Kbaud, continuous transmission of AA +RE enabled and LINSCI off. This measurement includes the

O b
) -
c t (s
d u
r o
e P
l e t
s o
O b

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 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

13.5 Clock and timing characteristics

Subject to general operating conditions for VDD, fOSC and TA.

13.5.1 General timings

Table 110. General timings

Symbol Parameter(1) Conditions Min. Typ.(2) Max. Unit

2 3 12 tCPU
tc(INST) Instruction cycle time
250 375 1500 ns
fCPU = 8 MHz
Interrupt reaction time(3) 10 22 tCPU
tv(IT)
tv(IT) = Δtc(INST) + 10 1.25
(
2.75
s ) µs
1. Guaranteed by design. Not tested in production.

u ct
d
2. Data based on typical application software.

needed to finish the current instruction execution.

r o
3. Time measured between interrupt event and interrupt vector fetch. Dtc(INST) is the number of tCPU cycles

e P
l e t
s o
O b
) -
c t (s
d u
r o
e P
l e t
s o
O b

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

13.5.2 Crystal and ceramic resonator oscillators

The ST7 internal clock can be supplied with four different crystal/ceramic resonator
oscillators. All the information given in this paragraph are based on characterization results
with specified typical external components. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, package, accuracy...).

Table 111. Oscillator parameters

Symbol Parameter Conditions Min. Typ. Max. Unit

fCrOSC Crystal oscillator frequency(1) 2 16 MHz

Recommended load capacitance
See Table 112: Typical
( s )
ct
CL1 versus equivalent serial
ceramic resonator pF
CL2 resistance of the crystal or
ceramic resonator (RS)
d u
characteristics

r o
1. When PLL is used, please refer to Section 7: Supply, reset and clock management (fCrOSC min. is 8 MHz
with PLL).

e P
Table 112. Typical ceramic resonator characteristics
Typical ceramic resonators(1)
l e t
Supplier
fCrOSC

s o CL1
[pF]
CL2
[pF]
Supply voltage
range (V)
b
(MHz) Reference(2) Oscillator modes

2 CSTCC2M00G56-R0
- O LP or MP (47) (47)

Murata
4

(s )
CSTCR4M00G55-R0 MP or MS (39) (39)
3.0 V to 5.5 V
8

c t
CSTCE8M00G55-R0 MS or HS (33) (33)
16

d uCSTCE16M0V53-R0 HS (15) (15)

o
1. Resonator characteristics given by the ceramic resonator manufacturer. For more information on these

P r
resonators, please consult www.murata.com
2. SMD = [-R0: Plastic tape package (∅ = 180mm), -B0: Bulk]

e t e
o l
b s
O

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 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

13.6 Memory characteristics

13.6.1 RAM and hardware registers

TA = -40 to +125 °C, unless otherwise specified.

Table 113. RAM and hardware registers

Symbol Parameter Conditions Min. Typ. Max. Unit

VRM Data retention mode(1) Halt mode (or reset) 1.6 V

1. Minimum VDD supply voltage without losing data stored in RAM (in halt mode or under reset) or in
hardware registers (only in halt mode). Not tested in production.

13.6.2 Flash program memory

( s )
TA = -40 to +85°C, unless otherwise specified.
u ct
o d
Table 114. Characteristics of dual voltage HDFlash memory
Symbol Parameter Conditions
P r Min. Typ. Max. Unit

Refer to operating range of

e t e
VDD
write/erase
o l
Operating voltage for Flash VDD with TA, Section 13.3.1:
General operating conditions
3.0 5.5 V
on page 182
b s
Programming time for 1~32
bytes(1)
- O
TA = −40 to +85 °C 5 10 ms
tprog

(s
Programming time for 1.5
) TA = 25 °C 0.24 0.48 s

tRET(2)
Kbytes

c t TA = 55 °C(3)
u
Data retention 20 Years

od
TPROG = 25 °C 1K

Pr
NRW Write erase cycles Cycles
TPROG = 85 °C 300

ete
Read/write/erase modes
2.6(4) mA
fCPU = 8 MHz, VDD = 5.5 V

ol
IDD Supply current
No read/no write mode 100

b s Power down mode/halt 0 0.1

µA

O 1. Up to 32 bytes can be programmed at a time

2. Data based on reliability test results and monitored in production
3. The data retention time increases when the TA decreases
4. Guaranteed by design. Not tested in production

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

13.6.3 EEPROM data memory

TA = -40 to +125°C, unless otherwise specified.

Table 115. Characteristics of EEPROM data memory

Symbol Parameter Conditions Min. Typ. Max. Unit

Refer to operating
range of VDD with TA,
Operating voltage for EEPROM Section 13.3.1:
VDD 3.0 5.5 V
write/erase General operating
conditions on
page 182

(s)
tprog Programming time for 1~32 bytes TA = −40 to +125 °C 5 10 ms
Data retention with 1 k cycling
(TPROG = −40 to +125 °C
20
c t
u
od
Data retention with 10 k cycling
tRET(1) TA = 55 °C(2) 10 Years
(TPROG = −40 to +125 °C)
Data retention with 100 k cycling
P r 1
(TPROG = −40 to +125 °C)

e t e
2. The data retention time increases when the TA decreases
o l
1. Data based on reliability test results and monitored in production

b s
13.7 O (EMC) characteristics
Electromagnetic compatibility
-
s )
Susceptibility tests are performed on a sample basis during product characterization.
(
13.7.1 c t
Functional electromagnetic susceptibility (EMS)
d u
r o
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
P
LEDs). See Table 116: Electromagnetic test results on page 197.

ete
● ESD: Electro-static discharge (positive and negative) is applied on all pins of the device

o l until a functional disturbance occurs. This test conforms with the

IEC 1000 - 4 - 2 standard.

b s ● FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS

O through a 100pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000 - 4 - 4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.

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 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
● Corrupted program counter
● Unexpected reset
● Critical data corruption (control registers...)

( s )
ct
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
d u
reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1
second.
r o
P
To complete these trials, ESD stress can be applied directly on the device, over the range of
e
l e t
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Table 116. Electromagnetic test results

s o
Symbol Parameter
O b Conditions
Level/

) - class

(s
Voltage limits to be applied on any I/O pin VDD = 5 V, TA = 25 °C, fOSC = 8 MHz,
VFESD

c t
to induce a functional disturbance conforms to IEC 1000-4-2

VFFTB
d u
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VDD
VDD = 5 V, TA = 25 °C, fOSC = 8 MHz,
3B

r o
pins to induce a functional disturbance
conforms to IEC 1000-4-4

e P
13.7.2
l e t
Electromagnetic interference (EMI)

s o Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the

O b norm SAE J 1752/3 which specifies the board and the loading of each pin. See Table 117:
EMI emissions on page 197.

Table 117. EMI emissions

Max. vs. [fOSC/fCPU]
Monitored
Sym. Parameter Conditions Unit
frequency band
8/4 MHz 16/8 MHz

0.1MHz to 30 MHz 15 15
VDD = 5 V, TA = 25 °C, 30 MHz to 130 MHz 13 19 dBµV
Peak
SEMI SO20 package,
level(1)
conforming to SAE J 1752/3 130 MHz to 1 GHz 9 13
SAE EMI level 2.5 3 -
1. Data based on characterization results, not tested in production.

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

13.7.3 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, DLU and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: the human body model and the machine model. This test conforms to the
JESD22-A114A/A115A standard.

Table 118. ESD absolute maximum ratings

( s )
Symbol Ratings Conditions

u ct
Maximum value(1) Unit

VESD(HBM)
Electro-static discharge voltage
(Human body model)
o d 4000

VESD(MM)
Electro-static discharge voltage
(Machine model)
TA = +25 °C
P r 400 V

Electro-static discharge voltage

e t e
VESD(CDM)
(Charged device model)
o l 1000

s
1. Data based on characterization results, not tested in production

b
Static and dynamic latch-up (LU)
- O
(s )
LU: Three complementary static tests are required on 10 parts to assess the latch-up

c t
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each

d u
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer

o
to application note AN1181.
r
e P
DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin
of three samples when the micro is running to assess the latch-up performance in dynamic

l e t
mode. Power supplies are set to the typical values, the oscillator is connected as near as
possible to the pins of the micro and the component is put in reset mode. This test conforms

s o to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application

O b note AN1181.

Electrical sensitivities

Table 119. Latch up results

Symbol Parameter Conditions Class(1)

TA = 25 °C
LU Static latch-up class
TA = 125 °C A
DLU Dynamic latch-up class VDD = 5.5 V, fOSC = 4 MHz, TA = 25 °C
1. Class description: A class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, which means when a device belongs to class A it exceeds the JEDEC standard.
Class B strictly covers all the JEDEC criteria (international standard). Class B strictly covers all the JEDEC
criteria (international standard)

198/234 Doc ID 11928 Rev 8

ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

13.8 I/O port pin characteristics

13.8.1 General characteristics

Subject to general operating conditions for VDD, fOSC, and TA (-40 to +125°C), unless
otherwise specified.

Table 120. I/O general port pin characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

VIL Input low level voltage VSS - 0.3 0.3 x VDD

V
VIH Input high level voltage 0.7 x VDD VDD + 0.3

Vhys
Schmitt trigger voltage
400
( s ) mV

ct
hysteresis(1)
VSS ≤ VIN ≤ VDD

du
IL Input leakage current ±1
Static current consumption
IS induced by each floating Floating input mode
r o 400
µA

input pin(2)

e P
RPU
Weak pull-up equivalent
resistor(3)
VIN = VSS, VDD = 5 V

l e t 50 100 170 kΩ

so
CIO I/O pin capacitance 5 pF

tf(IO)out
Output high to low level fall
time(1)
O b
CL = 50 pF

)-
25 ns
Output low to high level rise between 10% and 90%
tr(IO)out (1)
time

t ( s
External interrupt pulse
tw(IT)in
time(4)
u c 1 tCPU

d
1. Data based on characterization results, not tested in production

o
P r
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: Using the output mode of
the I/O for example or an external pull-up or pull-down resistor (see Figure 84). Static peak current value
taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in

e t e
production. This value depends on VDD and temperature values

o l 3. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current
characteristics described in Figure 84: Two typical applications with unused I/O pin on page 199)

bs
4. To generate an external interrupt, a minimum pulse width must be applied on an I/O port pin configured as
an external interrupt source.

O Figure 84. Two typical applications with unused I/O pin

VDD ST7
Unused I/O port
10kΩ
10kΩ
Unused I/O port
ST7

1. I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

Caution: During normal operation the ICCCLK pin must be pulled up, internally or externally (external
pull-up of 10 k mandatory in noisy environments). This is to avoid entering ICC mode
unexpectedly during a reset.

Figure 85. Typical IPU vs. VDD with VIN = VSS

90

80 Ta=140°C

Ta=95°C
70 Ta=25°C
Ta=-45°C
60

50

Ipu(uA)
TO BE CHARACTERIZED

)
40

30

( s
20

10
u ct
0

o d
2 2.5 3 3.5 4
Vdd(V)
4.5 5 5.5

P r 6

e t e
13.8.2 Output driving current
o l
s
Subject to general operating conditions for VDD, fOSC, and TA (-40 to +125 °C) unless otherwise specified.
b
Table 121. Output driving current
- O
Symbol Parameter

(s ) Conditions Min. Typ. Max. Unit

ct
Output low level voltage for a IIO = +5 mA 1.0
standard I/O pin when eight pins are

du
sunk at same time (see Figure 88) IIO = +2 mA 0.4
VOL(1)

r o
Output low level voltage for a high IIO = +20 mA 1.4

P
sink I/O pin when four pins are sunk
at same time (see Figure 94)
e
VDD = 5 V
IIO = +8 mA 0.75
V

e t
Output high level voltage for an I/O IIO = -5 mA VDD - 1.5

ol
VOH(2) pin when four pins are sourced at
IIO = -2 mA VDD - 1.0

b s same time (see Figure 94)

1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2: Current characteristics

O on page 180 and the sum of IIO (I/O ports and control pins) must not exceed IVSS
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2: Current
characteristics on page 180 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.

200/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

Figure 86. Typical VOL at VDD = 3 V

-45°C
4.0 25°C
3.5 90°C
110°C

VOL(V) at VDD = 3V
3.0 130°C
2.5

D
2.0

TB
1.5
1.0
0.5
0.0
0.01 1 2 3 4 5 6
lio (m A)

( s )
ct
Figure 87. Typical VOL at VDD = 4 V

1.2
-45°C
d u
o
25°C

r
90°C
1.0 110°C
VOL(V) at VDD = 4V

0.8
130°C

e P
0.6

0.4

l e t
o
D
0.2

s
TB

b
0.0
0.01 1 2 3 4 5 6

- Olio (m A)

(s )
Figure 88. Typical VOL at VDD = 5 V
c t
u
od
-45°C
1.0 25°C

P r 0.9 90°C
110°C
VOL(V) at VDD = 5V

0.8
0.7
130°C

e te 0.6
0.5

l
0.4
0.3

o
D

0.2

s 0.1
TB

O b 0.0
0.01 1 2 3
lio (m A)
4 5 6

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

Figure 89. Typical VOL at VDD = 3 V (high-sink)

-45°C
1.2 25°C
90°C

VOL(V) at VDD = 3V (HS)

1.0 110°C
130°C
0.8

0.6

0.4

D
0.2

TB
0.0
5 8 10 15
lio (m A)

( s )
ct
Figure 90. Typical VOL at VDD = 4 V (high-sink)

-45°C
d u
o
0.9 25°C
90°C
r
VOL(V) at VDD = 4V (HS)

0.8
110°C
0.7
0.6
130°C

e P
t
0.5

e
0.4
0.3

l
D
0.2
0.1

s o
TB

0.0
5 8

O b lio (m A)
10 15

) -
c
Figure 91. Typical VOL at VDD = 5 V (high-sink) t (s
d u
r o 0.8
-45°C
25°C

P 90°C
VOL (V) at VDD = 5V (HS)

0.7
110°C
0.6 130°C

e
let
0.5
0.4

so
0.3
D

0.2

b
TB

0.1

O
0.0
5 8 10 15
lio (m A)

202/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

Figure 92. Typical VDD - VOH at VDD = 3 V

-45°C
1.8 25°C
1.6 90°C

VDD - VOH at VDD = 3V

1.4
110°C
130°C
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.01 -1 -2 -3 -4
lio (m A)

( s )
Figure 93. Typical VDD - VOH at VDD = 4 V
u ct
o d
r
-45°C
2.0 25°C
1.8 90°C
P
VDD - VOH at VDD = 4V

1.6 110°C

e
1.4 130°C
1.2
1.0

l e t
o
0.8

s
0.6
D
0.4
0.2
b
TB

O
0.0
-0.01 -1 -2 -3 -4 -5 -6

) - lio (m A)

c t (s
u
Figure 94. Typical VDD - VOH at VDD = 5 V
d
r o -45°C

P 1.8
1.6
25°C
90°C
VDD - VOH at VDD = 5V

e te 1.4
1.2
110°C
130°C

o l 1.0
0.8

s
D

0.6

b 0.4
TB

O
0.2
0.0
-0.01 -1 -2 -3 -4 -5 -6
lio (m A)

Doc ID 11928 Rev 8 203/234

 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

Figure 95. Typical VOL vs. VDD (standard I/Os)

-45°C
0.5 25°C
0.4 90°C
110°C

Vol (V) at llo = 2mA

0.4
130°C
0.3
0.3

D
0.2

TB
0.2
0.1
0.1
0.0
3 4 5
VDD (V)

( s )
Typical VOL vs. VDD (standard I/Os)
u ct
o d
r
-45°C -45°C
0.4 25°C 1.2 25°C
90°C

P
90°C

Vol (V) at llo = 15mA (HS)

Vol (V) at llo = 5mA (HS)

0.3 1.0 110°C

110°C
0.3 130°C 130°C

e
D
0.8
0.2

t 0.6
TB

0.2
0.1

o l e 0.4

0.2

bs
0.1
0.0 0.0
3 4 5 3 4 5

O
VDD (V) VDD (V)

) -
Figure 96. Typical VDD - VOH vs. VDD
t ( s
u c
4.0

o d -45°C
25°C
0.7 -45°C
25°C
VDD - VOH (V) at llo = -2mA
VDD - VOH (V) at llo = -5mA

90°C

Pr
3.5 0.6 90°C
110°C 110°C
3.0 130°C 130°C
0.5
D

2.5
0.4
2.0
TB

e
0.3

t
1.5
0.2
1.0

l e 0.5
0.0
0.1

so
0.0
3 4 5 3 4 5
VDD (V) VDD (V)

O b

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 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

13.9 Control pin characteristics

13.9.1 Asynchronous RESET pin

TA = -40 to +125 °C, unless otherwise specified.

Table 122. Asynchronous RESET pin

Symbol Parameter Conditions Min. Typ. Max. Unit

VIL Input low-level voltage Vss - 0.3 0.3 x VDD

VIH Input high-level voltage 0.7 x VDD VDD + 0.3
Vhys Schmitt trigger voltage hysteresis(1) 1
IIO = +5 mA,
( s
1.0(2)
)
ct
V
TA ≤ +85 °C 0.5
1.2(2)
TA ≤ +125 °C
VOL Output low-level voltage(1) VDD = 5 V
IIO = +2 mA,
d u
TA ≤ +85 °C
r o
0.45
0.7(2)
0.9(2)

resistor(1)(3)
TA ≤ +125 °C

e P
RON
tw(RSTL)out
Pull-up equivalent
Generated reset pulse duration
VDD = 5 V
Internal reset sources
l e t 10 39
30
70 kΩ

th(RSTL)in External reset pulse hold time(4)

s o 20
µs

tg(RSTL)in Filtered glitch duration

O b 200 ns

) -
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2: Current characteristics
on page 180 and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. Guaranteed by design. Not tested in production.

c t (s
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax

u
and VDD.

o d
4. To guarantee the reset of the device, a minimum pulse must be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.

P r
RESET circuit design recommendations

e t e
o l The reset network protects the device against parasitic resets. The output of the external
reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the

b s device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the
O RESET pin can go below the VIL level specified in Section 13.9.1: Asynchronous RESET pin
on page 205. Otherwise the reset is not taken into account internally. Because the reset
circuit is designed to allow the internal reset to be output in the RESET pin, the user must
ensure that the current sunk on the RESET pin is less than the absolute maximum value
specified for IINJ(RESET) in Section 13.2.2: Current characteristics on page 180.
Refer to Section 12.2.2: Illegal opcode reset on page 175 for details on illegal opcode reset
conditions.

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 Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

RESET pin protection when LVD is disabled

Figure 97. RESET pin protection when LVD is disabled

VDD ST7

RON
User
external Internal reset
reset Filter
circuit
0.01µF
Watchdog
Pulse
generator Illegal opcode
Required

( s )
RESET pin protection when LVD is enabled
u ct
Figure 98. RESET pin protection when LVD Is enabled
o d
VDD
P r ST7

e t e
Required Optional
(note 3)
RON

o l
bs
External Internal reset
reset Filter

-O
0.01µF
1MΩ Watchdog
Pulse Illegal opcode

)
generator
LVD reset

( s
Note:
u ct
When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A

o d
10nF pull-down capacitor is required to filter noise on the reset line.

P r
If a capacitive power supply is used, it is recommended to connect a 1 MΩ pull-down
resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect

t e
of the power supply (this adds 5 µA to the power consumption of the MCU).
e
o l Tips when using the LVD

b s 1. Check that all recommendations related to reset circuit have been applied (see RESET

O 2.
circuit design recommendations)
Check that the power supply is properly decoupled (100 nF + 10 µF close to the MCU).
Refer to AN1709. If this cannot be done, it is recommended to put a 100 nF + 1MΩ pull-
down on the RESET pin.
3. The capacitors connected on the RESET pin and also the power supply are key to
avoiding any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a
robust solution. Otherwise: replace 10nF pull-down on the RESET pin with a 5 µF to
20 µF capacitor.

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ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

13.10 Communication interface characteristics

13.10.1 Serial peripheral interface (SPI)

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Refer to Section 10: I/O ports for more details on the input/output alternate function
characteristics (SS, SCK, MOSI, MISO).

Table 123. SPI characteristics

Symbol Parameter Conditions Min. Max. Unit

fSCK = 1/ Master, fCPU = 8 MHz fCPU/128 = 0.0625 fCPU/4 = 2

SPI clock frequency
)
tc(SCK) MHz
Slave, fCPU = 8 MHz 0 fCPU/2 = 4

( s
ct
tr(SCK) SPI clock rise and fall See Table 2: Device pin description
time on page 17
tf(SCK)
tsu(SS)(1) SS setup time(2)
d u
th(SS)(1)
Slave
r o
(4 x TCPU) + 50

tw(SCKH)(1)
SS hold time
Master
e P 120
100
tw(SCKL) (1)
SCK high and low time
Slave
l e t 90
tsu(MI)(1)
Data input setup time
Master
s o
tsu(SI)(1)
th(MI)(1)
Slave

O b 100 ns

th(SI)(1)
Data input hold time
) - Master
Slave
ta(SO)(1)

ct (s
Data output access time
Slave
0 120

du
(1)
tdis(SO) Data output disable time 240
tv(SO)(1)

ro
Data output valid time Slave 120
th(SO)(1) (after enable edge)

e P
tv(MO)(1)
Data output hold time
Data output valid time
0
120

let
Master
tCPU
th(MO)(1) Data output hold time (after enable edge) 0

s o 1. Data based on design simulation, not tested in production.

Ob 2. Depends on fCPU. For example, if fCPU = 8 MHz, then tCPU = 1/fCPU = 125 ns and tsu(SS) = 550 ns.

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Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

Figure 99. SPI slave timing diagram with CPHA = 0

SS INPUT

tsu(SS) tc(SCK) th(SS)

CPHA = 0
SCK INPUT

CPOL = 0

CPHA = 0
CPOL = 1
tw(SCKH)
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)
tr(SCK)
tf(SCK)

)
MISO OUTPUT see note 2 MSB OUT BIT6 OUT LSB OUT see note 2

th(SI)
( s
ct
tsu(SI)

MOSI INPUT MSB IN BIT1 IN LSB IN

d u
r o
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD

e P
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.

l e t
Figure 100. SPI slave timing diagram with CPHA = 1
s o
SS INPUT

O b
)-
tsu(SS) tc(SCK)
th(SS)

CPHA = 1

t ( s
SCK INPUT

c
CPOL = 0

CPHA = 1
CPOL = 1
d u
o
Pr
tw(SCKH)
tw(SCKL) tv(SO) th(SO) tdis(SO)
ta(SO) tr(SCK)
tf(SCK)

MISO OUTPUT

e t e HZ MSB OUT BIT6 OUT LSB OUT

o l see note 2
tsu(SI)
th(SI) see note 2

b s MOSI INPUT MSB IN BIT1 IN LSB IN

O
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.

208/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

Figure 101. SPI master timing diagram

SS INPUT

tc(SCK)

CPHA = 0
CPOL = 0
SCK INPUT

CPHA = 0
CPOL = 1

CPHA=1
CPOL=0
CPHA = 1
CPOL = 1
tw(SCKH)
tw(SCKL) tr(SCK)

tsu(MI)
th(MI)
tf(SCK)

( s )
MISO INPUT MSB IN
tv(MO)
BIT6 IN
th(MO)
u
LSB IN
ct
o d
Pr
MOSI OUTPUT see note 2 MSB OUT BIT6 OUT LSB OUT see note 2

1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.

e t e
ol
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends of the I/O port
configuration.

b s
- O
(s )
c t
d u
r o
e P
l e t
s o
O b

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Electrical characteristics ST7L34 ST7L35 ST7L38 ST7L39

13.11 10-bit ADC characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Table 124. 10-bit ADC characteristics

Symbol Parameter Conditions Min.(1) Typ.(2) Max.(1) Unit

fADC ADC clock frequency 0.5 4 MHz

(3)
VAIN Conversion voltage range VSSA VDDA V
RAIN External input resistor 10(4) kΩ
CADC Internal sample and hold capacitor 6 pF
tSTAB Stabilization time after ADC enable 0(5)

( s ) µs

tADC
Conversion time (sample+hold) fCPU = 8 MHz, fADC
= 4 MHz
3.5

c t
- Sample capacitor loading time
- Hold conversion time
d
4
10u 1/fADC

1. Data based on characterization results, not tested in production

r o
as design guidelines and are not tested.
e P
2. Unless otherwise specified, typical data is based on TA = 25 °C and VDD - VSS = 5 V. They are given only

e t
3. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS

ol
4. Any added external serial resistor downgrades the ADC accuracy (especially for resistance greater than

s
10kΩ). Data based on characterization results, not tested in production.

is then always valid.

O b
5. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable

) -
Figure 102. Typical application with ADC

c t (s VDD ST7

u
od
VT
0.6V

Pr
RAIN AINx 10-bit A/D
VAIN conversion

e t e VT
0.6V IL
±1µA
CADC

o l
b s
O Table 125. ADC accuracy with 4.5 V < VDD < 5.5 V
Symbol Parameter Conditions Typ. Max.(1) Unit

|ET| Total unadjusted error 2.0 3.4

|EO| Offset error 0.4 1.7
|EG| Gain error fCPU = 8 MHz, fADC = 4 MHz(2)(3) 0.4 1.5 LSB
|ED| Differential linearity error 1.9 3.1
|EL| Integral linearity error 1.8 2.9
1. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value
from -40 °C to +125 °C (± 3σ distribution limits).

210/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Electrical characteristics

2. Data based on characterization results over the whole temperature range, monitored in production.
3. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins may
reduce the accuracy of the conversion being performed on another analog input.
The effect of negative injection current on robust pins is specified in Section 13.11: 10-bit ADC
characteristics on page 210
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 13.8: I/O port
pin characteristics on page 199 does not affect the ADC accuracy.

Table 126. ADC accuracy with 3 V < VDD < 3.6 V

Symbol Parameter Conditions Typ. Max.(1) Unit

|ET| Total unadjusted error 1.9 3.1

|EO| Offset error 0.3 1.2
|EG| Gain error fCPU = 4 MHz, fADC = 2 MHz(2)(3) 0.3 1
( s ) LSB
|ED| Differential linearity error
c
1.8 t
3
|EL| Integral linearity error
d u1.7 2.8
1. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value
from -40 °C to +125 °C (± 3σ distribution limits).
r o
2. Data based on characterization results over the whole temperature range, monitored in production.

e P
t
3. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins may

e
ol
reduce the accuracy of the conversion being performed on another analog input.
The effect of negative injection current on robust pins is specified in Section 13.11: 10-bit ADC
characteristics on page 210

pin characteristics on page 199 does not affect the ADC accuracy.
b s
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 13.8: I/O port

Figure 103. ADC accuracy characteristics

- O
(s )
Digital result ADCDR

c t
u
EG
1023
1022

o d
1LSB
V
DD
–V
SS
= --------------------------------

r
IDEAL 1024
1021

e P (2)
(1) = Example of an actual transfer curve

let
ET
7 (3)
(1) (2) = Ideal transfer curve
6

so
5 (3) = End point correlation line
EO EL

O b 4
3
2
ED

1 LSBIDEAL
1
Vin (LSBIDEAL)
0 1 2 3 4 5 6 7 10211022 1023 1024
VSS VDD

1. Legend:
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves
EO = Offset error: deviation between the first actual transition and the first ideal one
EG = Gain error: deviation between the last ideal transition and the last actual one
ED = Differential linearity error: maximum deviation between actual steps and the ideal one
EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line

Doc ID 11928 Rev 8 211/234

Package characteristics ST7L34 ST7L35 ST7L38 ST7L39

14 Package characteristics

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.

14.1 Package mechanical data

( s )
ct
Figure 104. 20-pin plastic small outline package, 300-mil width

D h x 45×
d u
L

o
Pr
A c

B A1 α
e

e t e
s ol
O b E H

) -
c t(s
d u
Table 127. 20-pin plastic small outline package, 300-mil width, mechanical data

r o mm inches

e P
Dim.
Min. Typ. Max. Min. Typ. Max.

l e t A 2.35 2.65 0.093 0.104

o
bs
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.020

O C 0.23 0.32 0.009 0.013

D 12.60 13.00 0.496 0.512
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030

α 0° 8° 0° 8°

L 0.40 1.27 0.016 0.050

212/234 Doc ID 11928 Rev 8

ST7L34 ST7L35 ST7L38 ST7L39 Package characteristics

Figure 105. QFN 5x6, 20-terminal very thin fine pitch quad flat no-lead package
D2
D D2/2

Nx L
1

2 E2/2

E (NE - 1) x e E2

1
Pin 1 ID
R0.20 K
2X
e Nx b
2X
See detail A (ND - 1) x e

( s )
ct
Top view Bottom view

A A1
Seating plane

d u
A3
r o
Side view
CL

e P CL

L
l e t L

o
e e

s
e/2
Terminal tip
For odd terminal side

O b For even terminal side

) -
(s
Detail A

c t
Table 128. QFN 5x6: 20-terminal very thin fine pitch quad flat no-lead package
u
od
mm inches
Dim.

P r Min. Typ. Max. Min. Typ. Min.

e t e e 0.80 0.0315

o l L 0.45 0.50 0.55 0.0177 0.0197 0.0217

bs
b(1) 0.25 0.30 0.35 0.0098 0.0118 0.0138
D2 3.30 3.40 3.50 0.1299 0.1339 0.1378
O E2 4.30 4.40 4.50 0.1693 0.1732 0.1772
D 5.00 0.1969
E 6.00 0.2362
A 0.80 0.85 0.90 0.0315 0.0335 0.0354
A1 0.00 0.02 0.05 0.0000 0.0008 0.0020
A3 0.02 0.0008
K 0.20 0.0079
(2)
N 20

Doc ID 11928 Rev 8 213/234

 Package characteristics ST7L34 ST7L35 ST7L38 ST7L39

Table 128. QFN 5x6: 20-terminal very thin fine pitch quad flat no-lead package
ND(3) 4
NE(3) 6
1. Dimension b applies to metallized terminals and is measured between 0.15 and 0.30 mm from terminal
TIP. If the terminal has the optional radius on the other end of the terminal the dimension b should not be
measured in that radius area.
2. N is the total number of terminals
3. ND and NE refer to the number of terminals on each D and E side respectively

14.2 Packaging for automatic handling

The devices can be supplied in trays or with tape and reel conditioning.

( s )
ct
Tape and reel conditioning can be ordered with pin 1 left-oriented or right-oriented when
facing the tape sprocket holes as shown in Figure 106.

d u
Figure 106. pin 1 orientation in tape and reel conditioning
r o
Left orientation
P
Right orientation (EIA 481-C compliant)

e
Pin 1

l e t Pin 1

s o
O b
) -
See also Figure 107: ST7FL3x Flash commercial product structure on page 220 and

c t (s
Figure 108: ST7FL3x FASTROM commercial product structure on page 221.

14.3 d u
Thermal characteristics
r o
P
Table 129. Thermal characteristics

e
l e t Symbol Parameter Package Value Unit

s o RthJA Package thermal resistance (junction to ambient)

SO20
QFN20
70
30
°C/W

O b TJmax Maximum junction temperature(1)

SO20
150 °C
QFN20
SO20 < 350
PDmax Maximum power dissipation(2) mW
QFN20 < 800
1. The maximum chip-junction temperature is based on technology characteristics
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA)/RthJA. The power dissipation of
an application can be defined by the user with the formula: PD = PINT + PPORT, where PINT is the chip
internal power (IDD x VDD) and PPORT is the port power dissipation depending on the ports used in the
application.

214/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Device configuration and ordering information

15 Device configuration and ordering information

15.1 Introduction
Each device is available for production in user programmable versions (Flash) as well as in factory coded
versions (ROM). ST7L3x devices are ROM versions.
ST7PL3x devices are factory advanced service technique ROM (FASTROM) versions: They are factory
programmed Flash devices.
ST7FL3 Flash devices are shipped to customers with a default program memory content (FFh), while
ROM/FASTROM factory coded parts contain the code supplied by the customer. This implies that Flash
devices have to be configured by the customer using the option bytes while the ROM/FASTROM devices
are factory-configured.
( s )
u ct
15.2 Option bytes
o d
P r
The two option bytes allow the hardware configuration of the microcontroller to be selected. Differences
in option byte configuration between Flash and ROM devices are presented in Table 130 and are

t e
described in Section 15.2.1: Flash option bytes on page 216 and Section 15.2.2: ROM option bytes on

e
page 217.

o l
Table 130. Flash and ROM option bytes
b s
Option byte 0
O Option byte 1

)-
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flash
t (1s
SEC SEC
0
FM
PR
FM
PW
Name
AW
UCK
OSCRANGE
2:0
u c ROP ROP
Res
PLL
OFF
Res OSC LVD 1:0
WDG WDG
SW HALT
ROM

o d Res
_R _D

Pr
Default value 1 1 1 1 1 1 0 0 1(1) 1 0(1) 0 1 1 1 1

e t e
1. Contact your STMicroelectronics support

s ol
O b

Doc ID 11928 Rev 8 215/234

 Device configuration and ordering information ST7L34 ST7L35 ST7L38 ST7L39

15.2.1 Flash option bytes

Table 131. Option byte 0 description

Bit Bit name Function
Auto wake up clock selection
0: 32 kHz oscillator (VLP) selected as AWU clock
7 AWUCK 1: AWU RC oscillator selected as AWU clock.
Note: If this bit is reset, the internal RC oscillator must be selected
(option OSC = 0).
Oscillator range
When the internal RC oscillator is not selected (Option OSC = 1),
these option bits select the range of the resonator oscillator current
source or the external clock source.

( s )
ct
000: Typ. frequency range with resonator (LP) = 1~2 MHz
001: Typ. frequency range with resonator (MP) = 2~4 MHz)

6:4
OSCRANGE
u
010: Typ. frequency range with resonator (MS) = 4~8 MHz)

d
011: Typ. frequency range with resonator (HS) = 8~16 MHz)
[2:0]

r o
100: Typ. frequency range with resonator (VLP) = 32.768~ kHz)
101: External clock on OSC1
110: Reserved
e P
111: External clock on PB4

l e t
Note: OSCRANGE[2:0] has no effect when AWUCK option is set to 0.

AWU clock.
s o
In this case, the VLP oscillator range is automatically selected as

b
Sector 0 size definition
O
3:2 SEC[1:0] -
These option bits indicate the size of sector 0 as follows:

)
00: Sector 0 size = 0.5 Kbytes

(s
01: Sector 0 size = 1 Kbyte

c t 10: Sector 0 size = 2 Kbytes

11: Sector 0 size = 4 Kbytes
u
od
Readout protection

P r Readout protection, when selected provides a protection against

program memory content extraction and against write access to Flash
memory.

e t e Erasing the option bytes when the FMP_R option is selected will cause

o l 1 FMP_R the whole memory to be erased first and the device can be
reprogrammed.

b s Refer to the ST7 Flash Programming Reference Manual and

Section 4.5: Memory protection on page 25 for more details.

O 0: Readout protection off

1: Readout protection on
Flash write protection
This option indicates if the Flash program memory is write protected.
Warning: When this option is selected, the program memory (and
the option bit itself) can never be erased or programmed again.
0: Write protection off
0 FMP_W
1: Write protection on
Note: The option bytes have no address in the memory map and are
accessed only in programming mode (for example using a
standard ST7 programming tool). The default content of the Flash
is fixed to FFh.

216/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Device configuration and ordering information

Table 132. Option byte 1 description

Bit Bit name Function
7 - Reserved, must be set to 1(1)
PLL disable
This option bit enables or disables the PLL.
6 PLLOFF
0: PLL enabled
1: PLL disabled (bypassed)
5 - Reserved, must be set to 0(1)
RC oscillator selection
This option bit enables selection of the internal RC oscillator.
0: RC oscillator on
4 OSC
1: RC oscillator off
Note: To improve clock stability and frequency accuracy when the RC
( s )
ct
oscillator is selected, it is recommended to place a decoupling
capacitor, typically 100 nF, between the VDD and VSS pins as close as
possible to the ST7 device.
d u
Low voltage selection
r o
3:2 LVD[1:0] selected threshold to the LVD and AVD:
e P
These option bits enable the voltage detection block (LVD and AVD) with a

11: LVD off

l e t
10: LVD on (highest voltage threshold)
Hardware or software watchdog
s o
1 WDGSW
b
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
O
0 WDGHALT -
Watchdog reset on halt

)
0: No reset generation when entering halt mode

c t (s
1: Reset generation when entering halt mode
1. Contact your local STMicroelectronics sales office.

d u
15.2.2 ROM option bytes
r o
P
Table 133. Option byte 0 description
e
l e t Bit Bit name Function

s o Auto wake up clock selection

0: 32 kHz oscillator (VLP) selected as AWU clock

O b 7 AWUCK 1: AWU RC oscillator selected as AWU clock.

Note: If this bit is reset, the internal RC oscillator must be selected
(option OSC = 0).

Doc ID 11928 Rev 8 217/234

 Device configuration and ordering information ST7L34 ST7L35 ST7L38 ST7L39

Table 133. Option byte 0 description

Bit Bit name Function
Oscillator range
When the internal RC oscillator is not selected (option OSC = 1),
these option bits select the range of the resonator oscillator current
source or the external clock source.
000: Typ. frequency range with resonator (LP) = 1~2 MHz
001: Typ. frequency range with resonator (MP) = 2~4 MHz)
010: Typ. frequency range with resonator (MS) = 4~8 MHz)
6:4 OSCRANGE[2:0] 011: Typ. frequency range with resonator (HS) = 8~16 MHz)
100: Typ. frequency range with resonator (VLP) = 32.768~ kHz)
101: External clock on OSC1
110: Reserved
111: External clock on PB4

( s )
ct
Note: OSCRANGE[2:0] has no effect when AWUCK option is set to 0.
In this case, the VLP oscillator range is automatically selected
as AWU clock

d u
3:2 - Reserved, must be set to 1
Readout protection for ROM r o
1 ROP_R
e P
This option is for read protection of ROM
0: Readout protection off
1: Readout protection on
l e t
o
Readout protection for data EEPROM
s
0 ROP_D

O b
This option is for read protection of EEPROM memory.
0: Readout protection off

) -
1: Readout protection on

t(s
Table 134. Option byte 1 description
c
Bit Bit name
u Function
7
od - Reserved, must be set to 1(1)

Pr
PLL disable
This option bit enables or disables the PLL.

e t e 6 PLLOFF
0: PLL enabled

ol
1: PLL disabled (bypassed)
5 - Reserved, must be set to 0(1)

b s RC oscillator selection

O This option bit enables selection of the internal RC oscillator.

0: RC oscillator on
1: RC oscillator off
4 OSC
Note: To improve clock stability and frequency accuracy when the RC
oscillator is selected, it is recommended to place a decoupling
capacitor, typically 100 nF, between the VDD and VSS pins as
close as possible to the ST7 device.
Low voltage selection
These option bits enable the voltage detection block (LVD and AVD)
3:2 LVD[1:0] with a selected threshold to the LVD and AVD:
11: LVD off
10: LVD on (highest voltage threshold)

218/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Device configuration and ordering information

Table 134. Option byte 1 description

Bit Bit name Function
Hardware or software watchdog
1 WDGSW 0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Watchdog reset on halt
0 WDGHALT 0: No reset generation when entering halt mode
1: Reset generation when entering halt mode
1. Contact your STMicroelectronics support

15.3 Device ordering information and transfer of customer code

( s )
ct
Customer code is made up of the ROM/FASTROM contents and the list of the selected
options (if any). The ROM/FASTROM contents are to be sent on a diskette or by electronic
u
means, with the S19 hexadecimal file generated by the development tool. All unused bytes
d
the correctly completed option list appended on page 223.
r o
must be set to FFh. The selected options are communicated to STMicroelectronics using

P
Refer to application note AN1635 for information on the counter listing returned by ST after
e
code has been transferred.

l e t
on contractual points.
s o
The STMicroelectronics Sales Organization will be pleased to provide detailed information

O b
) -
c t (s
d u
r o
e P
l e t
s o
O b

Doc ID 11928 Rev 8 219/234

 Device configuration and ordering information ST7L34 ST7L35 ST7L38 ST7L39

Figure 107. ST7FL3x Flash commercial product structure

Example: ST7 F L34 F 2 M A X S

Product class
ST7 microcontroller

Family type
F = Flash

Sub-family type
L34 = without data EEPROM, without LIN
L35 = without data EEPROM, with LIN

( s )
ct
L38 = with data EEPROM, without LIN
L39 = with data EEPROM, with LIN

d u
Pin count
F = 20 pins
r o
Program memory size
e P
2 = 8 Kbytes

l e t
Package type
M = SO
s o
U = QFN
O b
Temperature range

) -
(s
A = -40 °C to 85 °C
C = -40 °C to 125 °C
c t
d u
Tape and Reel conditioning options (left blank if Tray)
TR or R = Pin 1 left-oriented

r o
TX or X = Pin 1 right-oriented (EIA 481-C compliant)

e P ECOPACK/Fab code

l e t Blank or E = Lead-free ECOPACK® Phoenix Fab

s o S = Lead-free ECOPACK® Catania Fab

O b
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest
to you.

220/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Device configuration and ordering information

Figure 108. ST7FL3x FASTROM commercial product structure

Example: ST7 P L34 M A /xxx X S

Product class
ST7 microcontroller

Family type
P = FASTROM

Sub-family type
L34 = without data EEPROM, without LIN
L35 = without data EEPROM, with LIN

( s )
ct
L38 = with data EEPROM, without LIN
L39 = with data EEPROM, with LIN

d u
Package type
M = SO
r o
U = QFN
e P
Temperature range

l e t
A = -40 °C to 85 °C
C = -40 °C to 125 °C
s o
Code name
Defined by
O b
STMicroelectronics.
) -
(s
Denotes ROM code, pinout

t
and program memory size.

c
d u
Tape and Reel conditioning options (left blank if Tray)

r o
TR or R = Pin 1 left-oriented

e PTX or X = Pin 1 right-oriented (EIA 481-C compliant)

l e t ECOPACK/Fab code
Blank or E = Lead-free ECOPACK® Phoenix Fab

s o S = Lead-free ECOPACK® Catania Fab

O b

Doc ID 11928 Rev 8 221/234

 Device configuration and ordering information ST7L34 ST7L35 ST7L38 ST7L39

Figure 109. ROM commercial product code structure

Example: ST7 L34 M A /xxx X S

Product class
ST7 microcontroller

Sub-family type
L34 = without data EEPROM, without LIN
L35 = without data EEPROM, with LIN
L38 = with data EEPROM, without LIN
L39 = with data EEPROM, with LIN

( s )
ct
Package type
M = SO
U = QFN
d u
Temperature range
r o
A = -40 °C to 85 °C
e P
C = -40 °C to 125 °C

l e t
Code name
s o
Defined by
STMicroelectronics.
O b
-
Denotes ROM code, pinout
and program memory size.

(s )
Tape and Reel conditioning options (left blank if Tray)

c t
TR or R = Pin 1 left-oriented

u
TX or X = Pin 1 right-oriented (EIA 481-C compliant)

d
r o
ECOPACK/Fab code

P
Blank or E = Lead-free ECOPACK® Phoenix Fab

e
l e t
S = Lead-free ECOPACK® Catania Fab

s o
O b

222/234 Doc ID 11928 Rev 8

ST7L34 ST7L35 ST7L38 ST7L39 Device configuration and ordering information

ST7L3 FASTROM and ROM microcontroller option list

(Last update: October 2007)

Customer: .....................................................................
Address: .....................................................................
.....................................................................
Contact: .....................................................................
Phone No: .....................................................................
Reference/FASTROM or ROM code: ...............................

The FASTROM/ROM code name is assigned by STMicroelectronics.

FASTROM/ROM code must be sent in .S19 format. .Hex extension cannot be processed.

Device type/memory size/package (check only one option):

---------------------------------------------------------------------------------------------
FASTROM device 8K | SO20 | QFN20
---------------------------------------------------------------------------------------------
| [ ] ST7PL34F2M | [ ] ST7PL34F2U
|
|
[ ] ST7PL35F2M |
[ ] ST7PL38F2M |
[ ] ST7PL35F2U
[ ] ST7PL38F2U

( s )
ct
| [ ] ST7PL39F2M | [ ] ST7PL39F2U
-----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
ROM device 8K | SO20 | QFN20
----------------------------------------------------------------------------------------------
d u
|
|
[ ] ST7L34F2M
[ ] ST7L35F2M
|
|
[ ] ST7L34F2U
[ ] ST7L35F2U
r o
|
|
[ ] ST7L38F2M
[ ] ST7L39F2M
|
|
[ ] ST7L38F2U
[ ] ST7L39F2U
-----------------------------------------------------------------------------------------------
e P
Conditioning:
(check only one option)
[ ] Tape and reel [ ] Tube

l e t
Special marking: [ ] No
s o
[ ] Yes ".........................."

Maximum character count: SO20 (8 char. max): ..........................

O b
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
QFN20 (8 char. max): ..........................

)-
Temperature range: [ ] A (-40 to +85 °C) [ ] C (-40 to +125 °C)
AWUCK selection: [ ] 32 kHz oscillator [ ] AWU RC oscillator
Clock source selection:

t ( s
[ ] Resonator [ ] VLP: Very low power resonator (32 to 100 kHz)
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)

c [ ] MS: Medium speed resonator (4 to 8 MHz)

du
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] External clock [ ] on PB4
[ ] on OSCI

PLL:
r o
LVD reset threshold:
[ ] Internal RC oscillator
[ ] Disabled
[ ] Disabled
[ ] Enabled
[ ] Enabled (highest voltage threshold)

P
Watchdog selection:
Watchdog reset on halt:

e
[ ] Software activation
[ ] Disabled
[ ] Hardware activation
[ ] Enabled

l e t Flash devices only:

Sector 0 size: [ ] 0.5 K []1K []2K []4K

o
Readout protection: [ ] Disabled [ ] Enabled
Flash write protection: [ ] Disabled [ ] Enabled

b s ROM devices only

ROM readout protection: [ ] Disabled [ ] Enabled

O EEDATA readout protection:[ ] Disabled

Comments:
Supply operating range in the application:
[ ] Enabled

.............................
.............................
Notes: .............................
Date: .............................
Signature: ...........................

1. Not all configurations are available. See Section 15.2: Option bytes on page 215 for authorized option byte
combinations.

Doc ID 11928 Rev 8 223/234

 Device configuration and ordering information ST7L34 ST7L35 ST7L38 ST7L39

15.4 Development tools

15.4.1 Starter Kits

ST offers complete, affordable starter kits. Starter kits are complete, affordable
hardware/software tool packages that include features and samples to help you quickly start
developing your application.

15.4.2 Development and debugging tools

Application development for ST7 is supported by fully optimizing C compilers and the ST7
assembler-linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your

s )
application. The cosmic C compiler is available in a free version that outputs up to 16 Kbytes
(
ct
of code.

effective ST7-DVP3 series emulators and the low-cost RLink in-circuit

d u
The range of hardware tools includes full featured ST7-EMU3 series emulators, cost

r
debugger/programmer. These tools are supported by the ST7 Toolset from
o
e P
STMicroelectronics, which includes the STVD7 integrated development environment (IDE)
with high-level language debugger, editor, project manager and integrated programming
interface.
l e t
15.4.3 Programming tools
s o
O b
During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the

on your application board.

) -
RLink provide in-circuit programming capability for programming the Flash microcontroller

t (s
ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as

c
ST7 socket boards which provide all the sockets required for programming any of the
u
devices in a specific ST7 subfamily on a platform that can be used with any tool with in-
d
o
circuit programming capability for ST7.
r
P
For production programming of ST7 devices, ST’s third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
e
l e t
into your production environment.

s o
O b

224/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Device configuration and ordering information

15.4.4 Order codes for development and programming tools

Table 135 below lists the ordering codes for the ST7L3x development and programming
tools. For additional ordering codes for spare parts and accessories, refer to the online
product selector at www.st.com/mcu.

Table 135. ST7L3 development and programming tools

In-circuit debugger,
Emulator Programming tool
RLink series(1)
Supported
products Starter kit Starter kit ST socket
EMU In-circuit
with demo without DVP series boards and
series programmer
board demo board EPBs

ST7FL34
( s )
ct
ST7FL35 ST7-STICK
ST7FLITE- STX- ST7MDT10- ST7MDT10 ST7SB10-
ST7FL38 SK/RAIS(2)(3) RLINK(2)(3) DVP3(4) -EMU3

d u
STX-RLINK
(4)(5) 123(4)

ST7FL39
r o
1. Available from ST or from Raisonance

e P
2. USB connection to PC
3. Parallel port connection to PC
l e t
o
4. Add suffix /EU, /UK or /US for the power supply for your region

s
b
5. Includes connection kit for DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool
selection guide for connection kit ordering information

O
) -
c t (s
d u
r o
e P
l e t
s o
O b

Doc ID 11928 Rev 8 225/234

 Important notes ST7L34 ST7L35 ST7L38 ST7L39

16 Important notes

16.1 Clearing active interrupts outside interrupt routine

When an active interrupt request occurs at the same time as the related flag or interrupt
mask is being cleared, the CC register may be corrupted.

Concurrent interrupt context

The symptom does not occur when the interrupts are handled normally, that is, when:
● The interrupt request is cleared (flag reset or interrupt mask) within its own interrupt
routine
●
s )
The interrupt request is cleared (flag reset or interrupt mask) within any interrupt
(
ct
routine
●
u
The interrupt request is cleared (flag reset or interrupt mask) in any part of the code
while this interrupt is disabled
d
r o
If these conditions are not met, the symptom is avoided by implementing the following
sequence:

e P
Example:
l e t
Perform SIM and RIM operation before and after resetting an active interrupt request.

● SIM
s o
●
●
Reset flag or interrupt mask
RIM
O b
) -
LINSCI limitations(s
16.2
c t
16.2.1
d u
Header time-out does not prevent wake-up from mute mode
r o
P
Normally, when LINSCI is configured in LIN slave mode, if a header time-out occurs during a
LIN header reception (that is, header length > 57 bits), the LIN header error bit (LHE) is set,
e
l e t
an interrupt occurs to inform the application but the LINSCI should stay in mute mode,
waiting for the next header reception.

s o Problem description

O b The LINSCI sampling period is Tbit/16. If a LIN header time-out occurs between the 9th and
the 15th sample of the identifier field stop bit (refer to Figure 110), the LINSCI wakes up
from mute mode. Nevertheless, LHE is set and LIN header detection flag (LHDF) is kept
cleared.
In addition, if LHE is reset by software before this 15th sample (by accessing the SCISR
register and reading the SCIDR register in the LINSCI interrupt routine), the LINSCI will
generate another LINSCI interrupt (due to the RDRF flag setting).

226/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Important notes

Figure 110. Header reception event sequence

LIN synch LIN synch Identifier

break field field

THEADER
ID field STOP bit
Critical
window

Active mode is set

(RWU is cleared) RDRF flag is set

Impact on application
( s )
Software may execute the interrupt routine twice after header reception.
u ct
d
Moreover, in reception mode, as the receiver is no longer in mute mode, an interrupt is

o
generated on each data byte reception.
Workaround
P r
t e
The problem can be detected in the LINSCI interrupt routine. In case of time-out error (LHE
e
o l
is set and LHLR is loaded with 00h), the software can check the RWU bit in the SCICR2
register. If RWU is cleared, it can be set by software (refer to Figure 111). The workaround is
shown in bold characters.
b s
Figure 111. LINSCI interrupt routine
- O
{
(s )
@interrupt void LINSCI_IT ( void ) /* LINSCI interrupt routine */

c t
/* clear flags */
SCISR_buffer = SCISR;

u
SCIDR_buffer = SCIDR;

d
{
r o
if ( SCISR_buffer & LHE )/* header error ? */

e P if (!LHLR)/* header time-out? */

{
if ( !(SCICR2 & RWU) )/* active mode ? */

l e t {
_asm("sim");/* disable interrupts */

s o SCISR;
SCIDR;/* Clear RDRF flag */

b
SCICR2 |= RWU;/* set mute mode */
SCISR;

O }
SCIDR;/* Clear RDRF flag */
SCICR2 |= RWU;/* set mute mode */
_asm("rim");/* enable interrupts */

}
}
}
Example using Cosmic compiler syntax

Doc ID 11928 Rev 8 227/234

 Revision history ST7L34 ST7L35 ST7L38 ST7L39

17 Revision history

Table 136. Revision history

Date Revision Changes

Jun-2004 1 First release

Changed temperature range (added -40 to +125°C)
Removed references to 1% internal RC accuracy; Changed Figure 4:
Memory map on page 19
Removed reference to amplifier for ADCDRL in Table 3: Hardware

s )
register map on page 20 and in Section 11.6.6: Register description
on page 166 and replaced “Data register low” by “Control and data
(
ct
register low”; Changed Section 4.4: ICC interface on page 23 and
added note 6

Internal RC oscillator adjustment on page 37

d u
Modified note on clock stability and on ICC mode in Section 7.1:

r o
Added text in note 1 in Table 7: RCCR calibration registers on page 37

clock management on page 37)

e P
Added RCCR1 (Figure 4 on page 19 and Section 7: Supply, reset and

l e t
Added note to Section 7.5: Reset sequence manager (RSM) on
page 42; Added note 3 after Table 24: I/O port mode options on
page 70
s o
Exit from halt mode during an overflow event set to ‘no’ in

O b
Section 11.2.4: Low power modes on page 88
Removed watchdog section in Section 11.3: Lite timer 2 (LT2) on

) -
page 101
Table 48: Effect of low power modes on lite timer 2 on page 104 and

23-Dec-2005
c2t (s
Table 49: Lite timer 2 interrupt control/wake-up capability on page 104
expanded

du Added important note in Master mode operation on page 111

Changed procedure description in Transmitter on page 126

r o In Extended baud rate generation on page 130: Corrected equation

e P for Rx to read: Rx = fCPU/(16 x ERPR x PR x RR), {instead of Rx =

fCPU/(16 x ERPR x PR x TR)}

l e t Added note on illegal opcode reset to Section 12.2.2: Illegal opcode

reset on page 175; Changed Section 13.1.2: Typical values on

s o page 178
Changed electrical characteristics in the following sections:

O b Section 13.3: Operating conditions on page 182, Section 13.4: Supply

current characteristics on page 189, Section 13.6: Memory
characteristics on page 195, Section 13.7.3: Absolute maximum
ratings (electrical sensitivity) on page 198, Section 13.8: I/O port pin
characteristics on page 199, Section 13.9: Control pin characteristics
on page 205, Section 13.10: Communication interface characteristics
on page 207 and Section 13.11: 10-bit ADC characteristics on
page 210
Modified Section 14: Package characteristics on page 212
Changed Section 15.2: Option bytes on page 215 (OPT 5 of option
byte 1), Section 15.3: Device ordering information and transfer of
customer code on page 219 and Section 15.4: Development tools on
page 224
Changed option list, Added Section 16: Important notes on page 226

228/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Revision history

Table 136. Revision history (continued)

Date Revision Changes

Removed all x4 PLL option references from document

Changed Read operation section in Section 5.3: Memory access on
page 28
Changed note Figure 8: Data EEPROM write operation on page 29.
Changed Section 5.5: Access error handling on page 30
Replaced 3.3 V with 3.6 V in Section 7.2: Phase locked loop on
page 38
Changed Master mode operation on page 111: added important note
Changed Section 13.1.2: Typical values on page 178
Changed Section 13.3.1: General operating conditions on page 182

the following figure: PLL ΔfCPU/fCPU vs time

( s )
and added note on clock stability and frequency accuracy; removed

ct
Changed Section 13.3.2: Operating conditions with low voltage
detector (LVD) on page 186 and Section 13.3.4: Internal RC oscillator
and PLL on page 188
d u
notes
r o
Changed Section 13.4.1: Supply current on page 189 and added

page 196
e P
Changed Table 115: Characteristics of EEPROM data memory on

page 195
l e t
Removed note 6 from Section 13.6: Memory characteristics on

06-Mar-2006 3 o
Changed Section 13.6.2: Flash program memory on page 195;
s
Changed Section 13.6.3: EEPROM data memory on page 196

on page 197
O b
Changed values in Section 13.7.2: Electromagnetic interference (EMI)

-
Changed absolute maximum ratings in Table 118: ESD absolute
)
(s
maximum ratings on page 198

c t Changed Section 13.8.1: General characteristics on page 199 and

Section 13.8.2: Output driving current on page 200

d u Changed Section 13.9.1: Asynchronous RESET pin on page 205

(changed values, removed references to 3 V and added note 5)

r o Changed Section 13.11: 10-bit ADC characteristics on page 210:

e P changed values in ADC accuracy tables and added note 3

Changed notes in Section 14.3: Thermal characteristics on page 214

l e t Changed Section 15: Device configuration and ordering information

on page 215

s o Changed Table 130: Soldering compatibility (wave and reflow

soldering process) on page 208

O b Added note to OSC option bit in Section 15.2: Option bytes on

page 215
Changed configuration of bit 7, option byte 1, in Table 130: Flash and
ROM option bytes on page 215
Changed device type/memory size/package and PLL options in
ST7L1 FASTROM and ROM microcontroller option list on page 257.

Doc ID 11928 Rev 8 229/234

 Revision history ST7L34 ST7L35 ST7L38 ST7L39

Table 136. Revision history (continued)

Date Revision Changes

Changed caution text in Section 8.2: External interrupts on page 51

Changed external interrupt function in Section 10.2.1: Input modes on
page 68
Changed Table 101 and Table 102
Changed Table 103 and Table 104
Changed Figure 98: RESET pin protection when LVD Is enabled on
17-Mar-2006 4
page 206
Removed EMC protective circuitry in Figure 97: RESET pin protection
when LVD is disabled on page 206 (device works correctly without
these components)
Removed section ‘LINSCI wrong break duration’ from Section 16:
Important notes on page 226

( s )
ct
Replaced ‘ST7L3’ with ‘ST7L34, ST7L35, ST7L38, ST7L39’ in

cover page.
d u
document name and added QFN20 package to package outline on

Changed Section 1: Description on page 14

r o
Transferred device summary table from cover page to Section 1:
Description on page 14

e P
Description on page 14
l e t
Added QFN20 package to the device summary table in Section 1:

o
Figure 1: General block diagram on page 15: Replaced autoreload

b s
timer 2 with autoreload timer 3
Added Figure 3: 20-pin QFN package pinout on page 16 to Section 2

- O
Table 2: Device pin description on page 17:
- Added QFN20 package pin numbers

(s )
- Removed caution about PB0 and PB1 negative current injection
restriction

c t Figure 4: Memory map on page 19: Removed references to note 2

Table 3: Hardware register map on page 20:

du - Changed register name for LTCNTR

20-Dec-2006
r o 5
- Changed reset status of registers LTCSR1, ATCSR and SICSR
- Changed note 3

e P Changed last paragraph of Section 5.5: Access error handling on

page 30

l e t Added caution about avoiding unwanted behavior during reset

sequence in Section 7.5.1: Introduction on page 42

s o Figure 17: Reset sequences on page 45: Replaced ‘TCPU’ with ‘tCPU’

O b at bottom of figure
Changed notes in Section 7.6.1: Low voltage detector (LVD) on
page 45
Figure 19: Reset and supply management block diagram on page 47:
Removed names from SICSR bits 7:5
Changed reset value of bits CR0 and CR1 from 0 to 1 in Section 7.6.4:
Register description on page 48
Table 16: Interrupt sensitivity bits on page 54: Restored table number
(inadvertantly removed in Rev. 3)
Figure 34: Watchdog block diagram on page 75: Changed register
label
Changed register name and label in Section 11.1.6: Register
description on page 77
Added note for ROM devices only to PWM mode on page 79

230/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Revision history

Table 136. Revision history (continued)

Date Revision Changes

Replaced bit name OVIE1 with OVFIE1 in Table 35: AT3 interrupt
control/wake-up capability on page 89
Changed description of bits 11:0 in Counter register 1 high (CNTR1H)
on page 90, Counter register 1 low (CNTR1L) on page 90 and
Table 37: CNTR1H and CNTR1L register descriptions on page 91
Changed name of register ATR1H and ATR1L in Autoreload register
high (ATR1H), Autoreload register low (ATR1L) and Table 38: ATR1H
and ATR1L register descriptions on page 92
Changed name of register ATCSR2 in Timer control register2
(ATCSR2) and Table 44: ATCSR2 register description on page 97

s )
Changed name of register ATR2H and ATR2L in Autoreload register2
high (ATR2H), Autoreload register2 low (ATR2L) and Table 45: ATR2H
(
ct
and ATR2L register descriptions on page 98
Changed name of register LTCSR1 in Lite timer control/status register
u
(LTCSR1) and Table 53: LTCSR1 register description on page 106.
d
r o
Changed names of registers SPIDR, SPICR and SPICSR in
Section 11.4.8: Register description on page 118

- replaced ‘tCPU’ with ‘TCPU’

e P
Figure 64: LIN synch field measurement on page 148:

- replaced ‘tBR’ with ‘TBR’

l e t
Modified Table 98: Current characteristics on page 180:

s
- Changed IIO values
o
b
- Removed ‘Injected current on PB0 and PB1 pins’ from table
- Removed note 5 ‘no negative current injection allowed on PB0 and
PB1 pins’
O
20-Dec-2006
5
) -
Restored symbol for PLL jitter in Table 102: Operating conditions

(s
cont’d (tested for TA = -40 to +125 °C) @ VDD = 4.5 to 5.5 V on page 183

c t (inadvertantly changed in Rev. 4)

Added note 5 to Table 105: Operating conditions with low voltage

d u detector on page 186

Specified applicable TA in Table 113: RAM and hardware registers on

r o page 195, Table 114: Characteristics of dual voltage HDFlash

e P memory on page 195 and Table 115: Characteristics of EEPROM

data memory on page 196

l e t Changed TA for programming time for 1~32 bytes and changed TPROG
from 125°C to 85°C for write erase cycles in Table 114:

s o Characteristics of dual voltage HDFlash memory on page 195

Figure 84: Two typical applications with unused I/O pin on page 199:

O b Replaced ST7XXX with ST7

Table 121: Output driving current on page 200: Added table number
and title
Table 122: Asynchronous RESET pin on page 205: Added table
number and title
Replaced ST72XXX with ST7 in Figure 98: RESET pin protection
when LVD Is enabled on page 206 and Figure 97: RESET pin
protection when LVD is disabled on page 206
Changed Section 13.10.1: Serial peripheral interface (SPI) on
page 207
Figure 100: SPI slave timing diagram with CPHA = 1 on page 208:
Replaced CPHA = 0 with CPHA = 1
Figure 101: SPI master timing diagram on page 209: Repositioned
tv(MO) and th(MO)

Doc ID 11928 Rev 8 231/234

 Revision history ST7L34 ST7L35 ST7L38 ST7L39

Table 136. Revision history (continued)

Date Revision Changes

Table 124: 10-bit ADC characteristics on page 210: Added table

number and title
Changed PDmax value for SO20 package in Table 129: Thermal
characteristics on page 214
Removed text concerning LQFP, TQFP and SDIP packages from
Section 15: Device configuration and ordering information on
page 215.
Figure 102: Typical application with ADC on page 210: Replaced
ST72XXX with ST7
Changed typical and maximum values and added table number and
title to Table 125: ADC accuracy with 4.5 V < VDD < 5.5 V on

( s )
page 210 and to Table 126: ADC accuracy with 3 V < VDD < 3.6 V on

ct
page 211
Added Figure 105: QFN 5x6, 20-terminal very thin fine pitch quad flat
no-lead package on page 213
d u
page 214
r o
Added QFN20 package to Table 129: Thermal characteristics on

process) on page 208:

e P
Table 130: Soldering compatibility (wave and reflow soldering

e t
- Changed title of ‘Plating material’ column
- Added QFN package
l
20-Dec-2006
5
s o
- Removed note concerning Pb-package temperature for leadfree
cont’d
b
soldering compatibility
Changed Section 15.2: Option bytes on page 215 to add different
O
configurations between Flash and ROM devices for OPTION BYTE 0

) -
Removed ‘automotive’ from title of Section 15.3: Device ordering

(s
information and transfer of customer code on page 219

c t Removed ‘Supported part numbers’ table from Section 15.3: Device

ordering information and transfer of customer code on page 219

du Added Figure 107: ST7FL3x Flash commercial product structure on

page 220

r o Added Table 135: Flash user programmable device types on page 213

e P Added Figure 108: ST7FL3x FASTROM commercial product structure

on page 221

l e t Added Table 136: FASTROM factory coded device types on page 215
Added Figure 109: ROM commercial product code structure on

s o page 222
Added Table 137: ROM factory coded device types on page 216

O b Updated ST7L3 FASTROM and ROM microcontroller option list on

page 223
Changed Section 15.4: Development tools on page 224 and
Table 135: ST7L3 development and programming tools on page 225
Updated disclaimer (last page) to include a mention about the use of
STproducts in automotive applications
Changed the description of internal RC oscillator from ‘high precision’
to ‘1% in Clock, reset and supply management on cover page and in
Section 7.4.3: Internal RC oscillator on page 41
Table 7: RCCR calibration registers on page 37: Added footnote 2
02-Aug-2010 6
Section 7.6.1: Low voltage detector (LVD) on page 45: Changed the
sentence about the LVD to read that it can be enabled with ‘highest
voltage threshold’ instead of ‘low, medium or high’
Figure 26: Halt mode flowchart on page 60: Added footnote 5

232/234 Doc ID 11928 Rev 8

 ST7L34 ST7L35 ST7L38 ST7L39 Revision history

Table 136. Revision history (continued)

Date Revision Changes

Figure 31: AWUFH mode flowchart on page 65: Added footnote 5

Table 101: Operating conditions (tested for TA = -40 to +125 °C) @
VDD = 4.5 to 5.5 V on page 183: Changed fRC and ACCRC Flash
values
Table 102: Operating conditions (tested for TA = -40 to +125 °C) @
VDD = 4.5 to 5.5 V on page 183: Changed ACCPLL ‘typical’ value
Table 103: Operating conditions (tested for TA = -40 to +125 °C) @
VDD = 3.0 to 3.6 V on page 184: Changed fRC and ACCRC Flash
6 values
02-Aug-2010 Table 118: ESD absolute maximum ratings on page 198: Changed
cont’d
values of VESD(HBM) and VESD(HBM).

s )
Table 132: Option byte 1 description on page 217: Added ‘must be set

(
ct
to 1’ to option bit 7 and ‘must be set to 0’ to option bit 5
Table 133: Option byte 0 description on page 217: Added ‘must be set
to 1’ to option bits 3:2

d u
r o
Updated Figure 107: ST7FL3x Flash commercial product structure,
Figure 108: ST7FL3x FASTROM commercial product structure and

P
Figure 109: ROM commercial product code structure

e
11-Oct-2010 7
l t
Updated fCLKIN test conditions and maximum values in Table 100:
e
General operating conditions and Figure 72: fCLKIN maximum

o
operating frequency vs VDD supply voltage
s
18-Nov-2011 8
b
Updated the maximum value of external clock frequency on CLKIN pin

O
(fCLKIN) when VDD = 3 to 3.3 V in Table 100: General operating

) -
conditions on page 182 and in Figure 72: fCLKIN maximum operating
frequency vs VDD supply voltage on page 182.

c t (s
d u
r o
e P
l e t
s o
O b

Doc ID 11928 Rev 8 233/234

 ST7L34 ST7L35 ST7L38 ST7L39

Please Read Carefully:

( s )
u ct
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time, without notice.

o d
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234/234 Doc ID 11928 Rev 8